src/soc/minerva/cli.py

   1 import argparse
   2 import warnings
   3 from nmigen import cli
   4
   5 from minerva.core import Minerva
   6
   7
   8 def main():
   9     parser = argparse.ArgumentParser(formatter_class=argparse.ArgumentDefaultsHelpFormatter)
  10
  11     parser.add_argument("--reset-addr",
  12             type=lambda s: int(s, 16), default="0x00000000",
  13             help="reset vector address")
  14
  15     parser.add_argument("--with-icache",
  16             default=False, action="store_true",
  17             help="enable the instruction cache")
  18     parser.add_argument("--with-dcache",
  19             default=False, action="store_true",
  20             help="enable the data cache")
  21     parser.add_argument("--with-muldiv",
  22             default=False, action="store_true",
  23             help="enable RV32M support")
  24     parser.add_argument("--with-debug",
  25             default=False, action="store_true",
  26             help="enable the Debug Module")
  27     parser.add_argument("--with-trigger",
  28             default=False, action="store_true",
  29             help="enable the Trigger Module")
  30     parser.add_argument("--with-rvfi",
  31             default=False, action="store_true",
  32             help="enable the riscv-formal interface")
  33
  34     icache_group = parser.add_argument_group("icache options")
  35     icache_group.add_argument("--icache-nways",
  36             type=int, choices=[1, 2], default=1,
  37             help="number of ways")
  38     icache_group.add_argument("--icache-nlines",
  39             type=int, default=128,
  40             help="number of lines")
  41     icache_group.add_argument("--icache-nwords",
  42             type=int, choices=[4, 8, 16], default=4,
  43             help="number of words in a line")
  44     icache_group.add_argument("--icache-base",
  45             type=lambda s: int(s, 16), default="0x00000000",
  46             help="base address")
  47     icache_group.add_argument("--icache-limit",
  48             type=lambda s: int(s, 16), default="0x80000000",
  49             help="limit address")
  50
  51     dcache_group = parser.add_argument_group("dcache options")
  52     dcache_group.add_argument("--dcache-nways",
  53             type=int, choices=[1, 2], default=1,
  54             help="number of ways")
  55     dcache_group.add_argument("--dcache-nlines",
  56             type=int, default=128,
  57             help="number of lines")
  58     dcache_group.add_argument("--dcache-nwords",
  59             type=int, choices=[4, 8, 16], default=4,
  60             help="number of words in a line")
  61     dcache_group.add_argument("--dcache-base",
  62             type=lambda s: int(s, 16), default="0x00000000",
  63             help="base address")
  64     dcache_group.add_argument("--dcache-limit",
  65             type=lambda s: int(s, 16), default="0x80000000",
  66             help="limit address")
  67
  68     trigger_group = parser.add_argument_group("trigger options")
  69     trigger_group.add_argument("--nb-triggers",
  70             type=int, default=8,
  71             help="number of triggers")
  72
  73     cli.main_parser(parser)
  74
  75     args = parser.parse_args()
  76
  77     if args.with_debug and not args.with_trigger:
  78         warnings.warn("Support for hardware breakpoints requires --with-trigger")
  79
  80     cpu = Minerva(args.reset_addr,
  81             args.with_icache, args.icache_nways, args.icache_nlines, args.icache_nwords,
  82             args.icache_base, args.icache_limit,
  83             args.with_dcache, args.dcache_nways, args.dcache_nlines, args.dcache_nwords,
  84             args.dcache_base, args.dcache_limit,
  85             args.with_muldiv,
  86             args.with_debug,
  87             args.with_trigger, args.nb_triggers,
  88             args.with_rvfi)
  89
  90     ports = [
  91         cpu.external_interrupt, cpu.timer_interrupt, cpu.software_interrupt,
  92         cpu.ibus.ack, cpu.ibus.adr, cpu.ibus.bte, cpu.ibus.cti, cpu.ibus.cyc, cpu.ibus.dat_r,
  93         cpu.ibus.dat_w, cpu.ibus.sel, cpu.ibus.stb, cpu.ibus.we, cpu.ibus.err,
  94         cpu.dbus.ack, cpu.dbus.adr, cpu.dbus.bte, cpu.dbus.cti, cpu.dbus.cyc, cpu.dbus.dat_r,
  95         cpu.dbus.dat_w, cpu.dbus.sel, cpu.dbus.stb, cpu.dbus.we, cpu.dbus.err
  96     ]
  97
  98     if args.with_debug:
  99         ports += [cpu.jtag.tck, cpu.jtag.tdi, cpu.jtag.tdo, cpu.jtag.tms]
 100
 101     if args.with_rvfi:
 102         ports += [
 103             cpu.rvfi.valid, cpu.rvfi.order, cpu.rvfi.insn, cpu.rvfi.trap, cpu.rvfi.halt,
 104             cpu.rvfi.intr, cpu.rvfi.mode, cpu.rvfi.ixl, cpu.rvfi.rs1_addr, cpu.rvfi.rs2_addr,
 105             cpu.rvfi.rs1_rdata, cpu.rvfi.rs2_rdata, cpu.rvfi.rd_addr, cpu.rvfi.rd_wdata,
 106             cpu.rvfi.pc_rdata, cpu.rvfi.pc_wdata, cpu.rvfi.mem_addr, cpu.rvfi.mem_rmask,
 107             cpu.rvfi.mem_wmask, cpu.rvfi.mem_rdata, cpu.rvfi.mem_wdata
 108         ]
 109
 110     cli.main_runner(parser, args, cpu, name="minerva_cpu", ports=ports)
 111
 112
 113 if __name__ == "__main__":
 114     main()