src/soc/minerva/units/debug/jtag.py

   1 from nmigen.hdl.rec import DIR_FANIN, DIR_FANOUT
   2
   3
   4 __all__ = ["jtag_layout", "JTAGReg", "dtmcs_layout", "dmi_layout"]
   5
   6
   7 jtag_layout = [
   8     ("tck",  1, DIR_FANIN),
   9     ("tdi",  1, DIR_FANIN),
  10     ("tdo",  1, DIR_FANOUT),
  11     ("tms",  1, DIR_FANIN),
  12     ("trst", 1, DIR_FANIN) # TODO
  13 ]
  14
  15
  16 class JTAGReg:
  17     BYPASS = 0x00
  18     IDCODE = 0x01
  19     DTMCS  = 0x10
  20     DMI    = 0x11
  21
  22
  23 # JTAG register layouts
  24
  25 dtmcs_layout = [
  26     ("version",       4),
  27     ("abits",         6),
  28     ("dmistat",       2),
  29     ("idle",          3),
  30     ("zero0",         1),
  31     ("dmireset",      1),
  32     ("dmihardreset",  1),
  33     ("zero1",        14)
  34 ]
  35
  36
  37 dmi_layout = [
  38     ("op",    2),
  39     ("data", 32),
  40     ("addr",  6)
  41 ]