src/soc/minerva/units/debug/top.py

   1 from nmigen import *
   2 from nmigen.hdl.rec import *
   3
   4
   5 from ...csr import *
   6 from ...isa import *
   7 from ...wishbone import wishbone_layout
   8 from .controller import *
   9 from .dmi import *
  10 from .jtag import *
  11 from .regfile import *
  12 from .wbmaster import *
  13
  14
  15 __all__ = ["DebugUnit"]
  16
  17
  18 jtag_regs = {
  19     JTAGReg.IDCODE: [("value", 32)],
  20     JTAGReg.DTMCS:  dtmcs_layout,
  21     JTAGReg.DMI:    dmi_layout
  22 }
  23
  24
  25 class DebugUnit(Elaboratable, AutoCSR):
  26     def __init__(self):
  27         self.jtag = Record(jtag_layout)
  28         self.dbus = Record(wishbone_layout)
  29
  30         self.trigger_haltreq = Signal()
  31
  32         self.x_ebreak = Signal()
  33         self.x_pc = Signal(32)
  34         self.x_stall = Signal()
  35
  36         self.m_branch_taken = Signal()
  37         self.m_branch_target = Signal(32)
  38         self.m_mret = Signal()
  39         self.m_exception = Signal()
  40         self.m_pc = Signal(32)
  41         self.m_valid = Signal()
  42         self.mepc_r_base = Signal(30)
  43         self.mtvec_r_base = Signal(30)
  44
  45         self.dcsr_step = Signal()
  46         self.dcsr_ebreakm = Signal()
  47         self.dpc_value = Signal(32)
  48
  49         self.halt = Signal()
  50         self.halted = Signal()
  51         self.killall = Signal()
  52         self.resumereq = Signal()
  53         self.resumeack = Signal()
  54
  55         self.dbus_busy = Signal()
  56
  57         self.csrf_addr = Signal(12)
  58         self.csrf_re = Signal()
  59         self.csrf_dat_r = Signal(32)
  60         self.csrf_we = Signal()
  61         self.csrf_dat_w = Signal(32)
  62
  63         self.gprf_addr = Signal(5)
  64         self.gprf_re = Signal()
  65         self.gprf_dat_r = Signal(32)
  66         self.gprf_we = Signal()
  67         self.gprf_dat_w = Signal(32)
  68
  69     def elaborate(self, platform):
  70         m = Module()
  71
  72         from jtagtap import JTAGTap
  73         tap        = m.submodules.tap        = JTAGTap(jtag_regs)
  74         regfile    = m.submodules.regfile    = DebugRegisterFile(tap.regs[JTAGReg.DMI])
  75         controller = m.submodules.controller = DebugController(regfile)
  76         wbmaster   = m.submodules.wbmaster   = DebugWishboneMaster(regfile)
  77
  78         m.d.comb += [
  79             tap.port.connect(self.jtag),
  80             tap.regs[JTAGReg.IDCODE].r.eq(0x10e31913), # Usurpate a Spike core for now.
  81             tap.regs[JTAGReg.DTMCS].r.eq(0x61) # (abits=6, version=1) TODO
  82         ]
  83
  84         m.d.comb += [
  85             controller.trigger_haltreq.eq(self.trigger_haltreq),
  86
  87             controller.x_ebreak.eq(self.x_ebreak),
  88             controller.x_pc.eq(self.x_pc),
  89             controller.x_stall.eq(self.x_stall),
  90
  91             controller.m_branch_taken.eq(self.m_branch_taken),
  92             controller.m_branch_target.eq(self.m_branch_target),
  93             controller.m_pc.eq(self.m_pc),
  94             controller.m_valid.eq(self.m_valid),
  95
  96             self.halt.eq(controller.halt),
  97             controller.halted.eq(self.halted),
  98             self.killall.eq(controller.killall),
  99             self.resumereq.eq(controller.resumereq),
 100             controller.resumeack.eq(self.resumeack),
 101
 102             self.dcsr_step.eq(controller.dcsr.r.step),
 103             self.dcsr_ebreakm.eq(controller.dcsr.r.ebreakm),
 104             self.dpc_value.eq(controller.dpc.r.value),
 105
 106             self.csrf_addr.eq(controller.csrf_addr),
 107             self.csrf_re.eq(controller.csrf_re),
 108             controller.csrf_dat_r.eq(self.csrf_dat_r),
 109             self.csrf_we.eq(controller.csrf_we),
 110             self.csrf_dat_w.eq(controller.csrf_dat_w),
 111
 112             self.gprf_addr.eq(controller.gprf_addr),
 113             self.gprf_re.eq(controller.gprf_re),
 114             controller.gprf_dat_r.eq(self.gprf_dat_r),
 115             self.gprf_we.eq(controller.gprf_we),
 116             self.gprf_dat_w.eq(controller.gprf_dat_w),
 117         ]
 118
 119         m.d.comb += [
 120             wbmaster.bus.connect(self.dbus),
 121             self.dbus_busy.eq(wbmaster.dbus_busy)
 122         ]
 123
 124         return m