src/soc/regfile/regfiles.py

   1 # POWER9 Register Files
   2 """POWER9 regfiles
   3
   4 Defines the following register files:
   5
   6     * INT regfile   - 32x 64-bit
   7     * SPR regfile   - 110x 64-bit
   8     * CR regfile    - CR0-7
   9     * XER regfile   - XER.so, XER.ca/ca32, XER.ov/ov32
  10     * FAST regfile  - PC, MSR, CTR, LR, TAR, SRR1, SRR2
  11
  12 Links:
  13
  14 * https://bugs.libre-soc.org/show_bug.cgi?id=345
  15 * https://bugs.libre-soc.org/show_bug.cgi?id=351
  16 * https://libre-soc.org/3d_gpu/architecture/regfile/
  17 * https://libre-soc.org/openpower/isatables/sprs.csv
  18 """
  19
  20 # TODO
  21
  22 from soc.regfile.regfile import RegFile, RegFileArray
  23 from soc.regfile.virtual_port import VirtualRegPort
  24 from soc.decoder.power_enums import SPR
  25
  26
  27 # Integer Regfile
  28 class IntRegs(RegFileArray):
  29     """IntRegs
  30
  31     * QTY 32of 64-bit registers
  32     * 3R2W
  33     * Array-based unary-indexed (not binary-indexed)
  34     * write-through capability (read on same cycle as write)
  35     """
  36     def __init__(self):
  37         super().__init__(64, 32)
  38         self.w_ports = [self.write_port("dest1"),
  39                         self.write_port("dest2")] # for now (LD/ST update)
  40         self.r_ports = [self.read_port("src1"),
  41                         self.read_port("src2"),
  42                         self.read_port("src3")]
  43
  44
  45 # Fast SPRs Regfile
  46 class FastRegs(RegFileArray):
  47     """FastRegs
  48
  49     FAST regfile  - PC, MSR, CTR, LR, TAR, SRR1, SRR2
  50
  51     * QTY 8of 64-bit registers
  52     * 3R2W
  53     * Array-based unary-indexed (not binary-indexed)
  54     * write-through capability (read on same cycle as write)
  55     """
  56     PC = 0
  57     MSR = 1
  58     CTR = 2
  59     LR = 3
  60     TAR = 4
  61     SRR0 = 5
  62     SRR1 = 6
  63     def __init__(self):
  64         super().__init__(64, 8)
  65         self.w_ports = [self.write_port("dest1"),
  66                         self.write_port("dest2"),
  67                         self.write_port("dest3")]
  68         self.r_ports = [self.read_port("src1"),
  69                         self.read_port("src2"),
  70                         self.read_port("src3")]
  71
  72
  73 # CR Regfile
  74 class CRRegs(VirtualRegPort):
  75     """Condition Code Registers (CR0-7)
  76
  77     * QTY 8of 8-bit registers
  78     * 3R1W 4-bit-wide with additional 1R1W for the "full" 32-bit width
  79     * Array-based unary-indexed (not binary-indexed)
  80     * write-through capability (read on same cycle as write)
  81     """
  82     def __init__(self):
  83         super().__init__(32, 8)
  84         self.w_ports = [self.full_wr, # 32-bit wide (masked, 8-en lines)
  85                         self.write_port("dest1"), # 4-bit wide, unary-indexed
  86                         self.write_port("dest2")] # 4-bit wide, unary-indexed
  87         self.r_ports = [self.full_rd, # 32-bit wide (masked, 8-en lines)
  88                         self.read_port("src1"),
  89                         self.read_port("src2"),
  90                         self.read_port("src3")]
  91
  92
  93 # XER Regfile
  94 class XERRegs(VirtualRegPort):
  95     """XER Registers (SO, CA/CA32, OV/OV32)
  96
  97     * QTY 3of 2-bit registers
  98     * 3R3W 2-bit-wide with additional 1R1W for the "full" 6-bit width
  99     * Array-based unary-indexed (not binary-indexed)
 100     * write-through capability (read on same cycle as write)
 101     """
 102     SO=0 # this is actually 2-bit but we ignore 1 bit of it
 103     CA=1 # CA and CA32
 104     OV=2 # OV and OV32
 105     def __init__(self):
 106         super().__init__(6, 3)
 107         self.w_ports = [self.full_wr, # 6-bit wide (masked, 3-en lines)
 108                         self.write_port("dest1"),
 109                         self.write_port("dest2"),
 110                         self.write_port("dest3")]
 111         self.r_ports = [self.full_rd, # 6-bit wide (masked, 3-en lines)
 112                         self.read_port("src1"),
 113                         self.read_port("src2"),
 114                         self.read_port("src3")]
 115
 116
 117 # SPR Regfile
 118 class SPRRegs(RegFile):
 119     """SPRRegs
 120
 121     * QTY len(SPRs) 64-bit registers
 122     * 1R1W
 123     * binary-indexed but REQUIRES MAPPING
 124     * write-through capability (read on same cycle as write)
 125     """
 126     def __init__(self):
 127         n_sprs = len(SPR)
 128         super().__init__(64, n_sprs)
 129         self.w_ports = [self.write_port(name="dest")]
 130         self.r_ports = [self.read_port("src")]
 131
 132
 133 # class containing all regfiles: int, cr, xer, fast, spr
 134 class RegFiles:
 135     def __init__(self):
 136         self.rf = {}
 137         for (name, kls) in [('int', IntRegs),
 138                             ('cr', CRRegs),
 139                             ('xer', XERRegs),
 140                             ('fast', FastRegs),
 141                             ('spr', SPRRegs),]:
 142             rf = self.rf[name] = kls()
 143             setattr(self, name, rf)
 144
 145     def elaborate_into(self, m, platform):
 146         for (name, rf) in self.rf.items():
 147             setattr(m.submodules, name, rf)
 148         return m
 149