src/soc/regfile/regfiles.py

   1 # POWER9 Register Files
   2 """POWER9 regfiles
   3
   4 Defines the following register files:
   5
   6     * INT regfile   - 32x 64-bit
   7     * SPR regfile   - 110x 64-bit
   8     * CR regfile    - CR0-7
   9     * XER regfile   - XER.so, XER.ca/ca32, XER.ov/ov32
  10     * FAST regfile  - PC, MSR, CTR, LR, TAR, SRR1, SRR2
  11
  12 Links:
  13
  14 * https://bugs.libre-soc.org/show_bug.cgi?id=345
  15 * https://bugs.libre-soc.org/show_bug.cgi?id=351
  16 * https://libre-soc.org/3d_gpu/architecture/regfile/
  17 * https://libre-soc.org/openpower/isatables/sprs.csv
  18 """
  19
  20 # TODO
  21
  22 from soc.regfile import RegFile, RegFileArray
  23 from soc.regfile.virtual_port import VirtualRegPort
  24 from soc.decoder.power_enums import SPR
  25
  26
  27 # Integer Regfile
  28 class IntRegs(RegFileArray):
  29     """IntRegs
  30
  31     * QTY 32of 64-bit registers
  32     * 3R1W
  33     * Array-based unary-indexed (not binary-indexed)
  34     * write-through capability (read on same cycle as write)
  35     """
  36     def __init__(self):
  37         super().__init__(64, 32)
  38         self.w_ports = [self.write_port("dest")]
  39         self.r_ports = [self.write_port("src1"),
  40                         self.write_port("src2"),
  41                         self.write_port("src3")]
  42
  43
  44 # CR Regfile
  45 class CRRegs(VirtualRegPort):
  46     """Condition Code Registers (CR0-7)
  47
  48     * QTY 8of 8-bit registers
  49     * 3R1W 4-bit-wide with additional 1R1W for the "full" 32-bit width
  50     * Array-based unary-indexed (not binary-indexed)
  51     * write-through capability (read on same cycle as write)
  52     """
  53     def __init__(self):
  54         super().__init__(32, 8)
  55         self.w_ports = [self.full_wr, # 32-bit wide (masked, 8-en lines)
  56                         self.write_port("dest")] # 4-bit wide, unary-indexed
  57         self.r_ports = [self.full_rd, # 32-bit wide (masked, 8-en lines)
  58                         self.write_port("src1"),
  59                         self.write_port("src2"),
  60                         self.write_port("src3")]
  61
  62
  63 # XER Regfile
  64 class XERRegs(VirtualRegPort):
  65     """XER Registers (SO, CA/CA32, OV/OV32)
  66
  67     * QTY 3of 2-bit registers
  68     * 3R3W 2-bit-wide with additional 1R1W for the "full" 6-bit width
  69     * Array-based unary-indexed (not binary-indexed)
  70     * write-through capability (read on same cycle as write)
  71     """
  72     def __init__(self):
  73         super().__init__(6, 2)
  74         self.w_ports = [self.full_wr, # 6-bit wide (masked, 3-en lines)
  75                         self.write_port("dest1"),
  76                         self.write_port("dest2",
  77                         self.write_port("dest3")]
  78         self.r_ports = [self.full_rd, # 6-bit wide (masked, 3-en lines)
  79                         self.write_port("src1"),
  80                         self.write_port("src2"),
  81                         self.write_port("src3")]
  82
  83
  84 # SPR Regfile
  85 class SPRRegs(RegFile):
  86     """SPRRegs
  87
  88     * QTY len(SPRs) 64-bit registers
  89     * 1R1W
  90     * binary-indexed but REQUIRES MAPPING
  91     * write-through capability (read on same cycle as write)
  92     """
  93     def __init__(self):
  94         n_sprs = len(SPR)
  95         super().__init__(64, n_sprs)
  96         self.w_ports = [self.write_port("dest")]
  97         self.r_ports = [self.write_port("src")]