src/soc/scoreboard/group_picker.py

   1 """ Group Picker: to select an instruction that is permitted to read (or write)
   2     based on the Function Unit expressing a *desire* to read (or write).
   3
   4     The job of the Group Picker is extremely simple yet extremely important.
   5     It sits in front of a register file port (read or write) and stops it from
   6     being corrupted.  It's a "port contention selector", basically.
   7
   8     The way it works is:
   9
  10     * Function Units need to read from (or write to) the register file,
  11       in order to get (or store) their operands, so they each have a signal,
  12       readable (or writable), which "expresses" this need.  This is an
  13       *unary* encoding.
  14
  15     * The Function Units also have a signal which indicates that they
  16       are requesting "release" of the register file port (this because
  17       in the scoreboard, readable/writable can be permanently HI even
  18       if the FU is idle, whereas the "release" signal is very specifically
  19       only HI if the read (or write) latch is still active)
  20
  21     * The Group Picker takes this unary encoding of the desire to read
  22       (or write) and, on a priority basis, activates one *and only* one
  23       of those signals, again as an unary output.
  24
  25     * Due to the way that the Computation Unit works, that signal (Go_Read
  26       or Go_Write) will fire for one (and only one) cycle, and can be used
  27       to enable the register file port read (or write) lines.  The Go_Read/Wr
  28       signal basically loops back to the Computation Unit and resets the
  29       "desire-to-read/write-expressing" latch.
  30
  31     In theory (and in practice!) the following is possible:
  32
  33     * Separate src1 and src2 Group Pickers.  This would allow instructions
  34       with only one operand to read to not block up other instructions,
  35       and it would also allow 3-operand instructions to be interleaved
  36       with 1 and 2 operand instructions.
  37
  38     * *Multiple* Group Pickers (multi-issue).  This would require
  39       a corresponding increase in the number of register file ports,
  40       either 4R2W (or more) or by "striping" the register file into
  41       split banks (a strategy best deployed on Vector Processors)
  42
  43 """
  44
  45 from nmigen.compat.sim import run_simulation
  46 from nmigen.cli import verilog, rtlil
  47 from nmigen import Module, Signal, Elaboratable, Array
  48
  49 #from nmutil.picker import MultiPriorityPicker as MPP
  50 from nmutil.picker import PriorityPicker
  51
  52
  53 class GroupPicker(Elaboratable):
  54     """ implements 10.5 mitch alsup group picker, p27
  55     """
  56     def __init__(self, wid, n_src, n_dst):
  57         self.n_src, self.n_dst = n_src, n_dst
  58         self.gp_wid = wid
  59
  60         # arrays
  61         rdr = []
  62         rd = []
  63         ri = []
  64         for i in range(n_src):
  65             rdr.append(Signal(wid, name="rdrel%d_i" % i, reset_less=True))
  66             rd.append(Signal(wid, name="gord%d_o" % i, reset_less=True))
  67             ri.append(Signal(wid, name="readable%d_i" % i, reset_less=True))
  68         wrr = []
  69         wr = []
  70         wi = []
  71         for i in range(n_dst):
  72             wrr.append(Signal(wid, name="reqrel%d_i" % i, reset_less=True))
  73             wr.append(Signal(wid, name="gowr%d_o" % i, reset_less=True))
  74             wi.append(Signal(wid, name="writable%d_i" % i, reset_less=True))
  75
  76         # inputs
  77         self.rd_rel_i = Array(rdr)  # go read in (top)
  78         self.req_rel_i = Array(wrr) # release request in (top)
  79         self.readable_i = Array(ri) # readable in (top)
  80         self.writable_i = Array(wi) # writable in (top)
  81
  82         # outputs
  83         self.go_rd_o = Array(rd)  # go read (bottom)
  84         self.go_wr_o = Array(wr)  # go write (bottom)
  85
  86     def elaborate(self, platform):
  87         m = Module()
  88
  89         # combine release (output ready signal) with writeable
  90         for i in range(self.n_dst):
  91             wpick = PriorityPicker(self.gp_wid)
  92             setattr(m.submodules, "wpick%d" % i, wpick)
  93             m.d.comb += wpick.i.eq(self.writable_i[i] & self.req_rel_i[i])
  94             m.d.comb += self.go_wr_o[i].eq(wpick.o)
  95
  96         for i in range(self.n_src):
  97             rpick = PriorityPicker(self.gp_wid)
  98             setattr(m.submodules, "rpick%d" % i, rpick)
  99             m.d.comb += rpick.i.eq(self.readable_i[i] & self.rd_rel_i[i])
 100             m.d.comb += self.go_rd_o[i].eq(rpick.o)
 101
 102         return m
 103
 104     def __iter__(self):
 105         yield from self.readable_i
 106         yield from self.writable_i
 107         yield from self.req_rel_i
 108         yield from self.rd_rel_i
 109         yield from self.go_rd_o
 110         yield from self.go_wr_o
 111
 112     def ports(self):
 113         return list(self)
 114
 115
 116 def grp_pick_sim(dut):
 117     yield dut.dest_i.eq(1)
 118     yield dut.issue_i.eq(1)
 119     yield
 120     yield dut.issue_i.eq(0)
 121     yield
 122     yield dut.src1_i.eq(1)
 123     yield dut.issue_i.eq(1)
 124     yield
 125     yield
 126     yield
 127     yield dut.issue_i.eq(0)
 128     yield
 129     yield dut.rd_rel_i.eq(1)
 130     yield
 131     yield dut.rd_rel_i.eq(0)
 132     yield
 133     yield dut.go_wr_i.eq(1)
 134     yield
 135     yield dut.go_wr_i.eq(0)
 136     yield
 137
 138
 139 def test_grp_pick():
 140     dut = GroupPicker(4, 2, 2)
 141     vl = rtlil.convert(dut, ports=dut.ports())
 142     with open("test_grp_pick.il", "w") as f:
 143         f.write(vl)
 144
 145     run_simulation(dut, grp_pick_sim(dut), vcd_name='test_grp_pick.vcd')
 146
 147 if __name__ == '__main__':
 148     test_grp_pick()