src/soc/scoremulti/fu_reg_matrix.py

   1 from nmigen.compat.sim import run_simulation
   2 from nmigen.cli import verilog, rtlil
   3 from nmigen import Module, Signal, Elaboratable, Array, Cat, Repl
   4
   5 from soc.scoremulti.dependence_cell import DependencyRow
   6 from soc.scoremulti.fu_wr_pending import FU_RW_Pend
   7 from soc.scoremulti.reg_sel import Reg_Rsv
   8 from soc.scoreboard.global_pending import GlobalPending
   9
  10 """
  11
  12  6600 Dependency Table Matrix inputs / outputs
  13  ---------------------------------------------
  14
  15                 d s1 s2 i  d s1 s2 i  d s1 s2 i  d s1 s2 i
  16                 | |   | |  | |   | |  | |   | |  | |   | |
  17                 v v   v v  v v   v v  v v   v v  v v   v v
  18  go_rd/go_wr -> dm-r0-fu0  dm-r1-fu0  dm-r2-fu0  dm-r3-fu0 -> wr/rd-pend
  19  go_rd/go_wr -> dm-r0-fu1  dm-r1-fu1  dm-r2-fu1  dm-r3-fu1 -> wr/rd-pend
  20  go_rd/go_wr -> dm-r0-fu2  dm-r1-fu2  dm-r2-fu2  dm-r3-fu2 -> wr/rd-pend
  21                  |  |  |    |  |  |    |  |  |    |  |  |
  22                  v  v  v    v  v  v    v  v  v    v  v  v
  23                  d  s1 s2   d  s1 s2   d  s1 s2   d  s1 s2
  24                  reg sel    reg sel    reg sel    reg sel
  25
  26 """
  27
  28 class FURegDepMatrix(Elaboratable):
  29     """ implements 11.4.7 mitch alsup FU-to-Reg Dependency Matrix, p26
  30     """
  31     def __init__(self, n_fu_row, n_reg_col, n_src, n_dest, cancel=None):
  32         self.n_src = n_src
  33         self.n_dest = n_dest
  34         self.n_fu_row = nf = n_fu_row      # Y (FUs)   ^v
  35         self.n_reg_col = n_reg = n_reg_col   # X (Regs)  <>
  36
  37         # arrays
  38         src = []
  39         rsel = []
  40         rd = []
  41         for i in range(n_src):
  42             j = i + 1 # name numbering to match src1/src2
  43             src.append(Signal(n_reg, name="src%d" % j, reset_less=True))
  44             rsel.append(Signal(n_reg, name="src%d_rsel_o" % j, reset_less=True))
  45             rd.append(Signal(nf, name="gord%d_i" % j, reset_less=True))
  46         dst = []
  47         dsel = []
  48         wr = []
  49         for i in range(n_src):
  50             j = i + 1 # name numbering to match src1/src2
  51             dst.append(Signal(n_reg, name="dst%d" % j, reset_less=True))
  52             dsel.append(Signal(n_reg, name="dst%d_rsel_o" % j, reset_less=True))
  53             wr.append(Signal(nf, name="gowr%d_i" % j, reset_less=True))
  54         wpnd = []
  55         pend = []
  56         for i in range(nf):
  57             j = i + 1 # name numbering to match src1/src2
  58             pend.append(Signal(nf, name="rd_src%d_pend_o" % j, reset_less=True))
  59             wpnd.append(Signal(nf, name="wr_dst%d_pend_o" % j, reset_less=True))
  60
  61         self.dest_i = Array(dst)     # Dest in (top)
  62         self.src_i = Array(src)      # oper in (top)
  63
  64         # cancellation array (from Address Matching), ties in with go_die_i
  65         self.cancel = cancel
  66
  67         # Register "Global" vectors for determining RaW and WaR hazards
  68         self.wr_pend_i = Signal(n_reg_col, reset_less=True) # wr pending (top)
  69         self.rd_pend_i = Signal(n_reg_col, reset_less=True) # rd pending (top)
  70         self.v_wr_rsel_o = Signal(n_reg_col, reset_less=True) # wr pending (bot)
  71         self.v_rd_rsel_o = Signal(n_reg_col, reset_less=True) # rd pending (bot)
  72
  73         self.issue_i = Signal(n_fu_row, reset_less=True)  # Issue in (top)
  74         self.go_wr_i = Array(wr)  # Go Write in (left)
  75         self.go_rd_i = Array(rd)  # Go Read in (left)
  76         self.go_die_i = Signal(n_fu_row, reset_less=True) # Go Die in (left)
  77
  78         # for Register File Select Lines (horizontal), per-reg
  79         self.dest_rsel_o = Array(dsel) # dest reg (bot)
  80         self.src_rsel_o = Array(rsel)  # src reg (bot)
  81
  82         # for Function Unit "forward progress" (vertical), per-FU
  83         self.wr_pend_o = Signal(n_fu_row, reset_less=True) # wr pending (right)
  84         self.wr_dst_pend_o = Array(wpnd) # dest pending
  85         self.rd_pend_o = Signal(n_fu_row, reset_less=True) # rd pending (right)
  86         self.rd_src_pend_o = Array(pend) # src1 pending
  87
  88     def elaborate(self, platform):
  89         m = Module()
  90         return self._elaborate(m, platform)
  91
  92     def _elaborate(self, m, platform):
  93
  94         # ---
  95         # matrix of dependency cells
  96         # ---
  97         cancel_mode = self.cancel is not None
  98         dm = Array(DependencyRow(self.n_reg_col, self.n_src,
  99                                  self.n_dest, cancel_mode) \
 100                     for r in range(self.n_fu_row))
 101         for fu in range(self.n_fu_row):
 102             setattr(m.submodules, "dr_fu%d" % fu, dm[fu])
 103
 104         # ---
 105         # array of Function Unit Pending vectors
 106         # ---
 107         fupend = Array(FU_RW_Pend(self.n_reg_col, self.n_src, self.n_dest) \
 108                         for f in range(self.n_fu_row))
 109         for fu in range(self.n_fu_row):
 110             setattr(m.submodules, "fu_fu%d" % (fu), fupend[fu])
 111
 112         # ---
 113         # array of Register Reservation vectors
 114         # ---
 115         regrsv = Array(Reg_Rsv(self.n_fu_row, self.n_src, self.n_dest) \
 116                         for r in range(self.n_reg_col))
 117         for rn in range(self.n_reg_col):
 118             setattr(m.submodules, "rr_r%d" % (rn), regrsv[rn])
 119
 120         # ---
 121         # connect Function Unit vector
 122         # ---
 123         wr_pend = []
 124         rd_pend = []
 125         for fu in range(self.n_fu_row):
 126             fup = fupend[fu]
 127             # accumulate FU Vector outputs
 128             wr_pend.append(fup.reg_wr_pend_o)
 129             rd_pend.append(fup.reg_rd_pend_o)
 130
 131         # ... and output them from this module (vertical, width=FUs)
 132         m.d.comb += self.wr_pend_o.eq(Cat(*wr_pend))
 133         m.d.comb += self.rd_pend_o.eq(Cat(*rd_pend))
 134
 135         # same for dest
 136         for i in range(self.n_dest):
 137             wr_dst_pend = []
 138             for fu in range(self.n_fu_row):
 139                 dc = dm[fu]
 140                 fup = fupend[fu]
 141                 dst_fwd_o = []
 142                 for rn in range(self.n_reg_col):
 143                     # accumulate cell fwd outputs for dest/src1/src2
 144                     dst_fwd_o.append(dc.dest_fwd_o[i][rn])
 145                 # connect cell fwd outputs to FU Vector in [Cat is gooood]
 146                 m.d.comb += [fup.dest_fwd_i[i].eq(Cat(*dst_fwd_o)),
 147                             ]
 148                 # accumulate FU Vector outputs
 149                 wr_dst_pend.append(fup.reg_wr_dst_pend_o[i])
 150             # ... and output them from this module (vertical, width=FUs)
 151             m.d.comb += self.wr_dst_pend_o[i].eq(Cat(*wr_dst_pend))
 152
 153         # same for src
 154         for i in range(self.n_src):
 155             rd_src_pend = []
 156             for fu in range(self.n_fu_row):
 157                 dc = dm[fu]
 158                 fup = fupend[fu]
 159                 src_fwd_o = []
 160                 for rn in range(self.n_reg_col):
 161                     # accumulate cell fwd outputs for dest/src1/src2
 162                     src_fwd_o.append(dc.src_fwd_o[i][rn])
 163                 # connect cell fwd outputs to FU Vector in [Cat is gooood]
 164                 m.d.comb += [fup.src_fwd_i[i].eq(Cat(*src_fwd_o)),
 165                             ]
 166                 # accumulate FU Vector outputs
 167                 rd_src_pend.append(fup.reg_rd_src_pend_o[i])
 168             # ... and output them from this module (vertical, width=FUs)
 169             m.d.comb += self.rd_src_pend_o[i].eq(Cat(*rd_src_pend))
 170
 171         # ---
 172         # connect Reg Selection vector
 173         # ---
 174         for i in range(self.n_dest):
 175             dest_rsel = []
 176             for rn in range(self.n_reg_col):
 177                 rsv = regrsv[rn]
 178                 dest_rsel_o = []
 179                 for fu in range(self.n_fu_row):
 180                     dc = dm[fu]
 181                     # accumulate cell reg-select outputs dest/src1/src2
 182                     dest_rsel_o.append(dc.dest_rsel_o[i][rn])
 183                 # connect cell reg-select outputs to Reg Vector In
 184                 m.d.comb += rsv.dest_rsel_i[i].eq(Cat(*dest_rsel_o)),
 185
 186                 # accumulate Reg-Sel Vector outputs
 187                 dest_rsel.append(rsv.dest_rsel_o[i])
 188
 189         # ... and output them from this module (horizontal, width=REGs)
 190         m.d.comb += self.dest_rsel_o[i].eq(Cat(*dest_rsel))
 191
 192         # same for src
 193         for i in range(self.n_src):
 194             src_rsel = []
 195             for rn in range(self.n_reg_col):
 196                 rsv = regrsv[rn]
 197                 src_rsel_o = []
 198                 for fu in range(self.n_fu_row):
 199                     dc = dm[fu]
 200                     # accumulate cell reg-select outputs dest/src1/src2
 201                     src_rsel_o.append(dc.src_rsel_o[i][rn])
 202                 # connect cell reg-select outputs to Reg Vector In
 203                 m.d.comb += rsv.src_rsel_i[i].eq(Cat(*src_rsel_o)),
 204                 # accumulate Reg-Sel Vector outputs
 205                 src_rsel.append(rsv.src_rsel_o[i])
 206
 207             # ... and output them from this module (horizontal, width=REGs)
 208             m.d.comb += self.src_rsel_o[i].eq(Cat(*src_rsel))
 209
 210         # ---
 211         # connect Dependency Matrix dest/src1/src2/issue to module d/s/s/i
 212         # ---
 213         for fu in range(self.n_fu_row):
 214             dc = dm[fu]
 215             # wire up inputs from module to row cell inputs (Cat is gooood)
 216             m.d.comb += [dc.rd_pend_i.eq(self.rd_pend_i),
 217                          dc.wr_pend_i.eq(self.wr_pend_i),
 218                         ]
 219         # same for dest
 220         for fu in range(self.n_fu_row):
 221             dc = dm[fu]
 222             # wire up inputs from module to row cell inputs (Cat is gooood)
 223             m.d.comb += dc.dest_i[i].eq(self.dest_i[i])
 224
 225         # same for src
 226         for i in range(self.n_src):
 227             for fu in range(self.n_fu_row):
 228                 dc = dm[fu]
 229                 # wire up inputs from module to row cell inputs (Cat is gooood)
 230                 m.d.comb += dc.src_i[i].eq(self.src_i[i])
 231
 232         # accumulate rsel bits into read/write pending vectors.
 233         rd_pend_v = []
 234         wr_pend_v = []
 235         for fu in range(self.n_fu_row):
 236             dc = dm[fu]
 237             rd_pend_v.append(dc.v_rd_rsel_o)
 238             wr_pend_v.append(dc.v_wr_rsel_o)
 239         rd_v = GlobalPending(self.n_reg_col, rd_pend_v)
 240         wr_v = GlobalPending(self.n_reg_col, wr_pend_v)
 241         m.submodules.rd_v = rd_v
 242         m.submodules.wr_v = wr_v
 243
 244         m.d.comb += self.v_rd_rsel_o.eq(rd_v.g_pend_o)
 245         m.d.comb += self.v_wr_rsel_o.eq(wr_v.g_pend_o)
 246
 247         # ---
 248         # connect Dep issue_i/go_rd_i/go_wr_i to module issue_i/go_rd/go_wr
 249         # ---
 250         issue_i = []
 251         for fu in range(self.n_fu_row):
 252             dc = dm[fu]
 253             issue_i.append(dc.issue_i)
 254         # wire up inputs from module to row cell inputs (Cat is gooood)
 255         m.d.comb += Cat(*issue_i).eq(self.issue_i)
 256
 257         for i in range(self.n_src):
 258             go_rd_i = []
 259             for fu in range(self.n_fu_row):
 260                 dc = dm[fu]
 261                 # accumulate cell fwd outputs for dest/src1/src2
 262                 go_rd_i.append(dc.go_rd_i[i])
 263             # wire up inputs from module to row cell inputs (Cat is gooood)
 264             m.d.comb += Cat(*go_rd_i).eq(self.go_rd_i[i])
 265
 266         for i in range(self.n_dest):
 267             go_wr_i = []
 268             for fu in range(self.n_fu_row):
 269                 dc = dm[fu]
 270                 # accumulate cell fwd outputs for dest/src1/src2
 271                 go_wr_i.append(dc.go_wr_i[i])
 272             # wire up inputs from module to row cell inputs (Cat is gooood)
 273             m.d.comb += Cat(*go_wr_i).eq(self.go_wr_i[i])
 274
 275         # ---
 276         # connect Dep go_die_i
 277         # ---
 278         if cancel_mode:
 279             for fu in range(self.n_fu_row):
 280                 dc = dm[fu]
 281                 go_die = Repl(self.go_die_i[fu], self.n_fu_row)
 282                 go_die = go_die | self.cancel[fu]
 283                 m.d.comb += dc.go_die_i.eq(go_die)
 284         else:
 285             go_die_i = []
 286             for fu in range(self.n_fu_row):
 287                 dc = dm[fu]
 288                 # accumulate cell fwd outputs for dest/src1/src2
 289                 go_die_i.append(dc.go_die_i)
 290             # wire up inputs from module to row cell inputs (Cat is gooood)
 291             m.d.comb += Cat(*go_die_i).eq(self.go_die_i)
 292         return m
 293
 294     def __iter__(self):
 295         yield from self.dest_i
 296         yield from self.src_i
 297         yield self.issue_i
 298         yield from self.go_wr_i
 299         yield from self.go_rd_i
 300         yield self.go_die_i
 301         yield from self.dest_rsel_o
 302         yield from self.src_rsel_o
 303         yield self.wr_pend_o
 304         yield self.rd_pend_o
 305         yield self.wr_pend_i
 306         yield self.rd_pend_i
 307         yield self.v_wr_rsel_o
 308         yield self.v_rd_rsel_o
 309         yield from self.rd_src_pend_o
 310
 311     def ports(self):
 312         return list(self)
 313
 314 def d_matrix_sim(dut):
 315     """ XXX TODO
 316     """
 317     yield dut.dest_i.eq(1)
 318     yield dut.issue_i.eq(1)
 319     yield
 320     yield dut.issue_i.eq(0)
 321     yield
 322     yield dut.src1_i.eq(1)
 323     yield dut.issue_i.eq(1)
 324     yield
 325     yield dut.issue_i.eq(0)
 326     yield
 327     yield dut.go_rd_i.eq(1)
 328     yield
 329     yield dut.go_rd_i.eq(0)
 330     yield
 331     yield dut.go_wr_i.eq(1)
 332     yield
 333     yield dut.go_wr_i.eq(0)
 334     yield
 335
 336 def test_d_matrix():
 337     dut = FURegDepMatrix(n_fu_row=3, n_reg_col=4, n_src=2, n_dest=2)
 338     vl = rtlil.convert(dut, ports=dut.ports())
 339     with open("test_fu_reg_matrix.il", "w") as f:
 340         f.write(vl)
 341
 342     run_simulation(dut, d_matrix_sim(dut), vcd_name='test_fu_reg_matrix.vcd')
 343
 344 if __name__ == '__main__':
 345     test_d_matrix()