src/soc/scoremulti/fu_wr_pending.py

   1 from nmigen import Elaboratable, Module, Signal, Array
   2
   3
   4 class FU_RW_Pend(Elaboratable):
   5     """ these are allocated per-FU (horizontally),
   6         and are of length reg_count
   7     """
   8     def __init__(self, reg_count, n_src, n_dest):
   9         self.n_src = n_src
  10         self.n_dest = n_dest
  11         self.reg_count = reg_count
  12         dst = []
  13         for i in range(n_dest):
  14             j = i + 1 # name numbering to match dest1/dest2
  15             dst.append(Signal(reg_count, name="dfwd%d_i" % j, reset_less=True))
  16         self.dest_fwd_i = Array(dst)
  17         src = []
  18         for i in range(n_src):
  19             j = i + 1 # name numbering to match src1/src2
  20             src.append(Signal(reg_count, name="sfwd%d_i" % j, reset_less=True))
  21         self.src_fwd_i = Array(src)
  22
  23         self.reg_wr_pend_o = Signal(reset_less=True)
  24         self.reg_rd_pend_o = Signal(reset_less=True)
  25         self.reg_rd_src_pend_o = Signal(n_src, reset_less=True)
  26         self.reg_wr_dst_pend_o = Signal(n_dest, reset_less=True)
  27
  28     def elaborate(self, platform):
  29         m = Module()
  30
  31         # OR forwarding input together to create per-src pending
  32         for i in range(self.n_src):
  33             m.d.comb += self.reg_rd_src_pend_o[i].eq(self.src_fwd_i[i].bool())
  34         # then OR all src pending together
  35         m.d.comb += self.reg_rd_pend_o.eq(self.reg_rd_src_pend_o.bool())
  36
  37         # likewise for per-dest then all-dest
  38         for i in range(self.n_dest):
  39             m.d.comb += self.reg_wr_dst_pend_o[i].eq(self.dest_fwd_i[i].bool())
  40         m.d.comb += self.reg_wr_pend_o.eq(self.reg_wr_dst_pend_o.bool())
  41         return m
  42