src/soc/simple/core_data.py

   1 """simple core input data
   2
   3 """
   4
   5 from nmigen import Signal
   6
   7 from openpower.sv.svp64 import SVP64Rec
   8
   9 from openpower.decoder.decode2execute1 import Decode2ToExecute1Type
  10 from openpower.decoder.decode2execute1 import IssuerDecode2ToOperand
  11 from soc.config.state import CoreState
  12
  13
  14 class FetchInput:
  15     """FetchInput: the input to the Fetch Unit
  16
  17     * pc - the current Program Counter
  18
  19     pretty much it for now!
  20
  21     """
  22     def __init__(self):
  23
  24         self.pc = Signal(64)
  25         self.msr = Signal(64)
  26
  27     def eq(self, i):
  28         return [self.pc.eq(i.pc), self.msr.eq(i.msr),
  29                ]
  30
  31
  32 class FetchOutput:
  33     """FetchOutput: the output from the fetch unit: one single instruction
  34
  35     * state.  this contains PC, MSR, and SVSTATE. this is crucial information.
  36       (TODO: bigendian_i should really be read from the relevant MSR bit)
  37
  38     * the raw instruction.  no decoding has been done - at all.
  39
  40       (TODO: provide a *pair* of raw instructions so that packet
  41        inspection can be done, and SVP64 decoding and future 64-bit
  42        prefix analysis carried out.  however right now that is *not*
  43        the focus)
  44     """
  45     def __init__(self): #, svp64_en):
  46         #self.svp64_en = svp64_en
  47
  48         # state and raw instruction (and SVP64 ReMap fields)
  49         self.state = CoreState("core_fetched")
  50         self.raw_insn_i = Signal(32) # one raw instruction
  51         self.bigendian_i = Signal() # bigendian - TODO, set by MSR.BE
  52
  53     def eq(self, i):
  54         return [self.state.eq(i.state),
  55                 self.raw_insn_i.eq(i.raw_insn_i),
  56                 self.bigendian_i.eq(i.bigendian_i),
  57                ]
  58
  59
  60 class CoreInput:
  61     """CoreInput: this is the input specification for Signals coming into core.
  62
  63     * state.  this contains PC, MSR, and SVSTATE. this is crucial information.
  64       (TODO: bigendian_i should really be read from the relevant MSR bit)
  65
  66     * the previously-decoded instruction goes into the Decode2Execute1Type
  67       data structure. no need for Core to re-decode that.  however note
  68       that *satellite* decoders *are* part of Core.
  69
  70     * the raw instruction. this is used by satellite decoders internal to
  71       Core, to provide Function-Unit-specific information.  really, they
  72       should be part of the actual ALU itself (in order to reduce wires),
  73       but hey.
  74
  75     * other stuff is related to SVP64.  the 24-bit SV REMAP field containing
  76       Vector context, etc.
  77     """
  78     def __init__(self, pspec, svp64_en, regreduce_en):
  79         self.pspec = pspec
  80         self.svp64_en = svp64_en
  81         self.e = Decode2ToExecute1Type("core", opkls=IssuerDecode2ToOperand,
  82                                 regreduce_en=regreduce_en)
  83
  84         # SVP64 RA_OR_ZERO needs to know if the relevant EXTRA2/3 field is zero
  85         self.sv_a_nz = Signal()
  86
  87         # state and raw instruction (and SVP64 ReMap fields)
  88         self.state = CoreState("core")
  89         self.raw_insn_i = Signal(32) # raw instruction
  90         self.bigendian_i = Signal() # bigendian - TODO, set by MSR.BE
  91         if svp64_en:
  92             self.sv_rm = SVP64Rec(name="core_svp64_rm") # SVP64 RM field
  93             self.is_svp64_mode = Signal() # set if SVP64 mode is enabled
  94             self.use_svp64_ldst_dec = Signal() # use alternative LDST decoder
  95             self.sv_pred_sm = Signal() # TODO: SIMD width
  96             self.sv_pred_dm = Signal() # TODO: SIMD width
  97
  98     def eq(self, i):
  99         res = [self.e.eq(i.e),
 100                 self.sv_a_nz.eq(i.sv_a_nz),
 101                 self.state.eq(i.state),
 102                 self.raw_insn_i.eq(i.raw_insn_i),
 103                 self.bigendian_i.eq(i.bigendian_i),
 104                ]
 105         if not self.svp64_en:
 106             return res
 107         res += [ self.sv_rm.eq(i.sv_rm),
 108                 self.is_svp64_mode.eq(i.is_svp64_mode),
 109                 self.use_svp64_ldst_dec.eq(i.use_svp64_ldst_dec),
 110                 self.sv_pred_sm.eq(i.sv_pred_sm),
 111                 self.sv_pred_dm.eq(i.sv_pred_dm),
 112                 ]
 113         return res
 114
 115
 116 class CoreOutput:
 117     def __init__(self):
 118         # start/stop and terminated signalling
 119         self.core_terminate_o = Signal()  # indicates stopped
 120         self.busy_o = Signal(name="corebusy_o")  # ALU is busy, no input
 121         self.any_busy_o = Signal(name="any_busy_o")  # at least one ALU busy
 122         self.exc_happened = Signal()             # exception happened
 123
 124     def eq(self, i):
 125         return [self.core_terminate_o.eq(i.core_terminate_o),
 126                 self.busy_o.eq(i.busy_o),
 127                 self.any_busy_o.eq(i.any_busy_o),
 128                 self.exc_happened.eq(i.exc_happened),
 129                ]
 130
 131