src/soc/simple/core_data.py

   1 """simple core input data
   2
   3 """
   4
   5 from nmigen import Signal
   6
   7 from openpower.sv.svp64 import SVP64Rec
   8
   9 from openpower.decoder.decode2execute1 import Decode2ToExecute1Type
  10 from openpower.decoder.decode2execute1 import IssuerDecode2ToOperand
  11 from soc.config.state import CoreState
  12
  13
  14 class CoreInput:
  15     """CoreInput: this is the input specification for Signals coming into core.
  16
  17     * state.  this contains PC, MSR, and SVSTATE. this is crucial information.
  18       (TODO: bigendian_i should really be read from the relevant MSR bit)
  19
  20     * the previously-decoded instruction goes into the Decode2Execute1Type
  21       data structure. no need for Core to re-decode that.  however note
  22       that *satellite* decoders *are* part of Core.
  23
  24     * the raw instruction. this is used by satellite decoders internal to
  25       Core, to provide Function-Unit-specific information.  really, they
  26       should be part of the actual ALU itself (in order to reduce wires),
  27       but hey.
  28
  29     * other stuff is related to SVP64.  the 24-bit SV REMAP field containing
  30       Vector context, etc.
  31     """
  32     def __init__(self, pspec, svp64_en, regreduce_en):
  33         self.pspec = pspec
  34         self.svp64_en = svp64_en
  35         self.e = Decode2ToExecute1Type("core", opkls=IssuerDecode2ToOperand,
  36                                 regreduce_en=regreduce_en)
  37
  38         # SVP64 RA_OR_ZERO needs to know if the relevant EXTRA2/3 field is zero
  39         self.sv_a_nz = Signal()
  40
  41         # state and raw instruction (and SVP64 ReMap fields)
  42         self.state = CoreState("core")
  43         self.raw_insn_i = Signal(32) # raw instruction
  44         self.bigendian_i = Signal() # bigendian - TODO, set by MSR.BE
  45         if svp64_en:
  46             self.sv_rm = SVP64Rec(name="core_svp64_rm") # SVP64 RM field
  47             self.is_svp64_mode = Signal() # set if SVP64 mode is enabled
  48             self.use_svp64_ldst_dec = Signal() # use alternative LDST decoder
  49             self.sv_pred_sm = Signal() # TODO: SIMD width
  50             self.sv_pred_dm = Signal() # TODO: SIMD width
  51
  52     def eq(self, i):
  53         self.e.eq(i.e)
  54         self.sv_a_nz.eq(i.sv_a_nz)
  55         self.state.eq(i.state)
  56         self.raw_insn_i.eq(i.raw_insn_i)
  57         self.bigendian_i.eq(i.bigendian_i)
  58         if not self.svp64_en:
  59             return
  60         self.sv_rm.eq(i.sv_rm)
  61         self.is_svp64_mode.eq(i.is_svp64_mode)
  62         self.use_svp64_ldst_dec.eq(i.use_svp64_ldst_dec)
  63         self.sv_pred_sm.eq(i.sv_pred_sm)
  64         self.sv_pred_dm.eq(i.sv_pred_dm)
  65
  66
  67 class CoreOutput:
  68     def __init__(self):
  69         # start/stop and terminated signalling
  70         self.core_terminate_o = Signal()  # indicates stopped
  71         self.busy_o = Signal(name="corebusy_o")  # at least one ALU busy
  72         self.exc_happened = Signal()             # exception happened
  73
  74     def eq(self, i):
  75         self.core_terminate_o.eq(i.core_terminate_o)
  76         self.busy_o.eq(i.busy_o)
  77         self.exc_happened.eq(i.exc_happened)
  78
  79