src/soc/simple/issuer.py

   1 """simple core issuer
   2
   3 not in any way intended for production use.  this runs a FSM that:
   4
   5 * reads the Program Counter from StateRegs
   6 * reads an instruction from a fixed-size Test Memory
   7 * issues it to the Simple Core
   8 * waits for it to complete
   9 * increments the PC
  10 * does it all over again
  11
  12 the purpose of this module is to verify the functional correctness
  13 of the Function Units in the absolute simplest and clearest possible
  14 way, and to at provide something that can be further incrementally
  15 improved.
  16 """
  17
  18 from nmigen import (Elaboratable, Module, Signal, ClockSignal, ResetSignal,
  19                     ClockDomain, DomainRenamer, Mux)
  20 from nmigen.cli import rtlil
  21 from nmigen.cli import main
  22 import sys
  23
  24 from soc.decoder.power_decoder import create_pdecode
  25 from soc.decoder.power_decoder2 import PowerDecode2, SVP64PrefixDecoder
  26 from soc.decoder.decode2execute1 import IssuerDecode2ToOperand
  27 from soc.decoder.decode2execute1 import Data
  28 from soc.experiment.testmem import TestMemory # test only for instructions
  29 from soc.regfile.regfiles import StateRegs, FastRegs
  30 from soc.simple.core import NonProductionCore
  31 from soc.config.test.test_loadstore import TestMemPspec
  32 from soc.config.ifetch import ConfigFetchUnit
  33 from soc.decoder.power_enums import MicrOp
  34 from soc.debug.dmi import CoreDebug, DMIInterface
  35 from soc.debug.jtag import JTAG
  36 from soc.config.pinouts import get_pinspecs
  37 from soc.config.state import CoreState
  38 from soc.interrupts.xics import XICS_ICP, XICS_ICS
  39 from soc.bus.simple_gpio import SimpleGPIO
  40 from soc.clock.select import ClockSelect
  41 from soc.clock.dummypll import DummyPLL
  42
  43
  44 from nmutil.util import rising_edge
  45
  46
  47 class TestIssuerInternal(Elaboratable):
  48     """TestIssuer - reads instructions from TestMemory and issues them
  49
  50     efficiency and speed is not the main goal here: functional correctness is.
  51     """
  52     def __init__(self, pspec):
  53
  54         # JTAG interface.  add this right at the start because if it's
  55         # added it *modifies* the pspec, by adding enable/disable signals
  56         # for parts of the rest of the core
  57         self.jtag_en = hasattr(pspec, "debug") and pspec.debug == 'jtag'
  58         if self.jtag_en:
  59             subset = {'uart', 'mtwi', 'eint', 'gpio', 'mspi0', 'mspi1',
  60                       'pwm', 'sd0', 'sdr'}
  61             self.jtag = JTAG(get_pinspecs(subset=subset))
  62             # add signals to pspec to enable/disable icache and dcache
  63             # (or data and intstruction wishbone if icache/dcache not included)
  64             # https://bugs.libre-soc.org/show_bug.cgi?id=520
  65             # TODO: do we actually care if these are not domain-synchronised?
  66             # honestly probably not.
  67             pspec.wb_icache_en = self.jtag.wb_icache_en
  68             pspec.wb_dcache_en = self.jtag.wb_dcache_en
  69
  70         # add interrupt controller?
  71         self.xics = hasattr(pspec, "xics") and pspec.xics == True
  72         if self.xics:
  73             self.xics_icp = XICS_ICP()
  74             self.xics_ics = XICS_ICS()
  75             self.int_level_i = self.xics_ics.int_level_i
  76
  77         # add GPIO peripheral?
  78         self.gpio = hasattr(pspec, "gpio") and pspec.gpio == True
  79         if self.gpio:
  80             self.simple_gpio = SimpleGPIO()
  81             self.gpio_o = self.simple_gpio.gpio_o
  82
  83         # main instruction core25
  84         self.core = core = NonProductionCore(pspec)
  85
  86         # instruction decoder.  goes into Trap Record
  87         pdecode = create_pdecode()
  88         self.cur_state = CoreState("cur") # current state (MSR/PC/EINT)
  89         self.pdecode2 = PowerDecode2(pdecode, state=self.cur_state,
  90                                      opkls=IssuerDecode2ToOperand)
  91         self.svp64 = SVP64PrefixDecoder() # for decoding SVP64 prefix
  92
  93         # Test Instruction memory
  94         self.imem = ConfigFetchUnit(pspec).fu
  95         # one-row cache of instruction read
  96         self.iline = Signal(64) # one instruction line
  97         self.iprev_adr = Signal(64) # previous address: if different, do read
  98
  99         # DMI interface
 100         self.dbg = CoreDebug()
 101
 102         # instruction go/monitor
 103         self.pc_o = Signal(64, reset_less=True)
 104         self.pc_i = Data(64, "pc_i") # set "ok" to indicate "please change me"
 105         self.core_bigendian_i = Signal()
 106         self.busy_o = Signal(reset_less=True)
 107         self.memerr_o = Signal(reset_less=True)
 108
 109         # FAST regfile read /write ports for PC, MSR, DEC/TB
 110         staterf = self.core.regs.rf['state']
 111         self.state_r_pc = staterf.r_ports['cia'] # PC rd
 112         self.state_w_pc = staterf.w_ports['d_wr1'] # PC wr
 113         self.state_r_msr = staterf.r_ports['msr'] # MSR rd
 114
 115         # DMI interface access
 116         intrf = self.core.regs.rf['int']
 117         crrf = self.core.regs.rf['cr']
 118         xerrf = self.core.regs.rf['xer']
 119         self.int_r = intrf.r_ports['dmi'] # INT read
 120         self.cr_r = crrf.r_ports['full_cr_dbg'] # CR read
 121         self.xer_r = xerrf.r_ports['full_xer'] # XER read
 122
 123         # hack method of keeping an eye on whether branch/trap set the PC
 124         self.state_nia = self.core.regs.rf['state'].w_ports['nia']
 125         self.state_nia.wen.name = 'state_nia_wen'
 126
 127     def elaborate(self, platform):
 128         m = Module()
 129         comb, sync = m.d.comb, m.d.sync
 130
 131         m.submodules.core = core = DomainRenamer("coresync")(self.core)
 132         m.submodules.imem = imem = self.imem
 133         m.submodules.dbg = dbg = self.dbg
 134         if self.jtag_en:
 135             m.submodules.jtag = jtag = self.jtag
 136             # TODO: UART2GDB mux, here, from external pin
 137             # see https://bugs.libre-soc.org/show_bug.cgi?id=499
 138             sync += dbg.dmi.connect_to(jtag.dmi)
 139
 140         cur_state = self.cur_state
 141
 142         # XICS interrupt handler
 143         if self.xics:
 144             m.submodules.xics_icp = icp = self.xics_icp
 145             m.submodules.xics_ics = ics = self.xics_ics
 146             comb += icp.ics_i.eq(ics.icp_o)           # connect ICS to ICP
 147             sync += cur_state.eint.eq(icp.core_irq_o) # connect ICP to core
 148
 149         # GPIO test peripheral
 150         if self.gpio:
 151             m.submodules.simple_gpio = simple_gpio = self.simple_gpio
 152
 153         # connect one GPIO output to ICS bit 15 (like in microwatt soc.vhdl)
 154         # XXX causes litex ECP5 test to get wrong idea about input and output
 155         # (but works with verilator sim *sigh*)
 156         #if self.gpio and self.xics:
 157         #   comb += self.int_level_i[15].eq(simple_gpio.gpio_o[0])
 158
 159         # instruction decoder
 160         pdecode = create_pdecode()
 161         m.submodules.dec2 = pdecode2 = self.pdecode2
 162         m.submodules.svp64 = svp64 = self.svp64
 163
 164         # convenience
 165         dmi, d_reg, d_cr, d_xer, = dbg.dmi, dbg.d_gpr, dbg.d_cr, dbg.d_xer
 166         intrf = self.core.regs.rf['int']
 167
 168         # clock delay power-on reset
 169         cd_por  = ClockDomain(reset_less=True)
 170         cd_sync = ClockDomain()
 171         core_sync = ClockDomain("coresync")
 172         m.domains += cd_por, cd_sync, core_sync
 173
 174         ti_rst = Signal(reset_less=True)
 175         delay = Signal(range(4), reset=3)
 176         with m.If(delay != 0):
 177             m.d.por += delay.eq(delay - 1)
 178         comb += cd_por.clk.eq(ClockSignal())
 179
 180         # power-on reset delay
 181         core_rst = ResetSignal("coresync")
 182         comb += ti_rst.eq(delay != 0 | dbg.core_rst_o | ResetSignal())
 183         comb += core_rst.eq(ti_rst)
 184
 185         # busy/halted signals from core
 186         comb += self.busy_o.eq(core.busy_o)
 187         comb += pdecode2.dec.bigendian.eq(self.core_bigendian_i)
 188
 189         # temporary hack: says "go" immediately for both address gen and ST
 190         l0 = core.l0
 191         ldst = core.fus.fus['ldst0']
 192         st_go_edge = rising_edge(m, ldst.st.rel_o)
 193         m.d.comb += ldst.ad.go_i.eq(ldst.ad.rel_o) # link addr-go direct to rel
 194         m.d.comb += ldst.st.go_i.eq(st_go_edge) # link store-go to rising rel
 195
 196         # PC and instruction from I-Memory
 197         pc_changed = Signal() # note write to PC
 198         comb += self.pc_o.eq(cur_state.pc)
 199         ilatch = Signal(32)
 200
 201         # address of the next instruction, in the absence of a branch
 202         # depends on the instruction size
 203         nia = Signal(64, reset_less=True)
 204
 205         # read the PC
 206         pc = Signal(64, reset_less=True)
 207         pc_ok_delay = Signal()
 208         sync += pc_ok_delay.eq(~self.pc_i.ok)
 209         with m.If(self.pc_i.ok):
 210             # incoming override (start from pc_i)
 211             comb += pc.eq(self.pc_i.data)
 212         with m.Else():
 213             # otherwise read StateRegs regfile for PC...
 214             comb += self.state_r_pc.ren.eq(1<<StateRegs.PC)
 215         # ... but on a 1-clock delay
 216         with m.If(pc_ok_delay):
 217             comb += pc.eq(self.state_r_pc.data_o)
 218
 219         # don't write pc every cycle
 220         comb += self.state_w_pc.wen.eq(0)
 221         comb += self.state_w_pc.data_i.eq(0)
 222
 223         # don't read msr every cycle
 224         comb += self.state_r_msr.ren.eq(0)
 225         msr_read = Signal(reset=1)
 226
 227         # connect up debug signals
 228         # TODO comb += core.icache_rst_i.eq(dbg.icache_rst_o)
 229         comb += dbg.terminate_i.eq(core.core_terminate_o)
 230         comb += dbg.state.pc.eq(pc)
 231         #comb += dbg.state.pc.eq(cur_state.pc)
 232         comb += dbg.state.msr.eq(cur_state.msr)
 233
 234         # temporaries
 235         core_busy_o = core.busy_o                 # core is busy
 236         core_ivalid_i = core.ivalid_i             # instruction is valid
 237         core_issue_i = core.issue_i               # instruction is issued
 238         dec_opcode_i = pdecode2.dec.raw_opcode_in # raw opcode
 239
 240         insn_type = core.e.do.insn_type
 241
 242         # handshake signals between fetch and decode/execute
 243         # fetch FSM can run as soon as the PC is valid
 244         fetch_pc_valid_i = Signal()
 245         fetch_pc_ready_o = Signal()
 246         # when done, deliver the instruction to the next FSM
 247         fetch_insn_o = Signal(32, reset_less=True)
 248         fetch_insn_valid_o = Signal()
 249         fetch_insn_ready_i = Signal()
 250
 251         # actually use a nmigen FSM for the first time (w00t)
 252         # this FSM is perhaps unusual in that it detects conditions
 253         # then "holds" information, combinatorially, for the core
 254         # (as opposed to using sync - which would be on a clock's delay)
 255         # this includes the actual opcode, valid flags and so on.
 256         with m.FSM(name='fetch_fsm'):
 257
 258             # waiting (zzz)
 259             with m.State("IDLE"):
 260                 with m.If(~dbg.core_stop_o & ~core_rst):
 261                     comb += fetch_pc_ready_o.eq(1)
 262                     with m.If(fetch_pc_valid_i):
 263                         # instruction allowed to go: start by reading the PC
 264                         # capture the PC and also drop it into Insn Memory
 265                         # we have joined a pair of combinatorial memory
 266                         # lookups together.  this is Generally Bad.
 267                         comb += self.imem.a_pc_i.eq(pc)
 268                         comb += self.imem.a_valid_i.eq(1)
 269                         comb += self.imem.f_valid_i.eq(1)
 270                         sync += cur_state.pc.eq(pc)
 271
 272                         # initiate read of MSR.  arrives one clock later
 273                         comb += self.state_r_msr.ren.eq(1 << StateRegs.MSR)
 274                         sync += msr_read.eq(0)
 275
 276                         m.next = "INSN_READ"  # move to "wait for bus" phase
 277                 with m.Else():
 278                     comb += core.core_stopped_i.eq(1)
 279                     comb += dbg.core_stopped_i.eq(1)
 280
 281             # dummy pause to find out why simulation is not keeping up
 282             with m.State("INSN_READ"):
 283                 # one cycle later, msr read arrives.  valid only once.
 284                 with m.If(~msr_read):
 285                     sync += msr_read.eq(1) # yeah don't read it again
 286                     sync += cur_state.msr.eq(self.state_r_msr.data_o)
 287                 with m.If(self.imem.f_busy_o): # zzz...
 288                     # busy: stay in wait-read
 289                     comb += self.imem.a_valid_i.eq(1)
 290                     comb += self.imem.f_valid_i.eq(1)
 291                 with m.Else():
 292                     # not busy: instruction fetched
 293                     f_instr_o = self.imem.f_instr_o
 294                     if f_instr_o.width == 32:
 295                         insn = f_instr_o
 296                     else:
 297                         insn = f_instr_o.word_select(cur_state.pc[2], 32)
 298                     # decode the SVP64 prefix, if any
 299                     comb += svp64.raw_opcode_in.eq(insn)
 300                     comb += svp64.bigendian.eq(self.core_bigendian_i)
 301                     # pass the decoded prefix (if any) to PowerDecoder2
 302                     sync += pdecode2.sv_rm.eq(svp64.svp64_rm)
 303                     # calculate the address of the following instruction
 304                     insn_size = Mux(svp64.is_svp64_mode, 8, 4)
 305                     sync += nia.eq(cur_state.pc + insn_size)
 306                     with m.If(~svp64.is_svp64_mode):
 307                         # with no prefix, store the instruction
 308                         # and hand it directly to the next FSM
 309                         sync += fetch_insn_o.eq(insn)
 310                         m.next = "INSN_READY"
 311                     with m.Else():
 312                         # fetch the rest of the instruction from memory
 313                         comb += self.imem.a_pc_i.eq(cur_state.pc + 4)
 314                         comb += self.imem.a_valid_i.eq(1)
 315                         comb += self.imem.f_valid_i.eq(1)
 316                         m.next = "INSN_READ2"
 317
 318             with m.State("INSN_READ2"):
 319                 with m.If(self.imem.f_busy_o):  # zzz...
 320                     # busy: stay in wait-read
 321                     comb += self.imem.a_valid_i.eq(1)
 322                     comb += self.imem.f_valid_i.eq(1)
 323                 with m.Else():
 324                     # not busy: instruction fetched
 325                     f_instr_o = self.imem.f_instr_o
 326                     if f_instr_o.width == 32:
 327                         insn = f_instr_o
 328                     else:
 329                         insn = f_instr_o.word_select((cur_state.pc+4)[2], 32)
 330                     sync += fetch_insn_o.eq(insn)
 331                     m.next = "INSN_READY"
 332
 333             with m.State("INSN_READY"):
 334                 # hand over the instruction, to be decoded
 335                 comb += fetch_insn_valid_o.eq(1)
 336                 with m.If(fetch_insn_ready_i):
 337                     m.next = "IDLE"
 338
 339         # decode / issue / execute FSM
 340         with m.FSM():
 341
 342             # go fetch the instruction at the current PC
 343             # at this point, there is no instruction running, that
 344             # could inadvertently update the PC.
 345             with m.State("INSN_FETCH"):
 346                 comb += fetch_pc_valid_i.eq(1)
 347                 with m.If(fetch_pc_ready_o):
 348                     m.next = "INSN_WAIT"
 349
 350             # decode the instruction when it arrives
 351             with m.State("INSN_WAIT"):
 352                 comb += fetch_insn_ready_i.eq(1)
 353                 with m.If(fetch_insn_valid_o):
 354                     # decode the instruction
 355                     # TODO, before issuing new instruction first
 356                     # check if it's SVP64. (svp64.is_svp64_mode set)
 357                     # if yes, record the svp64_rm, put that into
 358                     # pdecode2.sv_rm, then read another 32 bits (INSN_FETCH2?)
 359                     comb += dec_opcode_i.eq(fetch_insn_o)  # actual opcode
 360                     sync += core.e.eq(pdecode2.e)
 361                     sync += core.state.eq(cur_state)
 362                     sync += core.raw_insn_i.eq(dec_opcode_i)
 363                     sync += core.bigendian_i.eq(self.core_bigendian_i)
 364                     sync += ilatch.eq(insn) # latch current insn
 365                     # also drop PC and MSR into decode "state"
 366                     m.next = "INSN_START" # move to "start"
 367
 368             # waiting for instruction bus (stays there until not busy)
 369             with m.State("INSN_START"):
 370                 comb += core_ivalid_i.eq(1) # instruction is valid
 371                 comb += core_issue_i.eq(1)  # and issued
 372                 sync += pc_changed.eq(0)
 373
 374                 m.next = "INSN_ACTIVE" # move to "wait completion"
 375
 376             # instruction started: must wait till it finishes
 377             with m.State("INSN_ACTIVE"):
 378                 with m.If(insn_type != MicrOp.OP_NOP):
 379                     comb += core_ivalid_i.eq(1) # instruction is valid
 380                 with m.If(self.state_nia.wen & (1<<StateRegs.PC)):
 381                     sync += pc_changed.eq(1)
 382                 with m.If(~core_busy_o): # instruction done!
 383                     # ok here we are not reading the branch unit.  TODO
 384                     # this just blithely overwrites whatever pipeline
 385                     # updated the PC
 386                     with m.If(~pc_changed):
 387                         comb += self.state_w_pc.wen.eq(1<<StateRegs.PC)
 388                         comb += self.state_w_pc.data_i.eq(nia)
 389                     sync += core.e.eq(0)
 390                     sync += core.raw_insn_i.eq(0)
 391                     sync += core.bigendian_i.eq(0)
 392                     m.next = "INSN_FETCH"  # back to fetch
 393
 394         # this bit doesn't have to be in the FSM: connect up to read
 395         # regfiles on demand from DMI
 396         with m.If(d_reg.req): # request for regfile access being made
 397             # TODO: error-check this
 398             # XXX should this be combinatorial?  sync better?
 399             if intrf.unary:
 400                 comb += self.int_r.ren.eq(1<<d_reg.addr)
 401             else:
 402                 comb += self.int_r.addr.eq(d_reg.addr)
 403                 comb += self.int_r.ren.eq(1)
 404         d_reg_delay  = Signal()
 405         sync += d_reg_delay.eq(d_reg.req)
 406         with m.If(d_reg_delay):
 407             # data arrives one clock later
 408             comb += d_reg.data.eq(self.int_r.data_o)
 409             comb += d_reg.ack.eq(1)
 410
 411         # sigh same thing for CR debug
 412         with m.If(d_cr.req): # request for regfile access being made
 413             comb += self.cr_r.ren.eq(0b11111111) # enable all
 414         d_cr_delay  = Signal()
 415         sync += d_cr_delay.eq(d_cr.req)
 416         with m.If(d_cr_delay):
 417             # data arrives one clock later
 418             comb += d_cr.data.eq(self.cr_r.data_o)
 419             comb += d_cr.ack.eq(1)
 420
 421         # aaand XER...
 422         with m.If(d_xer.req): # request for regfile access being made
 423             comb += self.xer_r.ren.eq(0b111111) # enable all
 424         d_xer_delay  = Signal()
 425         sync += d_xer_delay.eq(d_xer.req)
 426         with m.If(d_xer_delay):
 427             # data arrives one clock later
 428             comb += d_xer.data.eq(self.xer_r.data_o)
 429             comb += d_xer.ack.eq(1)
 430
 431         # DEC and TB inc/dec FSM
 432         self.tb_dec_fsm(m, cur_state.dec)
 433
 434         return m
 435
 436     def tb_dec_fsm(self, m, spr_dec):
 437         """tb_dec_fsm
 438
 439         this is a FSM for updating either dec or tb.  it runs alternately
 440         DEC, TB, DEC, TB.  note that SPR pipeline could have written a new
 441         value to DEC, however the regfile has "passthrough" on it so this
 442         *should* be ok.
 443
 444         see v3.0B p1097-1099 for Timeer Resource and p1065 and p1076
 445         """
 446
 447         comb, sync = m.d.comb, m.d.sync
 448         fast_rf = self.core.regs.rf['fast']
 449         fast_r_dectb = fast_rf.r_ports['issue'] # DEC/TB
 450         fast_w_dectb = fast_rf.w_ports['issue'] # DEC/TB
 451
 452         with m.FSM() as fsm:
 453
 454             # initiates read of current DEC
 455             with m.State("DEC_READ"):
 456                 comb += fast_r_dectb.addr.eq(FastRegs.DEC)
 457                 comb += fast_r_dectb.ren.eq(1)
 458                 m.next = "DEC_WRITE"
 459
 460             # waits for DEC read to arrive (1 cycle), updates with new value
 461             with m.State("DEC_WRITE"):
 462                 new_dec = Signal(64)
 463                 # TODO: MSR.LPCR 32-bit decrement mode
 464                 comb += new_dec.eq(fast_r_dectb.data_o - 1)
 465                 comb += fast_w_dectb.addr.eq(FastRegs.DEC)
 466                 comb += fast_w_dectb.wen.eq(1)
 467                 comb += fast_w_dectb.data_i.eq(new_dec)
 468                 sync += spr_dec.eq(new_dec) # copy into cur_state for decoder
 469                 m.next = "TB_READ"
 470
 471             # initiates read of current TB
 472             with m.State("TB_READ"):
 473                 comb += fast_r_dectb.addr.eq(FastRegs.TB)
 474                 comb += fast_r_dectb.ren.eq(1)
 475                 m.next = "TB_WRITE"
 476
 477             # waits for read TB to arrive, initiates write of current TB
 478             with m.State("TB_WRITE"):
 479                 new_tb = Signal(64)
 480                 comb += new_tb.eq(fast_r_dectb.data_o + 1)
 481                 comb += fast_w_dectb.addr.eq(FastRegs.TB)
 482                 comb += fast_w_dectb.wen.eq(1)
 483                 comb += fast_w_dectb.data_i.eq(new_tb)
 484                 m.next = "DEC_READ"
 485
 486         return m
 487
 488     def __iter__(self):
 489         yield from self.pc_i.ports()
 490         yield self.pc_o
 491         yield self.memerr_o
 492         yield from self.core.ports()
 493         yield from self.imem.ports()
 494         yield self.core_bigendian_i
 495         yield self.busy_o
 496
 497     def ports(self):
 498         return list(self)
 499
 500     def external_ports(self):
 501         ports = self.pc_i.ports()
 502         ports += [self.pc_o, self.memerr_o, self.core_bigendian_i, self.busy_o,
 503                 ]
 504
 505         if self.jtag_en:
 506             ports += list(self.jtag.external_ports())
 507         else:
 508             # don't add DMI if JTAG is enabled
 509             ports += list(self.dbg.dmi.ports())
 510
 511         ports += list(self.imem.ibus.fields.values())
 512         ports += list(self.core.l0.cmpi.lsmem.lsi.slavebus.fields.values())
 513
 514         if self.xics:
 515             ports += list(self.xics_icp.bus.fields.values())
 516             ports += list(self.xics_ics.bus.fields.values())
 517             ports.append(self.int_level_i)
 518
 519         if self.gpio:
 520             ports += list(self.simple_gpio.bus.fields.values())
 521             ports.append(self.gpio_o)
 522
 523         return ports
 524
 525     def ports(self):
 526         return list(self)
 527
 528
 529 class TestIssuer(Elaboratable):
 530     def __init__(self, pspec):
 531         self.ti = TestIssuerInternal(pspec)
 532
 533         self.pll = DummyPLL()
 534
 535         # PLL direct clock or not
 536         self.pll_en = hasattr(pspec, "use_pll") and pspec.use_pll
 537         if self.pll_en:
 538             self.pll_18_o = Signal(reset_less=True)
 539
 540     def elaborate(self, platform):
 541         m = Module()
 542         comb = m.d.comb
 543
 544         # TestIssuer runs at direct clock
 545         m.submodules.ti = ti = self.ti
 546         cd_int = ClockDomain("coresync")
 547
 548         if self.pll_en:
 549             # ClockSelect runs at PLL output internal clock rate
 550             m.submodules.pll = pll = self.pll
 551
 552             # add clock domains from PLL
 553             cd_pll = ClockDomain("pllclk")
 554             m.domains += cd_pll
 555
 556             # PLL clock established.  has the side-effect of running clklsel
 557             # at the PLL's speed (see DomainRenamer("pllclk") above)
 558             pllclk = ClockSignal("pllclk")
 559             comb += pllclk.eq(pll.clk_pll_o)
 560
 561             # wire up external 24mhz to PLL
 562             comb += pll.clk_24_i.eq(ClockSignal())
 563
 564             # output 18 mhz PLL test signal
 565             comb += self.pll_18_o.eq(pll.pll_18_o)
 566
 567             # now wire up ResetSignals.  don't mind them being in this domain
 568             pll_rst = ResetSignal("pllclk")
 569             comb += pll_rst.eq(ResetSignal())
 570
 571         # internal clock is set to selector clock-out.  has the side-effect of
 572         # running TestIssuer at this speed (see DomainRenamer("intclk") above)
 573         intclk = ClockSignal("coresync")
 574         if self.pll_en:
 575             comb += intclk.eq(pll.clk_pll_o)
 576         else:
 577             comb += intclk.eq(ClockSignal())
 578
 579         return m
 580
 581     def ports(self):
 582         return list(self.ti.ports()) + list(self.pll.ports()) + \
 583                [ClockSignal(), ResetSignal()]
 584
 585     def external_ports(self):
 586         ports = self.ti.external_ports()
 587         ports.append(ClockSignal())
 588         ports.append(ResetSignal())
 589         if self.pll_en:
 590             ports.append(self.pll.clk_sel_i)
 591             ports.append(self.pll_18_o)
 592             ports.append(self.pll.pll_lck_o)
 593         return ports
 594
 595
 596 if __name__ == '__main__':
 597     units = {'alu': 1, 'cr': 1, 'branch': 1, 'trap': 1, 'logical': 1,
 598              'spr': 1,
 599              'div': 1,
 600              'mul': 1,
 601              'shiftrot': 1
 602             }
 603     pspec = TestMemPspec(ldst_ifacetype='bare_wb',
 604                          imem_ifacetype='bare_wb',
 605                          addr_wid=48,
 606                          mask_wid=8,
 607                          reg_wid=64,
 608                          units=units)
 609     dut = TestIssuer(pspec)
 610     vl = main(dut, ports=dut.ports(), name="test_issuer")
 611
 612     if len(sys.argv) == 1:
 613         vl = rtlil.convert(dut, ports=dut.external_ports(), name="test_issuer")
 614         with open("test_issuer.il", "w") as f:
 615             f.write(vl)