src/soc/simple/issuer.py

   1 """simple core issuer
   2
   3 not in any way intended for production use.  this runs a FSM that:
   4
   5 * reads the Program Counter from StateRegs
   6 * reads an instruction from a fixed-size Test Memory
   7 * issues it to the Simple Core
   8 * waits for it to complete
   9 * increments the PC
  10 * does it all over again
  11
  12 the purpose of this module is to verify the functional correctness
  13 of the Function Units in the absolute simplest and clearest possible
  14 way, and to at provide something that can be further incrementally
  15 improved.
  16 """
  17
  18 from nmigen import (Elaboratable, Module, Signal, ClockSignal, ResetSignal,
  19                     ClockDomain, DomainRenamer, Mux, Const)
  20 from nmigen.cli import rtlil
  21 from nmigen.cli import main
  22 import sys
  23
  24 from soc.decoder.power_decoder import create_pdecode
  25 from soc.decoder.power_decoder2 import PowerDecode2, SVP64PrefixDecoder
  26 from soc.decoder.decode2execute1 import IssuerDecode2ToOperand
  27 from soc.decoder.decode2execute1 import Data
  28 from soc.experiment.testmem import TestMemory # test only for instructions
  29 from soc.regfile.regfiles import StateRegs, FastRegs
  30 from soc.simple.core import NonProductionCore
  31 from soc.config.test.test_loadstore import TestMemPspec
  32 from soc.config.ifetch import ConfigFetchUnit
  33 from soc.decoder.power_enums import MicrOp
  34 from soc.debug.dmi import CoreDebug, DMIInterface
  35 from soc.debug.jtag import JTAG
  36 from soc.config.pinouts import get_pinspecs
  37 from soc.config.state import CoreState
  38 from soc.interrupts.xics import XICS_ICP, XICS_ICS
  39 from soc.bus.simple_gpio import SimpleGPIO
  40 from soc.bus.SPBlock512W64B8W import SPBlock512W64B8W
  41 from soc.clock.select import ClockSelect
  42 from soc.clock.dummypll import DummyPLL
  43 from soc.sv.svstate import SVSTATERec
  44
  45
  46 from nmutil.util import rising_edge
  47
  48 def get_insn(f_instr_o, pc):
  49     if f_instr_o.width == 32:
  50         return f_instr_o
  51     else:
  52         # 64-bit: bit 2 of pc decides which word to select
  53         return f_instr_o.word_select(pc[2], 32)
  54
  55
  56 class TestIssuerInternal(Elaboratable):
  57     """TestIssuer - reads instructions from TestMemory and issues them
  58
  59     efficiency and speed is not the main goal here: functional correctness is.
  60     """
  61     def __init__(self, pspec):
  62
  63         # test is SVP64 is to be enabled
  64         self.svp64_en = hasattr(pspec, "svp64") and (pspec.svp64 == True)
  65
  66         # JTAG interface.  add this right at the start because if it's
  67         # added it *modifies* the pspec, by adding enable/disable signals
  68         # for parts of the rest of the core
  69         self.jtag_en = hasattr(pspec, "debug") and pspec.debug == 'jtag'
  70         if self.jtag_en:
  71             subset = {'uart', 'mtwi', 'eint', 'gpio', 'mspi0', 'mspi1',
  72                       'pwm', 'sd0', 'sdr'}
  73             self.jtag = JTAG(get_pinspecs(subset=subset))
  74             # add signals to pspec to enable/disable icache and dcache
  75             # (or data and intstruction wishbone if icache/dcache not included)
  76             # https://bugs.libre-soc.org/show_bug.cgi?id=520
  77             # TODO: do we actually care if these are not domain-synchronised?
  78             # honestly probably not.
  79             pspec.wb_icache_en = self.jtag.wb_icache_en
  80             pspec.wb_dcache_en = self.jtag.wb_dcache_en
  81             self.wb_sram_en = self.jtag.wb_sram_en
  82         else:
  83             self.wb_sram_en = Const(1)
  84
  85         # add 4k sram blocks?
  86         self.sram4x4k = (hasattr(pspec, "sram4x4kblock") and
  87                          pspec.sram4x4kblock == True)
  88         if self.sram4x4k:
  89             self.sram4k = []
  90             for i in range(4):
  91                 self.sram4k.append(SPBlock512W64B8W(name="sram4k_%d" % i,
  92                                                     features={'err'}))
  93
  94         # add interrupt controller?
  95         self.xics = hasattr(pspec, "xics") and pspec.xics == True
  96         if self.xics:
  97             self.xics_icp = XICS_ICP()
  98             self.xics_ics = XICS_ICS()
  99             self.int_level_i = self.xics_ics.int_level_i
 100
 101         # add GPIO peripheral?
 102         self.gpio = hasattr(pspec, "gpio") and pspec.gpio == True
 103         if self.gpio:
 104             self.simple_gpio = SimpleGPIO()
 105             self.gpio_o = self.simple_gpio.gpio_o
 106
 107         # main instruction core25
 108         self.core = core = NonProductionCore(pspec)
 109
 110         # instruction decoder.  goes into Trap Record
 111         pdecode = create_pdecode()
 112         self.cur_state = CoreState("cur") # current state (MSR/PC/EINT/SVSTATE)
 113         self.pdecode2 = PowerDecode2(pdecode, state=self.cur_state,
 114                                      opkls=IssuerDecode2ToOperand,
 115                                      svp64_en=self.svp64_en)
 116         if self.svp64_en:
 117             self.svp64 = SVP64PrefixDecoder() # for decoding SVP64 prefix
 118
 119         # Test Instruction memory
 120         self.imem = ConfigFetchUnit(pspec).fu
 121         # one-row cache of instruction read
 122         self.iline = Signal(64) # one instruction line
 123         self.iprev_adr = Signal(64) # previous address: if different, do read
 124
 125         # DMI interface
 126         self.dbg = CoreDebug()
 127
 128         # instruction go/monitor
 129         self.pc_o = Signal(64, reset_less=True)
 130         self.pc_i = Data(64, "pc_i") # set "ok" to indicate "please change me"
 131         self.svstate_i = Data(32, "svstate_i") # ditto
 132         self.core_bigendian_i = Signal()
 133         self.busy_o = Signal(reset_less=True)
 134         self.memerr_o = Signal(reset_less=True)
 135
 136         # STATE regfile read /write ports for PC, MSR, SVSTATE
 137         staterf = self.core.regs.rf['state']
 138         self.state_r_pc = staterf.r_ports['cia'] # PC rd
 139         self.state_w_pc = staterf.w_ports['d_wr1'] # PC wr
 140         self.state_r_msr = staterf.r_ports['msr'] # MSR rd
 141         self.state_r_sv = staterf.r_ports['sv'] # SVSTATE rd
 142         self.state_w_sv = staterf.w_ports['sv'] # SVSTATE wr
 143
 144         # DMI interface access
 145         intrf = self.core.regs.rf['int']
 146         crrf = self.core.regs.rf['cr']
 147         xerrf = self.core.regs.rf['xer']
 148         self.int_r = intrf.r_ports['dmi'] # INT read
 149         self.cr_r = crrf.r_ports['full_cr_dbg'] # CR read
 150         self.xer_r = xerrf.r_ports['full_xer'] # XER read
 151
 152         # hack method of keeping an eye on whether branch/trap set the PC
 153         self.state_nia = self.core.regs.rf['state'].w_ports['nia']
 154         self.state_nia.wen.name = 'state_nia_wen'
 155
 156         # pulse to synchronize the simulator at instruction end
 157         self.insn_done = Signal()
 158
 159         if self.svp64_en:
 160             # store copies of predicate masks
 161             self.srcmask = Signal(64)
 162             self.dstmask = Signal(64)
 163
 164     def fetch_fsm(self, m, core, pc, svstate, nia, is_svp64_mode,
 165                         fetch_pc_ready_o, fetch_pc_valid_i,
 166                         fetch_insn_valid_o, fetch_insn_ready_i):
 167         """fetch FSM
 168         this FSM performs fetch of raw instruction data, partial-decodes
 169         it 32-bit at a time to detect SVP64 prefixes, and will optionally
 170         read a 2nd 32-bit quantity if that occurs.
 171         """
 172         comb = m.d.comb
 173         sync = m.d.sync
 174         pdecode2 = self.pdecode2
 175         cur_state = self.cur_state
 176         dec_opcode_i = pdecode2.dec.raw_opcode_in # raw opcode
 177
 178         msr_read = Signal(reset=1)
 179
 180         with m.FSM(name='fetch_fsm'):
 181
 182             # waiting (zzz)
 183             with m.State("IDLE"):
 184                 comb += fetch_pc_ready_o.eq(1)
 185                 with m.If(fetch_pc_valid_i):
 186                     # instruction allowed to go: start by reading the PC
 187                     # capture the PC and also drop it into Insn Memory
 188                     # we have joined a pair of combinatorial memory
 189                     # lookups together.  this is Generally Bad.
 190                     comb += self.imem.a_pc_i.eq(pc)
 191                     comb += self.imem.a_valid_i.eq(1)
 192                     comb += self.imem.f_valid_i.eq(1)
 193                     sync += cur_state.pc.eq(pc)
 194                     sync += cur_state.svstate.eq(svstate) # and svstate
 195
 196                     # initiate read of MSR. arrives one clock later
 197                     comb += self.state_r_msr.ren.eq(1 << StateRegs.MSR)
 198                     sync += msr_read.eq(0)
 199
 200                     m.next = "INSN_READ"  # move to "wait for bus" phase
 201
 202             # dummy pause to find out why simulation is not keeping up
 203             with m.State("INSN_READ"):
 204                 # one cycle later, msr/sv read arrives.  valid only once.
 205                 with m.If(~msr_read):
 206                     sync += msr_read.eq(1) # yeah don't read it again
 207                     sync += cur_state.msr.eq(self.state_r_msr.data_o)
 208                 with m.If(self.imem.f_busy_o): # zzz...
 209                     # busy: stay in wait-read
 210                     comb += self.imem.a_valid_i.eq(1)
 211                     comb += self.imem.f_valid_i.eq(1)
 212                 with m.Else():
 213                     # not busy: instruction fetched
 214                     insn = get_insn(self.imem.f_instr_o, cur_state.pc)
 215                     if self.svp64_en:
 216                         svp64 = self.svp64
 217                         # decode the SVP64 prefix, if any
 218                         comb += svp64.raw_opcode_in.eq(insn)
 219                         comb += svp64.bigendian.eq(self.core_bigendian_i)
 220                         # pass the decoded prefix (if any) to PowerDecoder2
 221                         sync += pdecode2.sv_rm.eq(svp64.svp64_rm)
 222                         # remember whether this is a prefixed instruction, so
 223                         # the FSM can readily loop when VL==0
 224                         sync += is_svp64_mode.eq(svp64.is_svp64_mode)
 225                         # calculate the address of the following instruction
 226                         insn_size = Mux(svp64.is_svp64_mode, 8, 4)
 227                         sync += nia.eq(cur_state.pc + insn_size)
 228                         with m.If(~svp64.is_svp64_mode):
 229                             # with no prefix, store the instruction
 230                             # and hand it directly to the next FSM
 231                             sync += dec_opcode_i.eq(insn)
 232                             m.next = "INSN_READY"
 233                         with m.Else():
 234                             # fetch the rest of the instruction from memory
 235                             comb += self.imem.a_pc_i.eq(cur_state.pc + 4)
 236                             comb += self.imem.a_valid_i.eq(1)
 237                             comb += self.imem.f_valid_i.eq(1)
 238                             m.next = "INSN_READ2"
 239                     else:
 240                         # not SVP64 - 32-bit only
 241                         sync += nia.eq(cur_state.pc + 4)
 242                         sync += dec_opcode_i.eq(insn)
 243                         m.next = "INSN_READY"
 244
 245             with m.State("INSN_READ2"):
 246                 with m.If(self.imem.f_busy_o):  # zzz...
 247                     # busy: stay in wait-read
 248                     comb += self.imem.a_valid_i.eq(1)
 249                     comb += self.imem.f_valid_i.eq(1)
 250                 with m.Else():
 251                     # not busy: instruction fetched
 252                     insn = get_insn(self.imem.f_instr_o, cur_state.pc+4)
 253                     sync += dec_opcode_i.eq(insn)
 254                     m.next = "INSN_READY"
 255                     # TODO: probably can start looking at pdecode2.rm_dec
 256                     # here (or maybe even in INSN_READ state, if svp64_mode
 257                     # detected, in order to trigger - and wait for - the
 258                     # predicate reading.
 259
 260             with m.State("INSN_READY"):
 261                 # hand over the instruction, to be decoded
 262                 comb += fetch_insn_valid_o.eq(1)
 263                 with m.If(fetch_insn_ready_i):
 264                     m.next = "IDLE"
 265
 266     def fetch_predicate_fsm(self, m, core, TODO):
 267         """fetch_predicate_fsm - obtains (constructs in the case of CR)
 268            src/dest predicate masks
 269
 270         https://bugs.libre-soc.org/show_bug.cgi?id=617
 271         the predicates can be read here, by using IntRegs r_ports['pred']
 272         or CRRegs r_ports['pred'].  in the case of CRs it will have to
 273         be done through multiple reads, extracting one relevant at a time.
 274         later, a faster way would be to use the 32-bit-wide CR port but
 275         this is more complex decoding, here.
 276         """
 277         comb = m.d.comb
 278         sync = m.d.sync
 279         pdecode2 = self.pdecode2
 280         rm_dec = pdecode2.rm_dec # SVP64RMModeDecode
 281         predmode = rm_dec.predmode
 282         srcpred, dstpred = rm_dec.srcpred, rm_dec.dstpred
 283
 284     def issue_fsm(self, m, core, pc_changed, sv_changed, nia,
 285                   dbg, core_rst, is_svp64_mode,
 286                   fetch_pc_ready_o, fetch_pc_valid_i,
 287                   fetch_insn_valid_o, fetch_insn_ready_i,
 288                   exec_insn_valid_i, exec_insn_ready_o,
 289                   exec_pc_valid_o, exec_pc_ready_i):
 290         """issue FSM
 291
 292         decode / issue FSM.  this interacts with the "fetch" FSM
 293         through fetch_insn_ready/valid (incoming) and fetch_pc_ready/valid
 294         (outgoing). also interacts with the "execute" FSM
 295         through exec_insn_ready/valid (outgoing) and exec_pc_ready/valid
 296         (incoming).
 297         SVP64 RM prefixes have already been set up by the
 298         "fetch" phase, so execute is fairly straightforward.
 299         """
 300
 301         comb = m.d.comb
 302         sync = m.d.sync
 303         pdecode2 = self.pdecode2
 304         cur_state = self.cur_state
 305
 306         # temporaries
 307         dec_opcode_i = pdecode2.dec.raw_opcode_in # raw opcode
 308
 309         # for updating svstate (things like srcstep etc.)
 310         update_svstate = Signal() # set this (below) if updating
 311         new_svstate = SVSTATERec("new_svstate")
 312         comb += new_svstate.eq(cur_state.svstate)
 313
 314         with m.FSM(name="issue_fsm"):
 315
 316             # sync with the "fetch" phase which is reading the instruction
 317             # at this point, there is no instruction running, that
 318             # could inadvertently update the PC.
 319             with m.State("ISSUE_START"):
 320                 # wait on "core stop" release, before next fetch
 321                 # need to do this here, in case we are in a VL==0 loop
 322                 with m.If(~dbg.core_stop_o & ~core_rst):
 323                     comb += fetch_pc_valid_i.eq(1) # tell fetch to start
 324                     with m.If(fetch_pc_ready_o):   # fetch acknowledged us
 325                         m.next = "INSN_WAIT"
 326                 with m.Else():
 327                     # tell core it's stopped, and acknowledge debug handshake
 328                     comb += core.core_stopped_i.eq(1)
 329                     comb += dbg.core_stopped_i.eq(1)
 330                     # while stopped, allow updating the PC and SVSTATE
 331                     with m.If(self.pc_i.ok):
 332                         comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
 333                         comb += self.state_w_pc.data_i.eq(self.pc_i.data)
 334                         sync += pc_changed.eq(1)
 335                     with m.If(self.svstate_i.ok):
 336                         comb += new_svstate.eq(self.svstate_i.data)
 337                         comb += update_svstate.eq(1)
 338                         sync += sv_changed.eq(1)
 339
 340             # decode the instruction when it arrives
 341             with m.State("INSN_WAIT"):
 342                 comb += fetch_insn_ready_i.eq(1)
 343                 with m.If(fetch_insn_valid_o):
 344                     # decode the instruction
 345                     sync += core.e.eq(pdecode2.e)
 346                     sync += core.state.eq(cur_state)
 347                     sync += core.raw_insn_i.eq(dec_opcode_i)
 348                     sync += core.bigendian_i.eq(self.core_bigendian_i)
 349                     # set RA_OR_ZERO detection in satellite decoders
 350                     sync += core.sv_a_nz.eq(pdecode2.sv_a_nz)
 351                     # loop into ISSUE_START if it's a SVP64 instruction
 352                     # and VL == 0.  this because VL==0 is a for-loop
 353                     # from 0 to 0 i.e. always, always a NOP.
 354                     cur_vl = cur_state.svstate.vl
 355                     with m.If(is_svp64_mode & (cur_vl == 0)):
 356                         # update the PC before fetching the next instruction
 357                         # since we are in a VL==0 loop, no instruction was
 358                         # executed that we could be overwriting
 359                         comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
 360                         comb += self.state_w_pc.data_i.eq(nia)
 361                         comb += self.insn_done.eq(1)
 362                         m.next = "ISSUE_START"
 363                     with m.Else():
 364                         m.next = "INSN_EXECUTE"  # move to "execute"
 365
 366             # handshake with execution FSM, move to "wait" once acknowledged
 367             with m.State("INSN_EXECUTE"):
 368                 # with m.If(is_svp64_mode):
 369                 #    TODO advance src/dst step to "skip" over predicated-out
 370                 #    from self.srcmask and self.dstmask
 371                 #    https://bugs.libre-soc.org/show_bug.cgi?id=617#c3
 372                 #    but still without exceeding VL in either case
 373                 comb += exec_insn_valid_i.eq(1) # trigger execute
 374                 with m.If(exec_insn_ready_o):   # execute acknowledged us
 375                     m.next = "EXECUTE_WAIT"
 376
 377             with m.State("EXECUTE_WAIT"):
 378                 # wait on "core stop" release, at instruction end
 379                 # need to do this here, in case we are in a VL>1 loop
 380                 with m.If(~dbg.core_stop_o & ~core_rst):
 381                     comb += exec_pc_ready_i.eq(1)
 382                     with m.If(exec_pc_valid_o):
 383                         # precalculate srcstep+1 and dststep+1
 384                         next_srcstep = Signal.like(cur_state.svstate.srcstep)
 385                         next_dststep = Signal.like(cur_state.svstate.dststep)
 386                         comb += next_srcstep.eq(cur_state.svstate.srcstep+1)
 387                         comb += next_dststep.eq(cur_state.svstate.dststep+1)
 388
 389                         # was this the last loop iteration?
 390                         is_last = Signal()
 391                         cur_vl = cur_state.svstate.vl
 392                         comb += is_last.eq(next_srcstep == cur_vl)
 393
 394                         # if either PC or SVSTATE were changed by the previous
 395                         # instruction, go directly back to Fetch, without
 396                         # updating either PC or SVSTATE
 397                         with m.If(pc_changed | sv_changed):
 398                             m.next = "ISSUE_START"
 399
 400                         # also return to Fetch, when no output was a vector
 401                         # (regardless of SRCSTEP and VL), or when the last
 402                         # instruction was really the last one of the VL loop
 403                         with m.Elif((~pdecode2.loop_continue) | is_last):
 404                             # before going back to fetch, update the PC state
 405                             # register with the NIA.
 406                             # ok here we are not reading the branch unit.
 407                             # TODO: this just blithely overwrites whatever
 408                             #       pipeline updated the PC
 409                             comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
 410                             comb += self.state_w_pc.data_i.eq(nia)
 411                             # reset SRCSTEP before returning to Fetch
 412                             with m.If(pdecode2.loop_continue):
 413                                 comb += new_svstate.srcstep.eq(0)
 414                                 comb += new_svstate.dststep.eq(0)
 415                                 comb += update_svstate.eq(1)
 416                             m.next = "ISSUE_START"
 417
 418                         # returning to Execute? then, first update SRCSTEP
 419                         with m.Else():
 420                             comb += new_svstate.srcstep.eq(next_srcstep)
 421                             comb += new_svstate.dststep.eq(next_dststep)
 422                             comb += update_svstate.eq(1)
 423                             m.next = "DECODE_SV"
 424
 425                 with m.Else():
 426                     comb += core.core_stopped_i.eq(1)
 427                     comb += dbg.core_stopped_i.eq(1)
 428                     # while stopped, allow updating the PC and SVSTATE
 429                     with m.If(self.pc_i.ok):
 430                         comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
 431                         comb += self.state_w_pc.data_i.eq(self.pc_i.data)
 432                         sync += pc_changed.eq(1)
 433                     with m.If(self.svstate_i.ok):
 434                         comb += new_svstate.eq(self.svstate_i.data)
 435                         comb += update_svstate.eq(1)
 436                         sync += sv_changed.eq(1)
 437
 438             # need to decode the instruction again, after updating SRCSTEP
 439             # in the previous state.
 440             # mostly a copy of INSN_WAIT, but without the actual wait
 441             with m.State("DECODE_SV"):
 442                 # decode the instruction
 443                 sync += core.e.eq(pdecode2.e)
 444                 sync += core.state.eq(cur_state)
 445                 sync += core.bigendian_i.eq(self.core_bigendian_i)
 446                 sync += core.sv_a_nz.eq(pdecode2.sv_a_nz)
 447                 m.next = "INSN_EXECUTE"  # move to "execute"
 448
 449         # check if svstate needs updating: if so, write it to State Regfile
 450         with m.If(update_svstate):
 451             comb += self.state_w_sv.wen.eq(1<<StateRegs.SVSTATE)
 452             comb += self.state_w_sv.data_i.eq(new_svstate)
 453             sync += cur_state.svstate.eq(new_svstate) # for next clock
 454
 455     def execute_fsm(self, m, core, pc_changed, sv_changed,
 456                     exec_insn_valid_i, exec_insn_ready_o,
 457                     exec_pc_valid_o, exec_pc_ready_i):
 458         """execute FSM
 459
 460         execute FSM. this interacts with the "issue" FSM
 461         through exec_insn_ready/valid (incoming) and exec_pc_ready/valid
 462         (outgoing). SVP64 RM prefixes have already been set up by the
 463         "issue" phase, so execute is fairly straightforward.
 464         """
 465
 466         comb = m.d.comb
 467         sync = m.d.sync
 468         pdecode2 = self.pdecode2
 469
 470         # temporaries
 471         core_busy_o = core.busy_o                 # core is busy
 472         core_ivalid_i = core.ivalid_i             # instruction is valid
 473         core_issue_i = core.issue_i               # instruction is issued
 474         insn_type = core.e.do.insn_type           # instruction MicroOp type
 475
 476         with m.FSM(name="exec_fsm"):
 477
 478             # waiting for instruction bus (stays there until not busy)
 479             with m.State("INSN_START"):
 480                 comb += exec_insn_ready_o.eq(1)
 481                 with m.If(exec_insn_valid_i):
 482                     comb += core_ivalid_i.eq(1)  # instruction is valid
 483                     comb += core_issue_i.eq(1)  # and issued
 484                     sync += sv_changed.eq(0)
 485                     sync += pc_changed.eq(0)
 486                     m.next = "INSN_ACTIVE"  # move to "wait completion"
 487
 488             # instruction started: must wait till it finishes
 489             with m.State("INSN_ACTIVE"):
 490                 with m.If(insn_type != MicrOp.OP_NOP):
 491                     comb += core_ivalid_i.eq(1) # instruction is valid
 492                 # note changes to PC and SVSTATE
 493                 with m.If(self.state_nia.wen & (1<<StateRegs.SVSTATE)):
 494                     sync += sv_changed.eq(1)
 495                 with m.If(self.state_nia.wen & (1<<StateRegs.PC)):
 496                     sync += pc_changed.eq(1)
 497                 with m.If(~core_busy_o): # instruction done!
 498                     comb += exec_pc_valid_o.eq(1)
 499                     with m.If(exec_pc_ready_i):
 500                         comb += self.insn_done.eq(1)
 501                         m.next = "INSN_START"  # back to fetch
 502
 503     def elaborate(self, platform):
 504         m = Module()
 505         comb, sync = m.d.comb, m.d.sync
 506
 507         m.submodules.core = core = DomainRenamer("coresync")(self.core)
 508         m.submodules.imem = imem = self.imem
 509         m.submodules.dbg = dbg = self.dbg
 510         if self.jtag_en:
 511             m.submodules.jtag = jtag = self.jtag
 512             # TODO: UART2GDB mux, here, from external pin
 513             # see https://bugs.libre-soc.org/show_bug.cgi?id=499
 514             sync += dbg.dmi.connect_to(jtag.dmi)
 515
 516         cur_state = self.cur_state
 517
 518         # 4x 4k SRAM blocks.  these simply "exist", they get routed in litex
 519         if self.sram4x4k:
 520             for i, sram in enumerate(self.sram4k):
 521                 m.submodules["sram4k_%d" % i] = sram
 522                 comb += sram.enable.eq(self.wb_sram_en)
 523
 524         # XICS interrupt handler
 525         if self.xics:
 526             m.submodules.xics_icp = icp = self.xics_icp
 527             m.submodules.xics_ics = ics = self.xics_ics
 528             comb += icp.ics_i.eq(ics.icp_o)           # connect ICS to ICP
 529             sync += cur_state.eint.eq(icp.core_irq_o) # connect ICP to core
 530
 531         # GPIO test peripheral
 532         if self.gpio:
 533             m.submodules.simple_gpio = simple_gpio = self.simple_gpio
 534
 535         # connect one GPIO output to ICS bit 15 (like in microwatt soc.vhdl)
 536         # XXX causes litex ECP5 test to get wrong idea about input and output
 537         # (but works with verilator sim *sigh*)
 538         #if self.gpio and self.xics:
 539         #   comb += self.int_level_i[15].eq(simple_gpio.gpio_o[0])
 540
 541         # instruction decoder
 542         pdecode = create_pdecode()
 543         m.submodules.dec2 = pdecode2 = self.pdecode2
 544         if self.svp64_en:
 545             m.submodules.svp64 = svp64 = self.svp64
 546
 547         # convenience
 548         dmi, d_reg, d_cr, d_xer, = dbg.dmi, dbg.d_gpr, dbg.d_cr, dbg.d_xer
 549         intrf = self.core.regs.rf['int']
 550
 551         # clock delay power-on reset
 552         cd_por  = ClockDomain(reset_less=True)
 553         cd_sync = ClockDomain()
 554         core_sync = ClockDomain("coresync")
 555         m.domains += cd_por, cd_sync, core_sync
 556
 557         ti_rst = Signal(reset_less=True)
 558         delay = Signal(range(4), reset=3)
 559         with m.If(delay != 0):
 560             m.d.por += delay.eq(delay - 1)
 561         comb += cd_por.clk.eq(ClockSignal())
 562
 563         # power-on reset delay
 564         core_rst = ResetSignal("coresync")
 565         comb += ti_rst.eq(delay != 0 | dbg.core_rst_o | ResetSignal())
 566         comb += core_rst.eq(ti_rst)
 567
 568         # busy/halted signals from core
 569         comb += self.busy_o.eq(core.busy_o)
 570         comb += pdecode2.dec.bigendian.eq(self.core_bigendian_i)
 571
 572         # temporary hack: says "go" immediately for both address gen and ST
 573         l0 = core.l0
 574         ldst = core.fus.fus['ldst0']
 575         st_go_edge = rising_edge(m, ldst.st.rel_o)
 576         m.d.comb += ldst.ad.go_i.eq(ldst.ad.rel_o) # link addr-go direct to rel
 577         m.d.comb += ldst.st.go_i.eq(st_go_edge) # link store-go to rising rel
 578
 579         # PC and instruction from I-Memory
 580         comb += self.pc_o.eq(cur_state.pc)
 581         pc_changed = Signal() # note write to PC
 582         sv_changed = Signal() # note write to SVSTATE
 583
 584         # read the PC
 585         pc = Signal(64, reset_less=True)
 586         pc_ok_delay = Signal()
 587         sync += pc_ok_delay.eq(~self.pc_i.ok)
 588         with m.If(self.pc_i.ok):
 589             # incoming override (start from pc_i)
 590             comb += pc.eq(self.pc_i.data)
 591         with m.Else():
 592             # otherwise read StateRegs regfile for PC...
 593             comb += self.state_r_pc.ren.eq(1<<StateRegs.PC)
 594         # ... but on a 1-clock delay
 595         with m.If(pc_ok_delay):
 596             comb += pc.eq(self.state_r_pc.data_o)
 597
 598         # read svstate
 599         svstate = Signal(64, reset_less=True)
 600         svstate_ok_delay = Signal()
 601         sync += svstate_ok_delay.eq(~self.svstate_i.ok)
 602         with m.If(self.svstate_i.ok):
 603             # incoming override (start from svstate__i)
 604             comb += svstate.eq(self.svstate_i.data)
 605         with m.Else():
 606             # otherwise read StateRegs regfile for SVSTATE...
 607             comb += self.state_r_sv.ren.eq(1 << StateRegs.SVSTATE)
 608         # ... but on a 1-clock delay
 609         with m.If(svstate_ok_delay):
 610             comb += svstate.eq(self.state_r_sv.data_o)
 611
 612         # don't write pc every cycle
 613         comb += self.state_w_pc.wen.eq(0)
 614         comb += self.state_w_pc.data_i.eq(0)
 615
 616         # don't read msr every cycle
 617         comb += self.state_r_msr.ren.eq(0)
 618
 619         # address of the next instruction, in the absence of a branch
 620         # depends on the instruction size
 621         nia = Signal(64, reset_less=True)
 622
 623         # connect up debug signals
 624         # TODO comb += core.icache_rst_i.eq(dbg.icache_rst_o)
 625         comb += dbg.terminate_i.eq(core.core_terminate_o)
 626         comb += dbg.state.pc.eq(pc)
 627         comb += dbg.state.svstate.eq(svstate)
 628         comb += dbg.state.msr.eq(cur_state.msr)
 629
 630         # pass the prefix mode from Fetch to Issue, so the latter can loop
 631         # on VL==0
 632         is_svp64_mode = Signal()
 633
 634         # there are *THREE* FSMs, fetch (32/64-bit) issue, decode/execute.
 635         # these are the handshake signals between fetch and decode/execute
 636
 637         # fetch FSM can run as soon as the PC is valid
 638         fetch_pc_valid_i = Signal() # Execute tells Fetch "start next read"
 639         fetch_pc_ready_o = Signal() # Fetch Tells SVSTATE "proceed"
 640
 641         # fetch FSM hands over the instruction to be decoded / issued
 642         fetch_insn_valid_o = Signal()
 643         fetch_insn_ready_i = Signal()
 644
 645         # issue FSM delivers the instruction to the be executed
 646         exec_insn_valid_i = Signal()
 647         exec_insn_ready_o = Signal()
 648
 649         # execute FSM, hands over the PC/SVSTATE back to the issue FSM
 650         exec_pc_valid_o = Signal()
 651         exec_pc_ready_i = Signal()
 652
 653         # the FSMs here are perhaps unusual in that they detect conditions
 654         # then "hold" information, combinatorially, for the core
 655         # (as opposed to using sync - which would be on a clock's delay)
 656         # this includes the actual opcode, valid flags and so on.
 657
 658         # Fetch, then Issue, then Execute. Issue is where the VL for-loop
 659         # lives.  the ready/valid signalling is used to communicate between
 660         # the three.
 661
 662         self.fetch_fsm(m, core, pc, svstate, nia, is_svp64_mode,
 663                        fetch_pc_ready_o, fetch_pc_valid_i,
 664                        fetch_insn_valid_o, fetch_insn_ready_i)
 665
 666         self.issue_fsm(m, core, pc_changed, sv_changed, nia,
 667                        dbg, core_rst, is_svp64_mode,
 668                        fetch_pc_ready_o, fetch_pc_valid_i,
 669                        fetch_insn_valid_o, fetch_insn_ready_i,
 670                        exec_insn_valid_i, exec_insn_ready_o,
 671                        exec_pc_valid_o, exec_pc_ready_i)
 672
 673         self.execute_fsm(m, core, pc_changed, sv_changed,
 674                          exec_insn_valid_i, exec_insn_ready_o,
 675                          exec_pc_valid_o, exec_pc_ready_i)
 676
 677         # this bit doesn't have to be in the FSM: connect up to read
 678         # regfiles on demand from DMI
 679         self.do_dmi(m, dbg)
 680
 681         # DEC and TB inc/dec FSM.  copy of DEC is put into CoreState,
 682         # (which uses that in PowerDecoder2 to raise 0x900 exception)
 683         self.tb_dec_fsm(m, cur_state.dec)
 684
 685         return m
 686
 687     def do_dmi(self, m, dbg):
 688         comb = m.d.comb
 689         sync = m.d.sync
 690         dmi, d_reg, d_cr, d_xer, = dbg.dmi, dbg.d_gpr, dbg.d_cr, dbg.d_xer
 691         intrf = self.core.regs.rf['int']
 692
 693         with m.If(d_reg.req): # request for regfile access being made
 694             # TODO: error-check this
 695             # XXX should this be combinatorial?  sync better?
 696             if intrf.unary:
 697                 comb += self.int_r.ren.eq(1<<d_reg.addr)
 698             else:
 699                 comb += self.int_r.addr.eq(d_reg.addr)
 700                 comb += self.int_r.ren.eq(1)
 701         d_reg_delay  = Signal()
 702         sync += d_reg_delay.eq(d_reg.req)
 703         with m.If(d_reg_delay):
 704             # data arrives one clock later
 705             comb += d_reg.data.eq(self.int_r.data_o)
 706             comb += d_reg.ack.eq(1)
 707
 708         # sigh same thing for CR debug
 709         with m.If(d_cr.req): # request for regfile access being made
 710             comb += self.cr_r.ren.eq(0b11111111) # enable all
 711         d_cr_delay  = Signal()
 712         sync += d_cr_delay.eq(d_cr.req)
 713         with m.If(d_cr_delay):
 714             # data arrives one clock later
 715             comb += d_cr.data.eq(self.cr_r.data_o)
 716             comb += d_cr.ack.eq(1)
 717
 718         # aaand XER...
 719         with m.If(d_xer.req): # request for regfile access being made
 720             comb += self.xer_r.ren.eq(0b111111) # enable all
 721         d_xer_delay  = Signal()
 722         sync += d_xer_delay.eq(d_xer.req)
 723         with m.If(d_xer_delay):
 724             # data arrives one clock later
 725             comb += d_xer.data.eq(self.xer_r.data_o)
 726             comb += d_xer.ack.eq(1)
 727
 728     def tb_dec_fsm(self, m, spr_dec):
 729         """tb_dec_fsm
 730
 731         this is a FSM for updating either dec or tb.  it runs alternately
 732         DEC, TB, DEC, TB.  note that SPR pipeline could have written a new
 733         value to DEC, however the regfile has "passthrough" on it so this
 734         *should* be ok.
 735
 736         see v3.0B p1097-1099 for Timeer Resource and p1065 and p1076
 737         """
 738
 739         comb, sync = m.d.comb, m.d.sync
 740         fast_rf = self.core.regs.rf['fast']
 741         fast_r_dectb = fast_rf.r_ports['issue'] # DEC/TB
 742         fast_w_dectb = fast_rf.w_ports['issue'] # DEC/TB
 743
 744         with m.FSM() as fsm:
 745
 746             # initiates read of current DEC
 747             with m.State("DEC_READ"):
 748                 comb += fast_r_dectb.addr.eq(FastRegs.DEC)
 749                 comb += fast_r_dectb.ren.eq(1)
 750                 m.next = "DEC_WRITE"
 751
 752             # waits for DEC read to arrive (1 cycle), updates with new value
 753             with m.State("DEC_WRITE"):
 754                 new_dec = Signal(64)
 755                 # TODO: MSR.LPCR 32-bit decrement mode
 756                 comb += new_dec.eq(fast_r_dectb.data_o - 1)
 757                 comb += fast_w_dectb.addr.eq(FastRegs.DEC)
 758                 comb += fast_w_dectb.wen.eq(1)
 759                 comb += fast_w_dectb.data_i.eq(new_dec)
 760                 sync += spr_dec.eq(new_dec) # copy into cur_state for decoder
 761                 m.next = "TB_READ"
 762
 763             # initiates read of current TB
 764             with m.State("TB_READ"):
 765                 comb += fast_r_dectb.addr.eq(FastRegs.TB)
 766                 comb += fast_r_dectb.ren.eq(1)
 767                 m.next = "TB_WRITE"
 768
 769             # waits for read TB to arrive, initiates write of current TB
 770             with m.State("TB_WRITE"):
 771                 new_tb = Signal(64)
 772                 comb += new_tb.eq(fast_r_dectb.data_o + 1)
 773                 comb += fast_w_dectb.addr.eq(FastRegs.TB)
 774                 comb += fast_w_dectb.wen.eq(1)
 775                 comb += fast_w_dectb.data_i.eq(new_tb)
 776                 m.next = "DEC_READ"
 777
 778         return m
 779
 780     def __iter__(self):
 781         yield from self.pc_i.ports()
 782         yield self.pc_o
 783         yield self.memerr_o
 784         yield from self.core.ports()
 785         yield from self.imem.ports()
 786         yield self.core_bigendian_i
 787         yield self.busy_o
 788
 789     def ports(self):
 790         return list(self)
 791
 792     def external_ports(self):
 793         ports = self.pc_i.ports()
 794         ports += [self.pc_o, self.memerr_o, self.core_bigendian_i, self.busy_o,
 795                 ]
 796
 797         if self.jtag_en:
 798             ports += list(self.jtag.external_ports())
 799         else:
 800             # don't add DMI if JTAG is enabled
 801             ports += list(self.dbg.dmi.ports())
 802
 803         ports += list(self.imem.ibus.fields.values())
 804         ports += list(self.core.l0.cmpi.lsmem.lsi.slavebus.fields.values())
 805
 806         if self.sram4x4k:
 807             for sram in self.sram4k:
 808                 ports += list(sram.bus.fields.values())
 809
 810         if self.xics:
 811             ports += list(self.xics_icp.bus.fields.values())
 812             ports += list(self.xics_ics.bus.fields.values())
 813             ports.append(self.int_level_i)
 814
 815         if self.gpio:
 816             ports += list(self.simple_gpio.bus.fields.values())
 817             ports.append(self.gpio_o)
 818
 819         return ports
 820
 821     def ports(self):
 822         return list(self)
 823
 824
 825 class TestIssuer(Elaboratable):
 826     def __init__(self, pspec):
 827         self.ti = TestIssuerInternal(pspec)
 828
 829         self.pll = DummyPLL()
 830
 831         # PLL direct clock or not
 832         self.pll_en = hasattr(pspec, "use_pll") and pspec.use_pll
 833         if self.pll_en:
 834             self.pll_18_o = Signal(reset_less=True)
 835
 836     def elaborate(self, platform):
 837         m = Module()
 838         comb = m.d.comb
 839
 840         # TestIssuer runs at direct clock
 841         m.submodules.ti = ti = self.ti
 842         cd_int = ClockDomain("coresync")
 843
 844         if self.pll_en:
 845             # ClockSelect runs at PLL output internal clock rate
 846             m.submodules.pll = pll = self.pll
 847
 848             # add clock domains from PLL
 849             cd_pll = ClockDomain("pllclk")
 850             m.domains += cd_pll
 851
 852             # PLL clock established.  has the side-effect of running clklsel
 853             # at the PLL's speed (see DomainRenamer("pllclk") above)
 854             pllclk = ClockSignal("pllclk")
 855             comb += pllclk.eq(pll.clk_pll_o)
 856
 857             # wire up external 24mhz to PLL
 858             comb += pll.clk_24_i.eq(ClockSignal())
 859
 860             # output 18 mhz PLL test signal
 861             comb += self.pll_18_o.eq(pll.pll_18_o)
 862
 863             # now wire up ResetSignals.  don't mind them being in this domain
 864             pll_rst = ResetSignal("pllclk")
 865             comb += pll_rst.eq(ResetSignal())
 866
 867         # internal clock is set to selector clock-out.  has the side-effect of
 868         # running TestIssuer at this speed (see DomainRenamer("intclk") above)
 869         intclk = ClockSignal("coresync")
 870         if self.pll_en:
 871             comb += intclk.eq(pll.clk_pll_o)
 872         else:
 873             comb += intclk.eq(ClockSignal())
 874
 875         return m
 876
 877     def ports(self):
 878         return list(self.ti.ports()) + list(self.pll.ports()) + \
 879                [ClockSignal(), ResetSignal()]
 880
 881     def external_ports(self):
 882         ports = self.ti.external_ports()
 883         ports.append(ClockSignal())
 884         ports.append(ResetSignal())
 885         if self.pll_en:
 886             ports.append(self.pll.clk_sel_i)
 887             ports.append(self.pll_18_o)
 888             ports.append(self.pll.pll_lck_o)
 889         return ports
 890
 891
 892 if __name__ == '__main__':
 893     units = {'alu': 1, 'cr': 1, 'branch': 1, 'trap': 1, 'logical': 1,
 894              'spr': 1,
 895              'div': 1,
 896              'mul': 1,
 897              'shiftrot': 1
 898             }
 899     pspec = TestMemPspec(ldst_ifacetype='bare_wb',
 900                          imem_ifacetype='bare_wb',
 901                          addr_wid=48,
 902                          mask_wid=8,
 903                          reg_wid=64,
 904                          units=units)
 905     dut = TestIssuer(pspec)
 906     vl = main(dut, ports=dut.ports(), name="test_issuer")
 907
 908     if len(sys.argv) == 1:
 909         vl = rtlil.convert(dut, ports=dut.external_ports(), name="test_issuer")
 910         with open("test_issuer.il", "w") as f:
 911             f.write(vl)