3 not in any way intended for production use. this runs a FSM that:
5 * reads the Program Counter from StateRegs
6 * reads an instruction from a fixed-size Test Memory
7 * issues it to the Simple Core
8 * waits for it to complete
10 * does it all over again
12 the purpose of this module is to verify the functional correctness
13 of the Function Units in the absolute simplest and clearest possible
14 way, and to at provide something that can be further incrementally
18 from nmigen
import (Elaboratable
, Module
, Signal
, ClockSignal
, ResetSignal
,
19 ClockDomain
, DomainRenamer
, Mux
, Const
, Repl
, Cat
)
20 from nmigen
.cli
import rtlil
21 from nmigen
.cli
import main
24 from nmutil
.singlepipe
import ControlBase
25 from soc
.simple
.core_data
import FetchOutput
, FetchInput
27 from nmigen
.lib
.coding
import PriorityEncoder
29 from openpower
.decoder
.power_decoder
import create_pdecode
30 from openpower
.decoder
.power_decoder2
import PowerDecode2
, SVP64PrefixDecoder
31 from openpower
.decoder
.decode2execute1
import IssuerDecode2ToOperand
32 from openpower
.decoder
.decode2execute1
import Data
33 from openpower
.decoder
.power_enums
import (MicrOp
, SVP64PredInt
, SVP64PredCR
,
35 from openpower
.state
import CoreState
36 from openpower
.consts
import (CR
, SVP64CROffs
, MSR
)
37 from soc
.experiment
.testmem
import TestMemory
# test only for instructions
38 from soc
.regfile
.regfiles
import StateRegs
, FastRegs
39 from soc
.simple
.core
import NonProductionCore
40 from soc
.config
.test
.test_loadstore
import TestMemPspec
41 from soc
.config
.ifetch
import ConfigFetchUnit
42 from soc
.debug
.dmi
import CoreDebug
, DMIInterface
43 from soc
.debug
.jtag
import JTAG
44 from soc
.config
.pinouts
import get_pinspecs
45 from soc
.interrupts
.xics
import XICS_ICP
, XICS_ICS
46 from soc
.bus
.simple_gpio
import SimpleGPIO
47 from soc
.bus
.SPBlock512W64B8W
import SPBlock512W64B8W
48 from soc
.clock
.select
import ClockSelect
49 from soc
.clock
.dummypll
import DummyPLL
50 from openpower
.sv
.svstate
import SVSTATERec
51 from soc
.experiment
.icache
import ICache
53 from nmutil
.util
import rising_edge
56 def get_insn(f_instr_o
, pc
):
57 if f_instr_o
.width
== 32:
60 # 64-bit: bit 2 of pc decides which word to select
61 return f_instr_o
.word_select(pc
[2], 32)
63 # gets state input or reads from state regfile
66 def state_get(m
, res
, core_rst
, state_i
, name
, regfile
, regnum
):
69 # read the {insert state variable here}
70 res_ok_delay
= Signal(name
="%s_ok_delay" % name
)
72 sync
+= res_ok_delay
.eq(~state_i
.ok
)
73 with m
.If(state_i
.ok
):
74 # incoming override (start from pc_i)
75 comb
+= res
.eq(state_i
.data
)
77 # otherwise read StateRegs regfile for {insert state here}...
78 comb
+= regfile
.ren
.eq(1 << regnum
)
79 # ... but on a 1-clock delay
80 with m
.If(res_ok_delay
):
81 comb
+= res
.eq(regfile
.o_data
)
84 def get_predint(m
, mask
, name
):
85 """decode SVP64 predicate integer mask field to reg number and invert
86 this is identical to the equivalent function in ISACaller except that
87 it doesn't read the INT directly, it just decodes "what needs to be done"
88 i.e. which INT reg, whether it is shifted and whether it is bit-inverted.
90 * all1s is set to indicate that no mask is to be applied.
91 * regread indicates the GPR register number to be read
92 * invert is set to indicate that the register value is to be inverted
93 * unary indicates that the contents of the register is to be shifted 1<<r3
96 regread
= Signal(5, name
=name
+"regread")
97 invert
= Signal(name
=name
+"invert")
98 unary
= Signal(name
=name
+"unary")
99 all1s
= Signal(name
=name
+"all1s")
101 with m
.Case(SVP64PredInt
.ALWAYS
.value
):
102 comb
+= all1s
.eq(1) # use 0b1111 (all ones)
103 with m
.Case(SVP64PredInt
.R3_UNARY
.value
):
104 comb
+= regread
.eq(3)
105 comb
+= unary
.eq(1) # 1<<r3 - shift r3 (single bit)
106 with m
.Case(SVP64PredInt
.R3
.value
):
107 comb
+= regread
.eq(3)
108 with m
.Case(SVP64PredInt
.R3_N
.value
):
109 comb
+= regread
.eq(3)
111 with m
.Case(SVP64PredInt
.R10
.value
):
112 comb
+= regread
.eq(10)
113 with m
.Case(SVP64PredInt
.R10_N
.value
):
114 comb
+= regread
.eq(10)
116 with m
.Case(SVP64PredInt
.R30
.value
):
117 comb
+= regread
.eq(30)
118 with m
.Case(SVP64PredInt
.R30_N
.value
):
119 comb
+= regread
.eq(30)
121 return regread
, invert
, unary
, all1s
124 def get_predcr(m
, mask
, name
):
125 """decode SVP64 predicate CR to reg number field and invert status
126 this is identical to _get_predcr in ISACaller
129 idx
= Signal(2, name
=name
+"idx")
130 invert
= Signal(name
=name
+"crinvert")
132 with m
.Case(SVP64PredCR
.LT
.value
):
133 comb
+= idx
.eq(CR
.LT
)
135 with m
.Case(SVP64PredCR
.GE
.value
):
136 comb
+= idx
.eq(CR
.LT
)
138 with m
.Case(SVP64PredCR
.GT
.value
):
139 comb
+= idx
.eq(CR
.GT
)
141 with m
.Case(SVP64PredCR
.LE
.value
):
142 comb
+= idx
.eq(CR
.GT
)
144 with m
.Case(SVP64PredCR
.EQ
.value
):
145 comb
+= idx
.eq(CR
.EQ
)
147 with m
.Case(SVP64PredCR
.NE
.value
):
148 comb
+= idx
.eq(CR
.EQ
)
150 with m
.Case(SVP64PredCR
.SO
.value
):
151 comb
+= idx
.eq(CR
.SO
)
153 with m
.Case(SVP64PredCR
.NS
.value
):
154 comb
+= idx
.eq(CR
.SO
)
159 class TestIssuerBase(Elaboratable
):
160 """TestIssuerBase - common base class for Issuers
162 takes care of power-on reset, peripherals, debug, DEC/TB,
163 and gets PC/MSR/SVSTATE from the State Regfile etc.
166 def __init__(self
, pspec
):
168 # test if microwatt compatibility is to be enabled
169 self
.microwatt_compat
= (hasattr(pspec
, "microwatt_compat") and
170 (pspec
.microwatt_compat
== True))
171 self
.alt_reset
= Signal(reset_less
=True) # not connected yet (microwatt)
173 if self
.microwatt_compat
:
174 self
.microwatt_old
= True # PLEASE DO NOT ALTER THIS
175 self
.microwatt_debug
= True # set to False when using an FPGA
177 # test is SVP64 is to be enabled
178 self
.svp64_en
= hasattr(pspec
, "svp64") and (pspec
.svp64
== True)
180 # and if regfiles are reduced
181 self
.regreduce_en
= (hasattr(pspec
, "regreduce") and
182 (pspec
.regreduce
== True))
184 # and if overlap requested
185 self
.allow_overlap
= (hasattr(pspec
, "allow_overlap") and
186 (pspec
.allow_overlap
== True))
188 # and get the core domain
189 self
.core_domain
= "coresync"
190 if (hasattr(pspec
, "core_domain") and
191 isinstance(pspec
.core_domain
, str)):
192 self
.core_domain
= pspec
.core_domain
194 # JTAG interface. add this right at the start because if it's
195 # added it *modifies* the pspec, by adding enable/disable signals
196 # for parts of the rest of the core
197 self
.jtag_en
= hasattr(pspec
, "debug") and pspec
.debug
== 'jtag'
198 #self.dbg_domain = "sync" # sigh "dbgsunc" too problematic
199 self
.dbg_domain
= "dbgsync" # domain for DMI/JTAG clock
201 # XXX MUST keep this up-to-date with litex, and
202 # soc-cocotb-sim, and err.. all needs sorting out, argh
205 'eint', 'gpio', 'mspi0',
206 # 'mspi1', - disabled for now
207 # 'pwm', 'sd0', - disabled for now
209 self
.jtag
= JTAG(get_pinspecs(subset
=subset
),
210 domain
=self
.dbg_domain
)
211 # add signals to pspec to enable/disable icache and dcache
212 # (or data and intstruction wishbone if icache/dcache not included)
213 # https://bugs.libre-soc.org/show_bug.cgi?id=520
214 # TODO: do we actually care if these are not domain-synchronised?
215 # honestly probably not.
216 pspec
.wb_icache_en
= self
.jtag
.wb_icache_en
217 pspec
.wb_dcache_en
= self
.jtag
.wb_dcache_en
218 self
.wb_sram_en
= self
.jtag
.wb_sram_en
220 self
.wb_sram_en
= Const(1)
222 # add 4k sram blocks?
223 self
.sram4x4k
= (hasattr(pspec
, "sram4x4kblock") and
224 pspec
.sram4x4kblock
== True)
228 self
.sram4k
.append(SPBlock512W64B8W(name
="sram4k_%d" % i
,
232 # add interrupt controller?
233 self
.xics
= hasattr(pspec
, "xics") and pspec
.xics
== True
235 self
.xics_icp
= XICS_ICP()
236 self
.xics_ics
= XICS_ICS()
237 self
.int_level_i
= self
.xics_ics
.int_level_i
239 self
.ext_irq
= Signal()
241 # add GPIO peripheral?
242 self
.gpio
= hasattr(pspec
, "gpio") and pspec
.gpio
== True
244 self
.simple_gpio
= SimpleGPIO()
245 self
.gpio_o
= self
.simple_gpio
.gpio_o
247 # main instruction core. suitable for prototyping / demo only
248 self
.core
= core
= NonProductionCore(pspec
)
249 self
.core_rst
= ResetSignal(self
.core_domain
)
251 # instruction decoder. goes into Trap Record
252 #pdecode = create_pdecode()
253 self
.cur_state
= CoreState("cur") # current state (MSR/PC/SVSTATE)
254 self
.pdecode2
= PowerDecode2(None, state
=self
.cur_state
,
255 opkls
=IssuerDecode2ToOperand
,
256 svp64_en
=self
.svp64_en
,
257 regreduce_en
=self
.regreduce_en
)
258 pdecode
= self
.pdecode2
.dec
261 self
.svp64
= SVP64PrefixDecoder() # for decoding SVP64 prefix
263 self
.update_svstate
= Signal() # set this if updating svstate
264 self
.new_svstate
= new_svstate
= SVSTATERec("new_svstate")
266 # Test Instruction memory
267 if hasattr(core
, "icache"):
268 # XXX BLECH! use pspec to transfer the I-Cache to ConfigFetchUnit
269 # truly dreadful. needs a huge reorg.
270 pspec
.icache
= core
.icache
271 self
.imem
= ConfigFetchUnit(pspec
).fu
274 self
.dbg
= CoreDebug()
275 self
.dbg_rst_i
= Signal(reset_less
=True)
277 # instruction go/monitor
278 self
.pc_o
= Signal(64, reset_less
=True)
279 self
.pc_i
= Data(64, "pc_i") # set "ok" to indicate "please change me"
280 self
.msr_i
= Data(64, "msr_i") # set "ok" to indicate "please change me"
281 self
.svstate_i
= Data(64, "svstate_i") # ditto
282 self
.core_bigendian_i
= Signal() # TODO: set based on MSR.LE
283 self
.busy_o
= Signal(reset_less
=True)
284 self
.memerr_o
= Signal(reset_less
=True)
286 # STATE regfile read /write ports for PC, MSR, SVSTATE
287 staterf
= self
.core
.regs
.rf
['state']
288 self
.state_r_msr
= staterf
.r_ports
['msr'] # MSR rd
289 self
.state_r_pc
= staterf
.r_ports
['cia'] # PC rd
290 self
.state_r_sv
= staterf
.r_ports
['sv'] # SVSTATE rd
292 self
.state_w_msr
= staterf
.w_ports
['d_wr2'] # MSR wr
293 self
.state_w_pc
= staterf
.w_ports
['d_wr1'] # PC wr
294 self
.state_w_sv
= staterf
.w_ports
['sv'] # SVSTATE wr
296 # DMI interface access
297 intrf
= self
.core
.regs
.rf
['int']
298 fastrf
= self
.core
.regs
.rf
['fast']
299 crrf
= self
.core
.regs
.rf
['cr']
300 xerrf
= self
.core
.regs
.rf
['xer']
301 self
.int_r
= intrf
.r_ports
['dmi'] # INT DMI read
302 self
.cr_r
= crrf
.r_ports
['full_cr_dbg'] # CR DMI read
303 self
.xer_r
= xerrf
.r_ports
['full_xer'] # XER DMI read
304 self
.fast_r
= fastrf
.r_ports
['dmi'] # FAST DMI read
308 self
.int_pred
= intrf
.r_ports
['pred'] # INT predicate read
309 self
.cr_pred
= crrf
.r_ports
['cr_pred'] # CR predicate read
311 # hack method of keeping an eye on whether branch/trap set the PC
312 self
.state_nia
= self
.core
.regs
.rf
['state'].w_ports
['nia']
313 self
.state_nia
.wen
.name
= 'state_nia_wen'
314 # and whether SPR pipeline sets DEC or TB
315 self
.state_spr
= self
.core
.regs
.rf
['state'].w_ports
['state1']
317 # pulse to synchronize the simulator at instruction end
318 self
.insn_done
= Signal()
320 # indicate any instruction still outstanding, in execution
321 self
.any_busy
= Signal()
324 # store copies of predicate masks
325 self
.srcmask
= Signal(64)
326 self
.dstmask
= Signal(64)
328 # sigh, the wishbone addresses are not wishbone-compliant
329 # in old versions of microwatt, tplaten_3d_game is a new one
330 if self
.microwatt_compat
:
331 self
.ibus_adr
= Signal(32, name
='wishbone_insn_out.adr')
332 self
.dbus_adr
= Signal(32, name
='wishbone_data_out.adr')
334 # add an output of the PC and instruction, and whether it was requested
335 # this is for verilator debug purposes
336 if self
.microwatt_compat
:
337 self
.nia
= Signal(64)
338 self
.msr_o
= Signal(64)
339 self
.nia_req
= Signal(1)
340 self
.insn
= Signal(32)
341 self
.ldst_req
= Signal(1)
342 self
.ldst_addr
= Signal(1)
344 # for pausing dec/tb during an SPR pipeline event, this
345 # ensures that an SPR write (mtspr) to TB or DEC does not
346 # get overwritten by the DEC/TB FSM
347 self
.pause_dec_tb
= Signal()
349 def setup_peripherals(self
, m
):
350 comb
, sync
= m
.d
.comb
, m
.d
.sync
352 # okaaaay so the debug module must be in coresync clock domain
353 # but NOT its reset signal. to cope with this, set every single
354 # submodule explicitly in coresync domain, debug and JTAG
355 # in their own one but using *external* reset.
356 csd
= DomainRenamer(self
.core_domain
)
357 dbd
= DomainRenamer(self
.dbg_domain
)
359 if self
.microwatt_compat
:
360 m
.submodules
.core
= core
= self
.core
362 m
.submodules
.core
= core
= csd(self
.core
)
364 # this _so_ needs sorting out. ICache is added down inside
365 # LoadStore1 and is already a submodule of LoadStore1
366 if not isinstance(self
.imem
, ICache
):
367 m
.submodules
.imem
= imem
= csd(self
.imem
)
369 # set up JTAG Debug Module (in correct domain)
370 m
.submodules
.dbg
= dbg
= dbd(self
.dbg
)
372 m
.submodules
.jtag
= jtag
= dbd(self
.jtag
)
373 # TODO: UART2GDB mux, here, from external pin
374 # see https://bugs.libre-soc.org/show_bug.cgi?id=499
375 sync
+= dbg
.dmi
.connect_to(jtag
.dmi
)
377 # fixup the clocks in microwatt-compat mode (but leave resets alone
378 # so that microwatt soc.vhdl can pull a reset on the core or DMI
379 # can do it, just like in TestIssuer)
380 if self
.microwatt_compat
:
381 intclk
= ClockSignal(self
.core_domain
)
382 dbgclk
= ClockSignal(self
.dbg_domain
)
383 if self
.core_domain
!= 'sync':
384 comb
+= intclk
.eq(ClockSignal())
385 if self
.dbg_domain
!= 'sync':
386 comb
+= dbgclk
.eq(ClockSignal())
388 # if using old version of microwatt
389 # drop the first 3 bits of the incoming wishbone addresses
390 if self
.microwatt_compat
:
391 ibus
= self
.imem
.ibus
392 dbus
= self
.core
.l0
.cmpi
.wb_bus()
393 if self
.microwatt_old
:
394 comb
+= self
.ibus_adr
.eq(Cat(Const(0, 3), ibus
.adr
))
395 comb
+= self
.dbus_adr
.eq(Cat(Const(0, 3), dbus
.adr
))
397 comb
+= self
.ibus_adr
.eq(ibus
.adr
)
398 comb
+= self
.dbus_adr
.eq(dbus
.adr
)
399 if self
.microwatt_debug
:
400 # microwatt verilator debug purposes
401 pi
= self
.core
.l0
.cmpi
.pi
.pi
402 comb
+= self
.ldst_req
.eq(pi
.addr_ok_o
)
403 comb
+= self
.ldst_addr
.eq(pi
.addr
)
405 cur_state
= self
.cur_state
407 # 4x 4k SRAM blocks. these simply "exist", they get routed in litex
409 for i
, sram
in enumerate(self
.sram4k
):
410 m
.submodules
["sram4k_%d" % i
] = csd(sram
)
411 comb
+= sram
.enable
.eq(self
.wb_sram_en
)
413 # XICS interrupt handler
415 m
.submodules
.xics_icp
= icp
= csd(self
.xics_icp
)
416 m
.submodules
.xics_ics
= ics
= csd(self
.xics_ics
)
417 comb
+= icp
.ics_i
.eq(ics
.icp_o
) # connect ICS to ICP
418 sync
+= cur_state
.eint
.eq(icp
.core_irq_o
) # connect ICP to core
420 sync
+= cur_state
.eint
.eq(self
.ext_irq
) # connect externally
422 # GPIO test peripheral
424 m
.submodules
.simple_gpio
= simple_gpio
= csd(self
.simple_gpio
)
426 # connect one GPIO output to ICS bit 15 (like in microwatt soc.vhdl)
427 # XXX causes litex ECP5 test to get wrong idea about input and output
428 # (but works with verilator sim *sigh*)
429 # if self.gpio and self.xics:
430 # comb += self.int_level_i[15].eq(simple_gpio.gpio_o[0])
432 # instruction decoder
433 pdecode
= create_pdecode()
434 m
.submodules
.dec2
= pdecode2
= csd(self
.pdecode2
)
436 m
.submodules
.svp64
= svp64
= csd(self
.svp64
)
438 # clock delay power-on reset
439 cd_por
= ClockDomain(reset_less
=True)
440 cd_sync
= ClockDomain()
441 m
.domains
+= cd_por
, cd_sync
442 core_sync
= ClockDomain(self
.core_domain
)
443 if self
.core_domain
!= "sync":
444 m
.domains
+= core_sync
445 if self
.dbg_domain
!= "sync":
446 dbg_sync
= ClockDomain(self
.dbg_domain
)
447 m
.domains
+= dbg_sync
449 # create a delay, but remember it is in the power-on-reset clock domain!
450 ti_rst
= Signal(reset_less
=True)
451 delay
= Signal(range(4), reset
=3)
452 stop_delay
= Signal(range(16), reset
=5)
453 with m
.If(delay
!= 0):
454 m
.d
.por
+= delay
.eq(delay
- 1) # decrement... in POR domain!
455 with m
.If(stop_delay
!= 0):
456 m
.d
.por
+= stop_delay
.eq(stop_delay
- 1) # likewise
457 comb
+= cd_por
.clk
.eq(ClockSignal())
459 # power-on reset delay
460 core_rst
= ResetSignal(self
.core_domain
)
461 if self
.core_domain
!= "sync":
462 comb
+= ti_rst
.eq(delay
!= 0 | dbg
.core_rst_o |
ResetSignal())
463 comb
+= core_rst
.eq(ti_rst
)
465 with m
.If(delay
!= 0 | dbg
.core_rst_o
):
466 comb
+= core_rst
.eq(1)
467 with m
.If(stop_delay
!= 0):
468 # run DMI core-stop as well but on an extra couple of cycles
469 comb
+= dbg
.core_stopped_i
.eq(1)
471 # connect external reset signal to DMI Reset
472 if self
.dbg_domain
!= "sync":
473 dbg_rst
= ResetSignal(self
.dbg_domain
)
474 comb
+= dbg_rst
.eq(self
.dbg_rst_i
)
476 # busy/halted signals from core
477 core_busy_o
= ~core
.p
.o_ready | core
.n
.o_data
.busy_o
# core is busy
478 comb
+= self
.busy_o
.eq(core_busy_o
)
479 comb
+= pdecode2
.dec
.bigendian
.eq(self
.core_bigendian_i
)
481 # temporary hack: says "go" immediately for both address gen and ST
482 # XXX: st.go_i is set to 1 cycle delay to reduce combinatorial chains
484 ldst
= core
.fus
.fus
['ldst0']
485 st_go_edge
= rising_edge(m
, ldst
.st
.rel_o
)
486 # link addr-go direct to rel
487 m
.d
.comb
+= ldst
.ad
.go_i
.eq(ldst
.ad
.rel_o
)
488 m
.d
.sync
+= ldst
.st
.go_i
.eq(st_go_edge
) # link store-go to rising rel
490 def do_dmi(self
, m
, dbg
):
491 """deals with DMI debug requests
493 currently only provides read requests for the INT regfile, CR and XER
494 it will later also deal with *writing* to these regfiles.
498 dmi
, d_reg
, d_cr
, d_xer
, = dbg
.dmi
, dbg
.d_gpr
, dbg
.d_cr
, dbg
.d_xer
500 intrf
= self
.core
.regs
.rf
['int']
501 fastrf
= self
.core
.regs
.rf
['fast']
503 with m
.If(d_reg
.req
): # request for regfile access being made
504 # TODO: error-check this
505 # XXX should this be combinatorial? sync better?
507 comb
+= self
.int_r
.ren
.eq(1 << d_reg
.addr
)
509 comb
+= self
.int_r
.addr
.eq(d_reg
.addr
)
510 comb
+= self
.int_r
.ren
.eq(1)
511 d_reg_delay
= Signal()
512 sync
+= d_reg_delay
.eq(d_reg
.req
)
513 with m
.If(d_reg_delay
):
514 # data arrives one clock later
515 comb
+= d_reg
.data
.eq(self
.int_r
.o_data
)
516 comb
+= d_reg
.ack
.eq(1)
519 with m
.If(d_fast
.req
): # request for regfile access being made
521 comb
+= self
.fast_r
.ren
.eq(1 << d_fast
.addr
)
523 comb
+= self
.fast_r
.addr
.eq(d_fast
.addr
)
524 comb
+= self
.fast_r
.ren
.eq(1)
525 d_fast_delay
= Signal()
526 sync
+= d_fast_delay
.eq(d_fast
.req
)
527 with m
.If(d_fast_delay
):
528 # data arrives one clock later
529 comb
+= d_fast
.data
.eq(self
.fast_r
.o_data
)
530 comb
+= d_fast
.ack
.eq(1)
532 # sigh same thing for CR debug
533 with m
.If(d_cr
.req
): # request for regfile access being made
534 comb
+= self
.cr_r
.ren
.eq(0b11111111) # enable all
535 d_cr_delay
= Signal()
536 sync
+= d_cr_delay
.eq(d_cr
.req
)
537 with m
.If(d_cr_delay
):
538 # data arrives one clock later
539 comb
+= d_cr
.data
.eq(self
.cr_r
.o_data
)
540 comb
+= d_cr
.ack
.eq(1)
543 with m
.If(d_xer
.req
): # request for regfile access being made
544 comb
+= self
.xer_r
.ren
.eq(0b111111) # enable all
545 d_xer_delay
= Signal()
546 sync
+= d_xer_delay
.eq(d_xer
.req
)
547 with m
.If(d_xer_delay
):
548 # data arrives one clock later
549 comb
+= d_xer
.data
.eq(self
.xer_r
.o_data
)
550 comb
+= d_xer
.ack
.eq(1)
552 def tb_dec_fsm(self
, m
, spr_dec
):
555 this is a FSM for updating either dec or tb. it runs alternately
556 DEC, TB, DEC, TB. note that SPR pipeline could have written a new
557 value to DEC, however the regfile has "passthrough" on it so this
560 see v3.0B p1097-1099 for Timer Resource and p1065 and p1076
563 comb
, sync
= m
.d
.comb
, m
.d
.sync
564 state_rf
= self
.core
.regs
.rf
['state']
565 state_r_dectb
= state_rf
.r_ports
['issue'] # DEC/TB
566 state_w_dectb
= state_rf
.w_ports
['issue'] # DEC/TB
570 # initiates read of current DEC
571 with m
.State("DEC_READ"):
572 comb
+= state_r_dectb
.ren
.eq(1<<StateRegs
.DEC
)
573 with m
.If(~self
.pause_dec_tb
):
576 # waits for DEC read to arrive (1 cycle), updates with new value
577 # respects if dec/tb writing has been paused
578 with m
.State("DEC_WRITE"):
579 with m
.If(self
.pause_dec_tb
):
580 # if paused, return to reading
584 # TODO: MSR.LPCR 32-bit decrement mode
585 comb
+= new_dec
.eq(state_r_dectb
.o_data
- 1)
586 comb
+= state_w_dectb
.wen
.eq(1<<StateRegs
.DEC
)
587 comb
+= state_w_dectb
.i_data
.eq(new_dec
)
588 # copy to cur_state for decoder, for an interrupt
589 sync
+= spr_dec
.eq(new_dec
)
592 # initiates read of current TB
593 with m
.State("TB_READ"):
594 comb
+= state_r_dectb
.ren
.eq(1<<StateRegs
.TB
)
595 with m
.If(~self
.pause_dec_tb
):
598 # waits for read TB to arrive, initiates write of current TB
599 # respects if dec/tb writing has been paused
600 with m
.State("TB_WRITE"):
601 with m
.If(self
.pause_dec_tb
):
602 # if paused, return to reading
606 comb
+= new_tb
.eq(state_r_dectb
.o_data
+ 1)
607 comb
+= state_w_dectb
.wen
.eq(1<<StateRegs
.TB
)
608 comb
+= state_w_dectb
.i_data
.eq(new_tb
)
613 def elaborate(self
, platform
):
616 comb
, sync
= m
.d
.comb
, m
.d
.sync
617 cur_state
= self
.cur_state
618 pdecode2
= self
.pdecode2
621 # set up peripherals and core
622 core_rst
= self
.core_rst
623 self
.setup_peripherals(m
)
625 # reset current state if core reset requested
627 m
.d
.sync
+= self
.cur_state
.eq(0)
628 # and, sigh, set configured values, which are also done in regfile
629 # XXX ??? what the hell is the shift for??
630 m
.d
.sync
+= self
.cur_state
.pc
.eq(self
.core
.pc_at_reset
)
631 m
.d
.sync
+= self
.cur_state
.msr
.eq(self
.core
.msr_at_reset
)
633 # check halted condition: requested PC to execute matches DMI stop addr
634 # and immediately stop. address of 0xffff_ffff_ffff_ffff can never
637 comb
+= halted
.eq(dbg
.stop_addr_o
== dbg
.state
.pc
)
639 comb
+= dbg
.core_stopped_i
.eq(1)
640 comb
+= dbg
.terminate_i
.eq(1)
642 # PC and instruction from I-Memory
643 comb
+= self
.pc_o
.eq(cur_state
.pc
)
644 self
.pc_changed
= Signal() # note write to PC
645 self
.msr_changed
= Signal() # note write to MSR
646 self
.sv_changed
= Signal() # note write to SVSTATE
648 # read state either from incoming override or from regfile
649 state
= CoreState("get") # current state (MSR/PC/SVSTATE)
650 state_get(m
, state
.msr
, core_rst
, self
.msr_i
,
652 self
.state_r_msr
, StateRegs
.MSR
)
653 state_get(m
, state
.pc
, core_rst
, self
.pc_i
,
655 self
.state_r_pc
, StateRegs
.PC
)
656 state_get(m
, state
.svstate
, core_rst
, self
.svstate_i
,
657 "svstate", # read SVSTATE
658 self
.state_r_sv
, StateRegs
.SVSTATE
)
660 # don't write pc every cycle
661 comb
+= self
.state_w_pc
.wen
.eq(0)
662 comb
+= self
.state_w_pc
.i_data
.eq(0)
664 # connect up debug state. note "combinatorially same" below,
665 # this is a bit naff, passing state over in the dbg class, but
666 # because it is combinatorial it achieves the desired goal
667 comb
+= dbg
.state
.eq(state
)
669 # this bit doesn't have to be in the FSM: connect up to read
670 # regfiles on demand from DMI
673 # DEC and TB inc/dec FSM. copy of DEC is put into CoreState,
674 # (which uses that in PowerDecoder2 to raise 0x900 exception)
675 self
.tb_dec_fsm(m
, cur_state
.dec
)
677 # while stopped, allow updating the MSR, PC and SVSTATE.
678 # these are mainly for debugging purposes (including DMI/JTAG)
679 with m
.If(dbg
.core_stopped_i
):
680 with m
.If(self
.pc_i
.ok
):
681 comb
+= self
.state_w_pc
.wen
.eq(1 << StateRegs
.PC
)
682 comb
+= self
.state_w_pc
.i_data
.eq(self
.pc_i
.data
)
683 sync
+= self
.pc_changed
.eq(1)
684 with m
.If(self
.msr_i
.ok
):
685 comb
+= self
.state_w_msr
.wen
.eq(1 << StateRegs
.MSR
)
686 comb
+= self
.state_w_msr
.i_data
.eq(self
.msr_i
.data
)
687 sync
+= self
.msr_changed
.eq(1)
688 with m
.If(self
.svstate_i
.ok | self
.update_svstate
):
689 with m
.If(self
.svstate_i
.ok
): # over-ride from external source
690 comb
+= self
.new_svstate
.eq(self
.svstate_i
.data
)
691 comb
+= self
.state_w_sv
.wen
.eq(1 << StateRegs
.SVSTATE
)
692 comb
+= self
.state_w_sv
.i_data
.eq(self
.new_svstate
)
693 sync
+= self
.sv_changed
.eq(1)
695 # start renaming some of the ports to match microwatt
696 if self
.microwatt_compat
:
697 self
.core
.o
.core_terminate_o
.name
= "terminated_out"
698 # names of DMI interface
699 self
.dbg
.dmi
.addr_i
.name
= 'dmi_addr'
700 self
.dbg
.dmi
.din
.name
= 'dmi_din'
701 self
.dbg
.dmi
.dout
.name
= 'dmi_dout'
702 self
.dbg
.dmi
.req_i
.name
= 'dmi_req'
703 self
.dbg
.dmi
.we_i
.name
= 'dmi_wr'
704 self
.dbg
.dmi
.ack_o
.name
= 'dmi_ack'
705 # wishbone instruction bus
706 ibus
= self
.imem
.ibus
707 ibus
.adr
.name
= 'wishbone_insn_out.adr'
708 ibus
.dat_w
.name
= 'wishbone_insn_out.dat'
709 ibus
.sel
.name
= 'wishbone_insn_out.sel'
710 ibus
.cyc
.name
= 'wishbone_insn_out.cyc'
711 ibus
.stb
.name
= 'wishbone_insn_out.stb'
712 ibus
.we
.name
= 'wishbone_insn_out.we'
713 ibus
.dat_r
.name
= 'wishbone_insn_in.dat'
714 ibus
.ack
.name
= 'wishbone_insn_in.ack'
715 ibus
.stall
.name
= 'wishbone_insn_in.stall'
717 dbus
= self
.core
.l0
.cmpi
.wb_bus()
718 dbus
.adr
.name
= 'wishbone_data_out.adr'
719 dbus
.dat_w
.name
= 'wishbone_data_out.dat'
720 dbus
.sel
.name
= 'wishbone_data_out.sel'
721 dbus
.cyc
.name
= 'wishbone_data_out.cyc'
722 dbus
.stb
.name
= 'wishbone_data_out.stb'
723 dbus
.we
.name
= 'wishbone_data_out.we'
724 dbus
.dat_r
.name
= 'wishbone_data_in.dat'
725 dbus
.ack
.name
= 'wishbone_data_in.ack'
726 dbus
.stall
.name
= 'wishbone_data_in.stall'
731 yield from self
.pc_i
.ports()
732 yield from self
.msr_i
.ports()
735 yield from self
.core
.ports()
736 yield from self
.imem
.ports()
737 yield self
.core_bigendian_i
743 def external_ports(self
):
744 if self
.microwatt_compat
:
745 ports
= [self
.core
.o
.core_terminate_o
,
747 self
.alt_reset
, # not connected yet
748 self
.nia
, self
.insn
, self
.nia_req
, self
.msr_o
,
749 self
.ldst_req
, self
.ldst_addr
,
753 ports
+= list(self
.dbg
.dmi
.ports())
754 # for dbus/ibus microwatt, exclude err btw and cti
755 for name
, sig
in self
.imem
.ibus
.fields
.items():
756 if name
not in ['err', 'bte', 'cti', 'adr']:
758 for name
, sig
in self
.core
.l0
.cmpi
.wb_bus().fields
.items():
759 if name
not in ['err', 'bte', 'cti', 'adr']:
761 # microwatt non-compliant with wishbone
762 ports
.append(self
.ibus_adr
)
763 ports
.append(self
.dbus_adr
)
766 ports
= self
.pc_i
.ports()
767 ports
= self
.msr_i
.ports()
768 ports
+= [self
.pc_o
, self
.memerr_o
, self
.core_bigendian_i
, self
.busy_o
,
772 ports
+= list(self
.jtag
.external_ports())
774 # don't add DMI if JTAG is enabled
775 ports
+= list(self
.dbg
.dmi
.ports())
777 ports
+= list(self
.imem
.ibus
.fields
.values())
778 ports
+= list(self
.core
.l0
.cmpi
.wb_bus().fields
.values())
781 for sram
in self
.sram4k
:
782 ports
+= list(sram
.bus
.fields
.values())
785 ports
+= list(self
.xics_icp
.bus
.fields
.values())
786 ports
+= list(self
.xics_ics
.bus
.fields
.values())
787 ports
.append(self
.int_level_i
)
789 ports
.append(self
.ext_irq
)
792 ports
+= list(self
.simple_gpio
.bus
.fields
.values())
793 ports
.append(self
.gpio_o
)
801 class TestIssuerInternal(TestIssuerBase
):
802 """TestIssuer - reads instructions from TestMemory and issues them
804 efficiency and speed is not the main goal here: functional correctness
805 and code clarity is. optimisations (which almost 100% interfere with
806 easy understanding) come later.
809 def fetch_fsm(self
, m
, dbg
, core
, core_rst
, nia
, is_svp64_mode
,
810 fetch_pc_o_ready
, fetch_pc_i_valid
,
811 fetch_insn_o_valid
, fetch_insn_i_ready
):
814 this FSM performs fetch of raw instruction data, partial-decodes
815 it 32-bit at a time to detect SVP64 prefixes, and will optionally
816 read a 2nd 32-bit quantity if that occurs.
820 pdecode2
= self
.pdecode2
821 cur_state
= self
.cur_state
822 dec_opcode_i
= pdecode2
.dec
.raw_opcode_in
# raw opcode
823 pc
, msr
, svstate
= cur_state
.pc
, cur_state
.msr
, cur_state
.svstate
825 # also note instruction fetch failed
826 if hasattr(core
, "icache"):
827 fetch_failed
= core
.icache
.i_out
.fetch_failed
830 fetch_failed
= Const(0, 1)
833 # set priv / virt mode on I-Cache, sigh
834 if isinstance(self
.imem
, ICache
):
835 comb
+= self
.imem
.i_in
.priv_mode
.eq(~msr
[MSR
.PR
])
836 comb
+= self
.imem
.i_in
.virt_mode
.eq(msr
[MSR
.IR
]) # Instr. Redir (VM)
838 with m
.FSM(name
='fetch_fsm'):
840 # allow fetch to not run at startup due to I-Cache reset not
841 # having time to settle. power-on-reset holds dbg.core_stopped_i
842 with m
.State("PRE_IDLE"):
843 with m
.If(~dbg
.core_stopped_i
& ~dbg
.core_stop_o
& ~core_rst
):
847 with m
.State("IDLE"):
848 # fetch allowed if not failed and stopped but not stepping
849 # (see dmi.py for how core_stop_o is generated)
850 with m
.If(~fetch_failed
& ~dbg
.core_stop_o
):
851 comb
+= fetch_pc_o_ready
.eq(1)
852 with m
.If(fetch_pc_i_valid
& ~pdecode2
.instr_fault
854 # instruction allowed to go: start by reading the PC
855 # capture the PC and also drop it into Insn Memory
856 # we have joined a pair of combinatorial memory
857 # lookups together. this is Generally Bad.
858 comb
+= self
.imem
.a_pc_i
.eq(pc
)
859 comb
+= self
.imem
.a_i_valid
.eq(1)
860 comb
+= self
.imem
.f_i_valid
.eq(1)
861 m
.next
= "INSN_READ" # move to "wait for bus" phase
863 # dummy pause to find out why simulation is not keeping up
864 with m
.State("INSN_READ"):
865 # when using "single-step" mode, checking dbg.stopping_o
866 # prevents progress. allow fetch to proceed once started
868 #if self.allow_overlap:
869 # stopping = dbg.stopping_o
871 # stopping: jump back to idle
874 with m
.If(self
.imem
.f_busy_o
&
875 ~pdecode2
.instr_fault
): # zzz...
876 # busy but not fetch failed: stay in wait-read
877 comb
+= self
.imem
.a_pc_i
.eq(pc
)
878 comb
+= self
.imem
.a_i_valid
.eq(1)
879 comb
+= self
.imem
.f_i_valid
.eq(1)
881 # not busy (or fetch failed!): instruction fetched
882 # when fetch failed, the instruction gets ignored
884 if hasattr(core
, "icache"):
885 # blech, icache returns actual instruction
886 insn
= self
.imem
.f_instr_o
888 # but these return raw memory
889 insn
= get_insn(self
.imem
.f_instr_o
, cur_state
.pc
)
892 # decode the SVP64 prefix, if any
893 comb
+= svp64
.raw_opcode_in
.eq(insn
)
894 comb
+= svp64
.bigendian
.eq(self
.core_bigendian_i
)
895 # pass the decoded prefix (if any) to PowerDecoder2
896 sync
+= pdecode2
.sv_rm
.eq(svp64
.svp64_rm
)
897 sync
+= pdecode2
.is_svp64_mode
.eq(is_svp64_mode
)
898 # remember whether this is a prefixed instruction,
899 # so the FSM can readily loop when VL==0
900 sync
+= is_svp64_mode
.eq(svp64
.is_svp64_mode
)
901 # calculate the address of the following instruction
902 insn_size
= Mux(svp64
.is_svp64_mode
, 8, 4)
903 sync
+= nia
.eq(cur_state
.pc
+ insn_size
)
904 with m
.If(~svp64
.is_svp64_mode
):
905 # with no prefix, store the instruction
906 # and hand it directly to the next FSM
907 sync
+= dec_opcode_i
.eq(insn
)
908 m
.next
= "INSN_READY"
910 # fetch the rest of the instruction from memory
911 comb
+= self
.imem
.a_pc_i
.eq(cur_state
.pc
+ 4)
912 comb
+= self
.imem
.a_i_valid
.eq(1)
913 comb
+= self
.imem
.f_i_valid
.eq(1)
914 m
.next
= "INSN_READ2"
916 # not SVP64 - 32-bit only
917 sync
+= nia
.eq(cur_state
.pc
+ 4)
918 sync
+= dec_opcode_i
.eq(insn
)
919 if self
.microwatt_compat
:
920 # for verilator debug purposes
921 comb
+= self
.insn
.eq(insn
)
922 comb
+= self
.nia
.eq(cur_state
.pc
)
923 comb
+= self
.msr_o
.eq(cur_state
.msr
)
924 comb
+= self
.nia_req
.eq(1)
925 m
.next
= "INSN_READY"
927 with m
.State("INSN_READ2"):
928 with m
.If(self
.imem
.f_busy_o
): # zzz...
929 # busy: stay in wait-read
930 comb
+= self
.imem
.a_i_valid
.eq(1)
931 comb
+= self
.imem
.f_i_valid
.eq(1)
933 # not busy: instruction fetched
934 if hasattr(core
, "icache"):
935 # blech, icache returns actual instruction
936 insn
= self
.imem
.f_instr_o
938 insn
= get_insn(self
.imem
.f_instr_o
, cur_state
.pc
+4)
939 sync
+= dec_opcode_i
.eq(insn
)
940 m
.next
= "INSN_READY"
941 # TODO: probably can start looking at pdecode2.rm_dec
942 # here or maybe even in INSN_READ state, if svp64_mode
943 # detected, in order to trigger - and wait for - the
946 pmode
= pdecode2
.rm_dec
.predmode
948 if pmode != SVP64PredMode.ALWAYS.value:
949 fire predicate loading FSM and wait before
952 sync += self.srcmask.eq(-1) # set to all 1s
953 sync += self.dstmask.eq(-1) # set to all 1s
954 m.next = "INSN_READY"
957 with m
.State("INSN_READY"):
958 # hand over the instruction, to be decoded
959 comb
+= fetch_insn_o_valid
.eq(1)
960 with m
.If(fetch_insn_i_ready
):
964 def fetch_predicate_fsm(self
, m
,
965 pred_insn_i_valid
, pred_insn_o_ready
,
966 pred_mask_o_valid
, pred_mask_i_ready
):
967 """fetch_predicate_fsm - obtains (constructs in the case of CR)
968 src/dest predicate masks
970 https://bugs.libre-soc.org/show_bug.cgi?id=617
971 the predicates can be read here, by using IntRegs r_ports['pred']
972 or CRRegs r_ports['pred']. in the case of CRs it will have to
973 be done through multiple reads, extracting one relevant at a time.
974 later, a faster way would be to use the 32-bit-wide CR port but
975 this is more complex decoding, here. equivalent code used in
976 ISACaller is "from openpower.decoder.isa.caller import get_predcr"
978 note: this ENTIRE FSM is not to be called when svp64 is disabled
982 pdecode2
= self
.pdecode2
983 rm_dec
= pdecode2
.rm_dec
# SVP64RMModeDecode
984 predmode
= rm_dec
.predmode
985 srcpred
, dstpred
= rm_dec
.srcpred
, rm_dec
.dstpred
986 cr_pred
, int_pred
= self
.cr_pred
, self
.int_pred
# read regfiles
987 # get src/dst step, so we can skip already used mask bits
988 cur_state
= self
.cur_state
989 srcstep
= cur_state
.svstate
.srcstep
990 dststep
= cur_state
.svstate
.dststep
991 cur_vl
= cur_state
.svstate
.vl
994 sregread
, sinvert
, sunary
, sall1s
= get_predint(m
, srcpred
, 's')
995 dregread
, dinvert
, dunary
, dall1s
= get_predint(m
, dstpred
, 'd')
996 sidx
, scrinvert
= get_predcr(m
, srcpred
, 's')
997 didx
, dcrinvert
= get_predcr(m
, dstpred
, 'd')
999 # store fetched masks, for either intpred or crpred
1000 # when src/dst step is not zero, the skipped mask bits need to be
1001 # shifted-out, before actually storing them in src/dest mask
1002 new_srcmask
= Signal(64, reset_less
=True)
1003 new_dstmask
= Signal(64, reset_less
=True)
1005 with m
.FSM(name
="fetch_predicate"):
1007 with m
.State("FETCH_PRED_IDLE"):
1008 comb
+= pred_insn_o_ready
.eq(1)
1009 with m
.If(pred_insn_i_valid
):
1010 with m
.If(predmode
== SVP64PredMode
.INT
):
1011 # skip fetching destination mask register, when zero
1013 sync
+= new_dstmask
.eq(-1)
1014 # directly go to fetch source mask register
1015 # guaranteed not to be zero (otherwise predmode
1016 # would be SVP64PredMode.ALWAYS, not INT)
1017 comb
+= int_pred
.addr
.eq(sregread
)
1018 comb
+= int_pred
.ren
.eq(1)
1019 m
.next
= "INT_SRC_READ"
1020 # fetch destination predicate register
1022 comb
+= int_pred
.addr
.eq(dregread
)
1023 comb
+= int_pred
.ren
.eq(1)
1024 m
.next
= "INT_DST_READ"
1025 with m
.Elif(predmode
== SVP64PredMode
.CR
):
1026 # go fetch masks from the CR register file
1027 sync
+= new_srcmask
.eq(0)
1028 sync
+= new_dstmask
.eq(0)
1031 sync
+= self
.srcmask
.eq(-1)
1032 sync
+= self
.dstmask
.eq(-1)
1033 m
.next
= "FETCH_PRED_DONE"
1035 with m
.State("INT_DST_READ"):
1036 # store destination mask
1037 inv
= Repl(dinvert
, 64)
1039 # set selected mask bit for 1<<r3 mode
1040 dst_shift
= Signal(range(64))
1041 comb
+= dst_shift
.eq(self
.int_pred
.o_data
& 0b111111)
1042 sync
+= new_dstmask
.eq(1 << dst_shift
)
1044 # invert mask if requested
1045 sync
+= new_dstmask
.eq(self
.int_pred
.o_data ^ inv
)
1046 # skip fetching source mask register, when zero
1048 sync
+= new_srcmask
.eq(-1)
1049 m
.next
= "FETCH_PRED_SHIFT_MASK"
1050 # fetch source predicate register
1052 comb
+= int_pred
.addr
.eq(sregread
)
1053 comb
+= int_pred
.ren
.eq(1)
1054 m
.next
= "INT_SRC_READ"
1056 with m
.State("INT_SRC_READ"):
1058 inv
= Repl(sinvert
, 64)
1060 # set selected mask bit for 1<<r3 mode
1061 src_shift
= Signal(range(64))
1062 comb
+= src_shift
.eq(self
.int_pred
.o_data
& 0b111111)
1063 sync
+= new_srcmask
.eq(1 << src_shift
)
1065 # invert mask if requested
1066 sync
+= new_srcmask
.eq(self
.int_pred
.o_data ^ inv
)
1067 m
.next
= "FETCH_PRED_SHIFT_MASK"
1069 # fetch masks from the CR register file
1070 # implements the following loop:
1071 # idx, inv = get_predcr(mask)
1073 # for cr_idx in range(vl):
1074 # cr = crl[cr_idx + SVP64CROffs.CRPred] # takes one cycle
1076 # mask |= 1 << cr_idx
1078 with m
.State("CR_READ"):
1079 # CR index to be read, which will be ready by the next cycle
1080 cr_idx
= Signal
.like(cur_vl
, reset_less
=True)
1081 # submit the read operation to the regfile
1082 with m
.If(cr_idx
!= cur_vl
):
1083 # the CR read port is unary ...
1085 # ... in MSB0 convention ...
1086 # ren = 1 << (7 - cr_idx)
1087 # ... and with an offset:
1088 # ren = 1 << (7 - off - cr_idx)
1089 idx
= SVP64CROffs
.CRPred
+ cr_idx
1090 comb
+= cr_pred
.ren
.eq(1 << (7 - idx
))
1091 # signal data valid in the next cycle
1092 cr_read
= Signal(reset_less
=True)
1093 sync
+= cr_read
.eq(1)
1094 # load the next index
1095 sync
+= cr_idx
.eq(cr_idx
+ 1)
1098 sync
+= cr_read
.eq(0)
1099 sync
+= cr_idx
.eq(0)
1100 m
.next
= "FETCH_PRED_SHIFT_MASK"
1102 # compensate for the one cycle delay on the regfile
1103 cur_cr_idx
= Signal
.like(cur_vl
)
1104 comb
+= cur_cr_idx
.eq(cr_idx
- 1)
1105 # read the CR field, select the appropriate bit
1106 cr_field
= Signal(4)
1109 comb
+= cr_field
.eq(cr_pred
.o_data
)
1110 comb
+= scr_bit
.eq(cr_field
.bit_select(sidx
, 1)
1112 comb
+= dcr_bit
.eq(cr_field
.bit_select(didx
, 1)
1114 # set the corresponding mask bit
1115 bit_to_set
= Signal
.like(self
.srcmask
)
1116 comb
+= bit_to_set
.eq(1 << cur_cr_idx
)
1118 sync
+= new_srcmask
.eq(new_srcmask | bit_to_set
)
1120 sync
+= new_dstmask
.eq(new_dstmask | bit_to_set
)
1122 with m
.State("FETCH_PRED_SHIFT_MASK"):
1123 # shift-out skipped mask bits
1124 sync
+= self
.srcmask
.eq(new_srcmask
>> srcstep
)
1125 sync
+= self
.dstmask
.eq(new_dstmask
>> dststep
)
1126 m
.next
= "FETCH_PRED_DONE"
1128 with m
.State("FETCH_PRED_DONE"):
1129 comb
+= pred_mask_o_valid
.eq(1)
1130 with m
.If(pred_mask_i_ready
):
1131 m
.next
= "FETCH_PRED_IDLE"
1133 def issue_fsm(self
, m
, core
, nia
,
1134 dbg
, core_rst
, is_svp64_mode
,
1135 fetch_pc_o_ready
, fetch_pc_i_valid
,
1136 fetch_insn_o_valid
, fetch_insn_i_ready
,
1137 pred_insn_i_valid
, pred_insn_o_ready
,
1138 pred_mask_o_valid
, pred_mask_i_ready
,
1139 exec_insn_i_valid
, exec_insn_o_ready
,
1140 exec_pc_o_valid
, exec_pc_i_ready
):
1143 decode / issue FSM. this interacts with the "fetch" FSM
1144 through fetch_insn_ready/valid (incoming) and fetch_pc_ready/valid
1145 (outgoing). also interacts with the "execute" FSM
1146 through exec_insn_ready/valid (outgoing) and exec_pc_ready/valid
1148 SVP64 RM prefixes have already been set up by the
1149 "fetch" phase, so execute is fairly straightforward.
1154 pdecode2
= self
.pdecode2
1155 cur_state
= self
.cur_state
1156 new_svstate
= self
.new_svstate
1159 dec_opcode_i
= pdecode2
.dec
.raw_opcode_in
# raw opcode
1161 # for updating svstate (things like srcstep etc.)
1162 comb
+= new_svstate
.eq(cur_state
.svstate
)
1164 # precalculate srcstep+1 and dststep+1
1165 cur_srcstep
= cur_state
.svstate
.srcstep
1166 cur_dststep
= cur_state
.svstate
.dststep
1167 next_srcstep
= Signal
.like(cur_srcstep
)
1168 next_dststep
= Signal
.like(cur_dststep
)
1169 comb
+= next_srcstep
.eq(cur_state
.svstate
.srcstep
+1)
1170 comb
+= next_dststep
.eq(cur_state
.svstate
.dststep
+1)
1172 # note if an exception happened. in a pipelined or OoO design
1173 # this needs to be accompanied by "shadowing" (or stalling)
1174 exc_happened
= self
.core
.o
.exc_happened
1175 # also note instruction fetch failed
1176 if hasattr(core
, "icache"):
1177 fetch_failed
= core
.icache
.i_out
.fetch_failed
1179 # set to fault in decoder
1180 # update (highest priority) instruction fault
1181 rising_fetch_failed
= rising_edge(m
, fetch_failed
)
1182 with m
.If(rising_fetch_failed
):
1183 sync
+= pdecode2
.instr_fault
.eq(1)
1185 fetch_failed
= Const(0, 1)
1186 flush_needed
= False
1188 sync
+= fetch_pc_i_valid
.eq(0)
1190 with m
.FSM(name
="issue_fsm"):
1192 with m
.State("PRE_IDLE"):
1193 with m
.If(~dbg
.core_stop_o
& ~core_rst
):
1194 m
.next
= "ISSUE_START"
1196 # sync with the "fetch" phase which is reading the instruction
1197 # at this point, there is no instruction running, that
1198 # could inadvertently update the PC.
1199 with m
.State("ISSUE_START"):
1200 # reset instruction fault
1201 sync
+= pdecode2
.instr_fault
.eq(0)
1202 # wait on "core stop" release, before next fetch
1203 # need to do this here, in case we are in a VL==0 loop
1204 with m
.If(~dbg
.core_stop_o
& ~core_rst
):
1205 sync
+= fetch_pc_i_valid
.eq(1) # tell fetch to start
1206 sync
+= cur_state
.pc
.eq(dbg
.state
.pc
)
1207 sync
+= cur_state
.svstate
.eq(dbg
.state
.svstate
)
1208 sync
+= cur_state
.msr
.eq(dbg
.state
.msr
)
1209 with m
.If(fetch_pc_o_ready
): # fetch acknowledged us
1210 m
.next
= "INSN_WAIT"
1212 # tell core it's stopped, and acknowledge debug handshake
1213 comb
+= dbg
.core_stopped_i
.eq(1)
1214 # while stopped, allow updating SVSTATE
1215 with m
.If(self
.svstate_i
.ok
):
1216 comb
+= new_svstate
.eq(self
.svstate_i
.data
)
1217 comb
+= self
.update_svstate
.eq(1)
1218 sync
+= self
.sv_changed
.eq(1)
1220 # wait for an instruction to arrive from Fetch
1221 with m
.State("INSN_WAIT"):
1222 # when using "single-step" mode, checking dbg.stopping_o
1223 # prevents progress. allow issue to proceed once started
1225 #if self.allow_overlap:
1226 # stopping = dbg.stopping_o
1227 with m
.If(stopping
):
1228 # stopping: jump back to idle
1229 m
.next
= "ISSUE_START"
1231 # request the icache to stop asserting "failed"
1232 comb
+= core
.icache
.flush_in
.eq(1)
1233 # stop instruction fault
1234 sync
+= pdecode2
.instr_fault
.eq(0)
1236 comb
+= fetch_insn_i_ready
.eq(1)
1237 with m
.If(fetch_insn_o_valid
):
1238 # loop into ISSUE_START if it's a SVP64 instruction
1239 # and VL == 0. this because VL==0 is a for-loop
1240 # from 0 to 0 i.e. always, always a NOP.
1241 cur_vl
= cur_state
.svstate
.vl
1242 with m
.If(is_svp64_mode
& (cur_vl
== 0)):
1243 # update the PC before fetching the next instruction
1244 # since we are in a VL==0 loop, no instruction was
1245 # executed that we could be overwriting
1246 comb
+= self
.state_w_pc
.wen
.eq(1 << StateRegs
.PC
)
1247 comb
+= self
.state_w_pc
.i_data
.eq(nia
)
1248 comb
+= self
.insn_done
.eq(1)
1249 m
.next
= "ISSUE_START"
1252 m
.next
= "PRED_START" # fetching predicate
1254 m
.next
= "DECODE_SV" # skip predication
1256 with m
.State("PRED_START"):
1257 comb
+= pred_insn_i_valid
.eq(1) # tell fetch_pred to start
1258 with m
.If(pred_insn_o_ready
): # fetch_pred acknowledged us
1259 m
.next
= "MASK_WAIT"
1261 with m
.State("MASK_WAIT"):
1262 comb
+= pred_mask_i_ready
.eq(1) # ready to receive the masks
1263 with m
.If(pred_mask_o_valid
): # predication masks are ready
1264 m
.next
= "PRED_SKIP"
1266 # skip zeros in predicate
1267 with m
.State("PRED_SKIP"):
1268 with m
.If(~is_svp64_mode
):
1269 m
.next
= "DECODE_SV" # nothing to do
1272 pred_src_zero
= pdecode2
.rm_dec
.pred_sz
1273 pred_dst_zero
= pdecode2
.rm_dec
.pred_dz
1275 # new srcstep, after skipping zeros
1276 skip_srcstep
= Signal
.like(cur_srcstep
)
1277 # value to be added to the current srcstep
1278 src_delta
= Signal
.like(cur_srcstep
)
1279 # add leading zeros to srcstep, if not in zero mode
1280 with m
.If(~pred_src_zero
):
1281 # priority encoder (count leading zeros)
1282 # append guard bit, in case the mask is all zeros
1283 pri_enc_src
= PriorityEncoder(65)
1284 m
.submodules
.pri_enc_src
= pri_enc_src
1285 comb
+= pri_enc_src
.i
.eq(Cat(self
.srcmask
,
1287 comb
+= src_delta
.eq(pri_enc_src
.o
)
1288 # apply delta to srcstep
1289 comb
+= skip_srcstep
.eq(cur_srcstep
+ src_delta
)
1290 # shift-out all leading zeros from the mask
1291 # plus the leading "one" bit
1292 # TODO count leading zeros and shift-out the zero
1293 # bits, in the same step, in hardware
1294 sync
+= self
.srcmask
.eq(self
.srcmask
>> (src_delta
+1))
1296 # same as above, but for dststep
1297 skip_dststep
= Signal
.like(cur_dststep
)
1298 dst_delta
= Signal
.like(cur_dststep
)
1299 with m
.If(~pred_dst_zero
):
1300 pri_enc_dst
= PriorityEncoder(65)
1301 m
.submodules
.pri_enc_dst
= pri_enc_dst
1302 comb
+= pri_enc_dst
.i
.eq(Cat(self
.dstmask
,
1304 comb
+= dst_delta
.eq(pri_enc_dst
.o
)
1305 comb
+= skip_dststep
.eq(cur_dststep
+ dst_delta
)
1306 sync
+= self
.dstmask
.eq(self
.dstmask
>> (dst_delta
+1))
1308 # TODO: initialize mask[VL]=1 to avoid passing past VL
1309 with m
.If((skip_srcstep
>= cur_vl
) |
1310 (skip_dststep
>= cur_vl
)):
1311 # end of VL loop. Update PC and reset src/dst step
1312 comb
+= self
.state_w_pc
.wen
.eq(1 << StateRegs
.PC
)
1313 comb
+= self
.state_w_pc
.i_data
.eq(nia
)
1314 comb
+= new_svstate
.srcstep
.eq(0)
1315 comb
+= new_svstate
.dststep
.eq(0)
1316 comb
+= self
.update_svstate
.eq(1)
1317 # synchronize with the simulator
1318 comb
+= self
.insn_done
.eq(1)
1320 m
.next
= "ISSUE_START"
1322 # update new src/dst step
1323 comb
+= new_svstate
.srcstep
.eq(skip_srcstep
)
1324 comb
+= new_svstate
.dststep
.eq(skip_dststep
)
1325 comb
+= self
.update_svstate
.eq(1)
1327 m
.next
= "DECODE_SV"
1329 # pass predicate mask bits through to satellite decoders
1330 # TODO: for SIMD this will be *multiple* bits
1331 sync
+= core
.i
.sv_pred_sm
.eq(self
.srcmask
[0])
1332 sync
+= core
.i
.sv_pred_dm
.eq(self
.dstmask
[0])
1334 # after src/dst step have been updated, we are ready
1335 # to decode the instruction
1336 with m
.State("DECODE_SV"):
1337 # decode the instruction
1338 with m
.If(~fetch_failed
):
1339 sync
+= pdecode2
.instr_fault
.eq(0)
1340 sync
+= core
.i
.e
.eq(pdecode2
.e
)
1341 sync
+= core
.i
.state
.eq(cur_state
)
1342 sync
+= core
.i
.raw_insn_i
.eq(dec_opcode_i
)
1343 sync
+= core
.i
.bigendian_i
.eq(self
.core_bigendian_i
)
1345 sync
+= core
.i
.sv_rm
.eq(pdecode2
.sv_rm
)
1346 # set RA_OR_ZERO detection in satellite decoders
1347 sync
+= core
.i
.sv_a_nz
.eq(pdecode2
.sv_a_nz
)
1348 # and svp64 detection
1349 sync
+= core
.i
.is_svp64_mode
.eq(is_svp64_mode
)
1350 # and svp64 bit-rev'd ldst mode
1351 ldst_dec
= pdecode2
.use_svp64_ldst_dec
1352 sync
+= core
.i
.use_svp64_ldst_dec
.eq(ldst_dec
)
1353 # after decoding, reset any previous exception condition,
1354 # allowing it to be set again during the next execution
1355 sync
+= pdecode2
.ldst_exc
.eq(0)
1357 m
.next
= "INSN_EXECUTE" # move to "execute"
1359 # handshake with execution FSM, move to "wait" once acknowledged
1360 with m
.State("INSN_EXECUTE"):
1361 # when using "single-step" mode, checking dbg.stopping_o
1362 # prevents progress. allow execute to proceed once started
1364 #if self.allow_overlap:
1365 # stopping = dbg.stopping_o
1366 with m
.If(stopping
):
1367 # stopping: jump back to idle
1368 m
.next
= "ISSUE_START"
1370 # request the icache to stop asserting "failed"
1371 comb
+= core
.icache
.flush_in
.eq(1)
1372 # stop instruction fault
1373 sync
+= pdecode2
.instr_fault
.eq(0)
1375 comb
+= exec_insn_i_valid
.eq(1) # trigger execute
1376 with m
.If(exec_insn_o_ready
): # execute acknowledged us
1377 m
.next
= "EXECUTE_WAIT"
1379 with m
.State("EXECUTE_WAIT"):
1380 comb
+= exec_pc_i_ready
.eq(1)
1381 # see https://bugs.libre-soc.org/show_bug.cgi?id=636
1382 # the exception info needs to be blatted into
1383 # pdecode.ldst_exc, and the instruction "re-run".
1384 # when ldst_exc.happened is set, the PowerDecoder2
1385 # reacts very differently: it re-writes the instruction
1386 # with a "trap" (calls PowerDecoder2.trap()) which
1387 # will *overwrite* whatever was requested and jump the
1388 # PC to the exception address, as well as alter MSR.
1389 # nothing else needs to be done other than to note
1390 # the change of PC and MSR (and, later, SVSTATE)
1391 with m
.If(exc_happened
):
1392 mmu
= core
.fus
.get_exc("mmu0")
1393 ldst
= core
.fus
.get_exc("ldst0")
1395 with m
.If(fetch_failed
):
1396 # instruction fetch: exception is from MMU
1397 # reset instr_fault (highest priority)
1398 sync
+= pdecode2
.ldst_exc
.eq(mmu
)
1399 sync
+= pdecode2
.instr_fault
.eq(0)
1401 # request icache to stop asserting "failed"
1402 comb
+= core
.icache
.flush_in
.eq(1)
1403 with m
.If(~fetch_failed
):
1404 # otherwise assume it was a LDST exception
1405 sync
+= pdecode2
.ldst_exc
.eq(ldst
)
1407 with m
.If(exec_pc_o_valid
):
1409 # was this the last loop iteration?
1411 cur_vl
= cur_state
.svstate
.vl
1412 comb
+= is_last
.eq(next_srcstep
== cur_vl
)
1414 with m
.If(pdecode2
.instr_fault
):
1415 # reset instruction fault, try again
1416 sync
+= pdecode2
.instr_fault
.eq(0)
1417 m
.next
= "ISSUE_START"
1419 # return directly to Decode if Execute generated an
1421 with m
.Elif(pdecode2
.ldst_exc
.happened
):
1422 m
.next
= "DECODE_SV"
1424 # if MSR, PC or SVSTATE were changed by the previous
1425 # instruction, go directly back to Fetch, without
1426 # updating either MSR PC or SVSTATE
1427 with m
.Elif(self
.msr_changed | self
.pc_changed |
1429 m
.next
= "ISSUE_START"
1431 # also return to Fetch, when no output was a vector
1432 # (regardless of SRCSTEP and VL), or when the last
1433 # instruction was really the last one of the VL loop
1434 with m
.Elif((~pdecode2
.loop_continue
) | is_last
):
1435 # before going back to fetch, update the PC state
1436 # register with the NIA.
1437 # ok here we are not reading the branch unit.
1438 # TODO: this just blithely overwrites whatever
1439 # pipeline updated the PC
1440 comb
+= self
.state_w_pc
.wen
.eq(1 << StateRegs
.PC
)
1441 comb
+= self
.state_w_pc
.i_data
.eq(nia
)
1442 # reset SRCSTEP before returning to Fetch
1444 with m
.If(pdecode2
.loop_continue
):
1445 comb
+= new_svstate
.srcstep
.eq(0)
1446 comb
+= new_svstate
.dststep
.eq(0)
1447 comb
+= self
.update_svstate
.eq(1)
1449 comb
+= new_svstate
.srcstep
.eq(0)
1450 comb
+= new_svstate
.dststep
.eq(0)
1451 comb
+= self
.update_svstate
.eq(1)
1452 m
.next
= "ISSUE_START"
1454 # returning to Execute? then, first update SRCSTEP
1456 comb
+= new_svstate
.srcstep
.eq(next_srcstep
)
1457 comb
+= new_svstate
.dststep
.eq(next_dststep
)
1458 comb
+= self
.update_svstate
.eq(1)
1459 # return to mask skip loop
1460 m
.next
= "PRED_SKIP"
1463 # check if svstate needs updating: if so, write it to State Regfile
1464 with m
.If(self
.update_svstate
):
1465 sync
+= cur_state
.svstate
.eq(self
.new_svstate
) # for next clock
1467 def execute_fsm(self
, m
, core
,
1468 exec_insn_i_valid
, exec_insn_o_ready
,
1469 exec_pc_o_valid
, exec_pc_i_ready
):
1472 execute FSM. this interacts with the "issue" FSM
1473 through exec_insn_ready/valid (incoming) and exec_pc_ready/valid
1474 (outgoing). SVP64 RM prefixes have already been set up by the
1475 "issue" phase, so execute is fairly straightforward.
1481 pdecode2
= self
.pdecode2
1484 core_busy_o
= core
.n
.o_data
.busy_o
# core is busy
1485 core_ivalid_i
= core
.p
.i_valid
# instruction is valid
1487 if hasattr(core
, "icache"):
1488 fetch_failed
= core
.icache
.i_out
.fetch_failed
1490 fetch_failed
= Const(0, 1)
1492 with m
.FSM(name
="exec_fsm"):
1494 # waiting for instruction bus (stays there until not busy)
1495 with m
.State("INSN_START"):
1496 comb
+= exec_insn_o_ready
.eq(1)
1497 with m
.If(exec_insn_i_valid
):
1498 comb
+= core_ivalid_i
.eq(1) # instruction is valid/issued
1499 sync
+= self
.sv_changed
.eq(0)
1500 sync
+= self
.pc_changed
.eq(0)
1501 sync
+= self
.msr_changed
.eq(0)
1502 with m
.If(core
.p
.o_ready
): # only move if accepted
1503 m
.next
= "INSN_ACTIVE" # move to "wait completion"
1505 # instruction started: must wait till it finishes
1506 with m
.State("INSN_ACTIVE"):
1507 # note changes to MSR, PC and SVSTATE, and DEC/TB
1508 # these last two are done together, and passed to the
1510 with m
.If(self
.state_nia
.wen
& (1 << StateRegs
.SVSTATE
)):
1511 sync
+= self
.sv_changed
.eq(1)
1512 with m
.If(self
.state_nia
.wen
& (1 << StateRegs
.MSR
)):
1513 sync
+= self
.msr_changed
.eq(1)
1514 with m
.If(self
.state_nia
.wen
& (1 << StateRegs
.PC
)):
1515 sync
+= self
.pc_changed
.eq(1)
1516 with m
.If((self
.state_spr
.wen
&
1517 ((1 << StateRegs
.DEC
) |
(1 << StateRegs
.TB
))).bool()):
1518 comb
+= self
.pause_dec_tb
.eq(1)
1519 with m
.If(~core_busy_o
): # instruction done!
1520 comb
+= exec_pc_o_valid
.eq(1)
1521 with m
.If(exec_pc_i_ready
):
1522 # when finished, indicate "done".
1523 # however, if there was an exception, the instruction
1524 # is *not* yet done. this is an implementation
1525 # detail: we choose to implement exceptions by
1526 # taking the exception information from the LDST
1527 # unit, putting that *back* into the PowerDecoder2,
1528 # and *re-running the entire instruction*.
1529 # if we erroneously indicate "done" here, it is as if
1530 # there were *TWO* instructions:
1531 # 1) the failed LDST 2) a TRAP.
1532 with m
.If(~pdecode2
.ldst_exc
.happened
&
1533 ~pdecode2
.instr_fault
):
1534 comb
+= self
.insn_done
.eq(1)
1535 m
.next
= "INSN_START" # back to fetch
1536 # terminate returns directly to INSN_START
1537 with m
.If(dbg
.terminate_i
):
1538 # comb += self.insn_done.eq(1) - no because it's not
1539 m
.next
= "INSN_START" # back to fetch
1541 def elaborate(self
, platform
):
1542 m
= super().elaborate(platform
)
1544 comb
, sync
= m
.d
.comb
, m
.d
.sync
1545 cur_state
= self
.cur_state
1546 pdecode2
= self
.pdecode2
1550 # set up peripherals and core
1551 core_rst
= self
.core_rst
1553 # indicate to outside world if any FU is still executing
1554 comb
+= self
.any_busy
.eq(core
.n
.o_data
.any_busy_o
) # any FU executing
1556 # address of the next instruction, in the absence of a branch
1557 # depends on the instruction size
1560 # connect up debug signals
1561 with m
.If(core
.o
.core_terminate_o
):
1562 comb
+= dbg
.terminate_i
.eq(1)
1564 # pass the prefix mode from Fetch to Issue, so the latter can loop
1566 is_svp64_mode
= Signal()
1568 # there are *THREE^WFOUR-if-SVP64-enabled* FSMs, fetch (32/64-bit)
1569 # issue, decode/execute, now joined by "Predicate fetch/calculate".
1570 # these are the handshake signals between each
1572 # fetch FSM can run as soon as the PC is valid
1573 fetch_pc_i_valid
= Signal() # Execute tells Fetch "start next read"
1574 fetch_pc_o_ready
= Signal() # Fetch Tells SVSTATE "proceed"
1576 # fetch FSM hands over the instruction to be decoded / issued
1577 fetch_insn_o_valid
= Signal()
1578 fetch_insn_i_ready
= Signal()
1580 # predicate fetch FSM decodes and fetches the predicate
1581 pred_insn_i_valid
= Signal()
1582 pred_insn_o_ready
= Signal()
1584 # predicate fetch FSM delivers the masks
1585 pred_mask_o_valid
= Signal()
1586 pred_mask_i_ready
= Signal()
1588 # issue FSM delivers the instruction to the be executed
1589 exec_insn_i_valid
= Signal()
1590 exec_insn_o_ready
= Signal()
1592 # execute FSM, hands over the PC/SVSTATE back to the issue FSM
1593 exec_pc_o_valid
= Signal()
1594 exec_pc_i_ready
= Signal()
1596 # the FSMs here are perhaps unusual in that they detect conditions
1597 # then "hold" information, combinatorially, for the core
1598 # (as opposed to using sync - which would be on a clock's delay)
1599 # this includes the actual opcode, valid flags and so on.
1601 # Fetch, then predicate fetch, then Issue, then Execute.
1602 # Issue is where the VL for-loop # lives. the ready/valid
1603 # signalling is used to communicate between the four.
1605 self
.fetch_fsm(m
, dbg
, core
, core_rst
, nia
, is_svp64_mode
,
1606 fetch_pc_o_ready
, fetch_pc_i_valid
,
1607 fetch_insn_o_valid
, fetch_insn_i_ready
)
1609 self
.issue_fsm(m
, core
, nia
,
1610 dbg
, core_rst
, is_svp64_mode
,
1611 fetch_pc_o_ready
, fetch_pc_i_valid
,
1612 fetch_insn_o_valid
, fetch_insn_i_ready
,
1613 pred_insn_i_valid
, pred_insn_o_ready
,
1614 pred_mask_o_valid
, pred_mask_i_ready
,
1615 exec_insn_i_valid
, exec_insn_o_ready
,
1616 exec_pc_o_valid
, exec_pc_i_ready
)
1619 self
.fetch_predicate_fsm(m
,
1620 pred_insn_i_valid
, pred_insn_o_ready
,
1621 pred_mask_o_valid
, pred_mask_i_ready
)
1623 self
.execute_fsm(m
, core
,
1624 exec_insn_i_valid
, exec_insn_o_ready
,
1625 exec_pc_o_valid
, exec_pc_i_ready
)
1627 # whatever was done above, over-ride it if core reset is held.
1628 # set NIA to pc_at_reset
1629 with m
.If(core_rst
):
1630 sync
+= nia
.eq(self
.core
.pc_at_reset
)
1635 class TestIssuer(Elaboratable
):
1636 def __init__(self
, pspec
):
1637 self
.ti
= TestIssuerInternal(pspec
)
1638 self
.pll
= DummyPLL(instance
=True)
1640 self
.dbg_rst_i
= Signal(reset_less
=True)
1642 # PLL direct clock or not
1643 self
.pll_en
= hasattr(pspec
, "use_pll") and pspec
.use_pll
1645 self
.pll_test_o
= Signal(reset_less
=True)
1646 self
.pll_vco_o
= Signal(reset_less
=True)
1647 self
.clk_sel_i
= Signal(2, reset_less
=True)
1648 self
.ref_clk
= ClockSignal() # can't rename it but that's ok
1649 self
.pllclk_clk
= ClockSignal("pllclk")
1651 def elaborate(self
, platform
):
1655 # TestIssuer nominally runs at main clock, actually it is
1656 # all combinatorial internally except for coresync'd components
1657 m
.submodules
.ti
= ti
= self
.ti
1660 # ClockSelect runs at PLL output internal clock rate
1661 m
.submodules
.wrappll
= pll
= self
.pll
1663 # add clock domains from PLL
1664 cd_pll
= ClockDomain("pllclk")
1667 # PLL clock established. has the side-effect of running clklsel
1668 # at the PLL's speed (see DomainRenamer("pllclk") above)
1669 pllclk
= self
.pllclk_clk
1670 comb
+= pllclk
.eq(pll
.clk_pll_o
)
1672 # wire up external 24mhz to PLL
1673 #comb += pll.clk_24_i.eq(self.ref_clk)
1674 # output 18 mhz PLL test signal, and analog oscillator out
1675 comb
+= self
.pll_test_o
.eq(pll
.pll_test_o
)
1676 comb
+= self
.pll_vco_o
.eq(pll
.pll_vco_o
)
1678 # input to pll clock selection
1679 comb
+= pll
.clk_sel_i
.eq(self
.clk_sel_i
)
1681 # now wire up ResetSignals. don't mind them being in this domain
1682 pll_rst
= ResetSignal("pllclk")
1683 comb
+= pll_rst
.eq(ResetSignal())
1685 # internal clock is set to selector clock-out. has the side-effect of
1686 # running TestIssuer at this speed (see DomainRenamer("intclk") above)
1687 # debug clock runs at coresync internal clock
1688 if self
.ti
.dbg_domain
!= 'sync':
1689 cd_dbgsync
= ClockDomain("dbgsync")
1690 intclk
= ClockSignal(self
.ti
.core_domain
)
1691 dbgclk
= ClockSignal(self
.ti
.dbg_domain
)
1692 # XXX BYPASS PLL XXX
1693 # XXX BYPASS PLL XXX
1694 # XXX BYPASS PLL XXX
1696 comb
+= intclk
.eq(self
.ref_clk
)
1697 assert self
.ti
.core_domain
!= 'sync', \
1698 "cannot set core_domain to sync and use pll at the same time"
1700 if self
.ti
.core_domain
!= 'sync':
1701 comb
+= intclk
.eq(ClockSignal())
1702 if self
.ti
.dbg_domain
!= 'sync':
1703 dbgclk
= ClockSignal(self
.ti
.dbg_domain
)
1704 comb
+= dbgclk
.eq(intclk
)
1705 comb
+= self
.ti
.dbg_rst_i
.eq(self
.dbg_rst_i
)
1710 return list(self
.ti
.ports()) + list(self
.pll
.ports()) + \
1711 [ClockSignal(), ResetSignal()]
1713 def external_ports(self
):
1714 ports
= self
.ti
.external_ports()
1715 ports
.append(ClockSignal())
1716 ports
.append(ResetSignal())
1718 ports
.append(self
.clk_sel_i
)
1719 ports
.append(self
.pll
.clk_24_i
)
1720 ports
.append(self
.pll_test_o
)
1721 ports
.append(self
.pll_vco_o
)
1722 ports
.append(self
.pllclk_clk
)
1723 ports
.append(self
.ref_clk
)
1727 if __name__
== '__main__':
1728 units
= {'alu': 1, 'cr': 1, 'branch': 1, 'trap': 1, 'logical': 1,
1734 pspec
= TestMemPspec(ldst_ifacetype
='bare_wb',
1735 imem_ifacetype
='bare_wb',
1740 dut
= TestIssuer(pspec
)
1741 vl
= main(dut
, ports
=dut
.ports(), name
="test_issuer")
1743 if len(sys
.argv
) == 1:
1744 vl
= rtlil
.convert(dut
, ports
=dut
.external_ports(), name
="test_issuer")
1745 with
open("test_issuer.il", "w") as f
: