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CR sub-fields are stored in MSB0 order
[soc.git] / src / soc / simple / issuer.py
1 """simple core issuer
2
3 not in any way intended for production use. this runs a FSM that:
4
5 * reads the Program Counter from StateRegs
6 * reads an instruction from a fixed-size Test Memory
7 * issues it to the Simple Core
8 * waits for it to complete
9 * increments the PC
10 * does it all over again
11
12 the purpose of this module is to verify the functional correctness
13 of the Function Units in the absolute simplest and clearest possible
14 way, and to at provide something that can be further incrementally
15 improved.
16 """
17
18 from nmigen import (Elaboratable, Module, Signal, ClockSignal, ResetSignal,
19 ClockDomain, DomainRenamer, Mux, Const, Repl, Cat)
20 from nmigen.cli import rtlil
21 from nmigen.cli import main
22 import sys
23
24 from nmigen.lib.coding import PriorityEncoder
25
26 from soc.decoder.power_decoder import create_pdecode
27 from soc.decoder.power_decoder2 import PowerDecode2, SVP64PrefixDecoder
28 from soc.decoder.decode2execute1 import IssuerDecode2ToOperand
29 from soc.decoder.decode2execute1 import Data
30 from soc.experiment.testmem import TestMemory # test only for instructions
31 from soc.regfile.regfiles import StateRegs, FastRegs
32 from soc.simple.core import NonProductionCore
33 from soc.config.test.test_loadstore import TestMemPspec
34 from soc.config.ifetch import ConfigFetchUnit
35 from soc.decoder.power_enums import (MicrOp, SVP64PredInt, SVP64PredCR,
36 SVP64PredMode)
37 from soc.consts import CR
38 from soc.debug.dmi import CoreDebug, DMIInterface
39 from soc.debug.jtag import JTAG
40 from soc.config.pinouts import get_pinspecs
41 from soc.config.state import CoreState
42 from soc.interrupts.xics import XICS_ICP, XICS_ICS
43 from soc.bus.simple_gpio import SimpleGPIO
44 from soc.bus.SPBlock512W64B8W import SPBlock512W64B8W
45 from soc.clock.select import ClockSelect
46 from soc.clock.dummypll import DummyPLL
47 from soc.sv.svstate import SVSTATERec
48
49
50 from nmutil.util import rising_edge
51
52 def get_insn(f_instr_o, pc):
53 if f_instr_o.width == 32:
54 return f_instr_o
55 else:
56 # 64-bit: bit 2 of pc decides which word to select
57 return f_instr_o.word_select(pc[2], 32)
58
59 # gets state input or reads from state regfile
60 def state_get(m, core_rst, state_i, name, regfile, regnum):
61 comb = m.d.comb
62 sync = m.d.sync
63 # read the PC
64 res = Signal(64, reset_less=True, name=name)
65 res_ok_delay = Signal(name="%s_ok_delay" % name)
66 with m.If(~core_rst):
67 sync += res_ok_delay.eq(~state_i.ok)
68 with m.If(state_i.ok):
69 # incoming override (start from pc_i)
70 comb += res.eq(state_i.data)
71 with m.Else():
72 # otherwise read StateRegs regfile for PC...
73 comb += regfile.ren.eq(1<<regnum)
74 # ... but on a 1-clock delay
75 with m.If(res_ok_delay):
76 comb += res.eq(regfile.data_o)
77 return res
78
79 def get_predint(m, mask, name):
80 """decode SVP64 predicate integer mask field to reg number and invert
81 this is identical to the equivalent function in ISACaller except that
82 it doesn't read the INT directly, it just decodes "what needs to be done"
83 i.e. which INT reg, whether it is shifted and whether it is bit-inverted.
84
85 * all1s is set to indicate that no mask is to be applied.
86 * regread indicates the GPR register number to be read
87 * invert is set to indicate that the register value is to be inverted
88 * unary indicates that the contents of the register is to be shifted 1<<r3
89 """
90 comb = m.d.comb
91 regread = Signal(5, name=name+"regread")
92 invert = Signal(name=name+"invert")
93 unary = Signal(name=name+"unary")
94 all1s = Signal(name=name+"all1s")
95 with m.Switch(mask):
96 with m.Case(SVP64PredInt.ALWAYS.value):
97 comb += all1s.eq(1) # use 0b1111 (all ones)
98 with m.Case(SVP64PredInt.R3_UNARY.value):
99 comb += regread.eq(3)
100 comb += unary.eq(1) # 1<<r3 - shift r3 (single bit)
101 with m.Case(SVP64PredInt.R3.value):
102 comb += regread.eq(3)
103 with m.Case(SVP64PredInt.R3_N.value):
104 comb += regread.eq(3)
105 comb += invert.eq(1)
106 with m.Case(SVP64PredInt.R10.value):
107 comb += regread.eq(10)
108 with m.Case(SVP64PredInt.R10_N.value):
109 comb += regread.eq(10)
110 comb += invert.eq(1)
111 with m.Case(SVP64PredInt.R30.value):
112 comb += regread.eq(30)
113 with m.Case(SVP64PredInt.R30_N.value):
114 comb += regread.eq(30)
115 comb += invert.eq(1)
116 return regread, invert, unary, all1s
117
118 def get_predcr(m, mask, name):
119 """decode SVP64 predicate CR to reg number field and invert status
120 this is identical to _get_predcr in ISACaller
121 """
122 comb = m.d.comb
123 idx = Signal(2, name=name+"idx")
124 invert = Signal(name=name+"crinvert")
125 with m.Switch(mask):
126 with m.Case(SVP64PredCR.LT.value):
127 comb += idx.eq(CR.LT)
128 comb += invert.eq(0)
129 with m.Case(SVP64PredCR.GE.value):
130 comb += idx.eq(CR.LT)
131 comb += invert.eq(1)
132 with m.Case(SVP64PredCR.GT.value):
133 comb += idx.eq(CR.GT)
134 comb += invert.eq(0)
135 with m.Case(SVP64PredCR.LE.value):
136 comb += idx.eq(CR.GT)
137 comb += invert.eq(1)
138 with m.Case(SVP64PredCR.EQ.value):
139 comb += idx.eq(CR.EQ)
140 comb += invert.eq(0)
141 with m.Case(SVP64PredCR.NE.value):
142 comb += idx.eq(CR.EQ)
143 comb += invert.eq(1)
144 with m.Case(SVP64PredCR.SO.value):
145 comb += idx.eq(CR.SO)
146 comb += invert.eq(0)
147 with m.Case(SVP64PredCR.NS.value):
148 comb += idx.eq(CR.SO)
149 comb += invert.eq(1)
150 return idx, invert
151
152
153 class TestIssuerInternal(Elaboratable):
154 """TestIssuer - reads instructions from TestMemory and issues them
155
156 efficiency and speed is not the main goal here: functional correctness
157 and code clarity is. optimisations (which almost 100% interfere with
158 easy understanding) come later.
159 """
160 def __init__(self, pspec):
161
162 # test is SVP64 is to be enabled
163 self.svp64_en = hasattr(pspec, "svp64") and (pspec.svp64 == True)
164
165 # and if regfiles are reduced
166 self.regreduce_en = (hasattr(pspec, "regreduce") and
167 (pspec.regreduce == True))
168
169 # JTAG interface. add this right at the start because if it's
170 # added it *modifies* the pspec, by adding enable/disable signals
171 # for parts of the rest of the core
172 self.jtag_en = hasattr(pspec, "debug") and pspec.debug == 'jtag'
173 if self.jtag_en:
174 # XXX MUST keep this up-to-date with litex, and
175 # soc-cocotb-sim, and err.. all needs sorting out, argh
176 subset = ['uart',
177 'mtwi',
178 'eint', 'gpio', 'mspi0',
179 # 'mspi1', - disabled for now
180 # 'pwm', 'sd0', - disabled for now
181 'sdr']
182 self.jtag = JTAG(get_pinspecs(subset=subset))
183 # add signals to pspec to enable/disable icache and dcache
184 # (or data and intstruction wishbone if icache/dcache not included)
185 # https://bugs.libre-soc.org/show_bug.cgi?id=520
186 # TODO: do we actually care if these are not domain-synchronised?
187 # honestly probably not.
188 pspec.wb_icache_en = self.jtag.wb_icache_en
189 pspec.wb_dcache_en = self.jtag.wb_dcache_en
190 self.wb_sram_en = self.jtag.wb_sram_en
191 else:
192 self.wb_sram_en = Const(1)
193
194 # add 4k sram blocks?
195 self.sram4x4k = (hasattr(pspec, "sram4x4kblock") and
196 pspec.sram4x4kblock == True)
197 if self.sram4x4k:
198 self.sram4k = []
199 for i in range(4):
200 self.sram4k.append(SPBlock512W64B8W(name="sram4k_%d" % i,
201 features={'err'}))
202
203 # add interrupt controller?
204 self.xics = hasattr(pspec, "xics") and pspec.xics == True
205 if self.xics:
206 self.xics_icp = XICS_ICP()
207 self.xics_ics = XICS_ICS()
208 self.int_level_i = self.xics_ics.int_level_i
209
210 # add GPIO peripheral?
211 self.gpio = hasattr(pspec, "gpio") and pspec.gpio == True
212 if self.gpio:
213 self.simple_gpio = SimpleGPIO()
214 self.gpio_o = self.simple_gpio.gpio_o
215
216 # main instruction core. suitable for prototyping / demo only
217 self.core = core = NonProductionCore(pspec)
218
219 # instruction decoder. goes into Trap Record
220 pdecode = create_pdecode()
221 self.cur_state = CoreState("cur") # current state (MSR/PC/SVSTATE)
222 self.pdecode2 = PowerDecode2(pdecode, state=self.cur_state,
223 opkls=IssuerDecode2ToOperand,
224 svp64_en=self.svp64_en,
225 regreduce_en=self.regreduce_en)
226 if self.svp64_en:
227 self.svp64 = SVP64PrefixDecoder() # for decoding SVP64 prefix
228
229 # Test Instruction memory
230 self.imem = ConfigFetchUnit(pspec).fu
231
232 # DMI interface
233 self.dbg = CoreDebug()
234
235 # instruction go/monitor
236 self.pc_o = Signal(64, reset_less=True)
237 self.pc_i = Data(64, "pc_i") # set "ok" to indicate "please change me"
238 self.svstate_i = Data(32, "svstate_i") # ditto
239 self.core_bigendian_i = Signal() # TODO: set based on MSR.LE
240 self.busy_o = Signal(reset_less=True)
241 self.memerr_o = Signal(reset_less=True)
242
243 # STATE regfile read /write ports for PC, MSR, SVSTATE
244 staterf = self.core.regs.rf['state']
245 self.state_r_pc = staterf.r_ports['cia'] # PC rd
246 self.state_w_pc = staterf.w_ports['d_wr1'] # PC wr
247 self.state_r_msr = staterf.r_ports['msr'] # MSR rd
248 self.state_r_sv = staterf.r_ports['sv'] # SVSTATE rd
249 self.state_w_sv = staterf.w_ports['sv'] # SVSTATE wr
250
251 # DMI interface access
252 intrf = self.core.regs.rf['int']
253 crrf = self.core.regs.rf['cr']
254 xerrf = self.core.regs.rf['xer']
255 self.int_r = intrf.r_ports['dmi'] # INT read
256 self.cr_r = crrf.r_ports['full_cr_dbg'] # CR read
257 self.xer_r = xerrf.r_ports['full_xer'] # XER read
258
259 if self.svp64_en:
260 # for predication
261 self.int_pred = intrf.r_ports['pred'] # INT predicate read
262 self.cr_pred = crrf.r_ports['cr_pred'] # CR predicate read
263
264 # hack method of keeping an eye on whether branch/trap set the PC
265 self.state_nia = self.core.regs.rf['state'].w_ports['nia']
266 self.state_nia.wen.name = 'state_nia_wen'
267
268 # pulse to synchronize the simulator at instruction end
269 self.insn_done = Signal()
270
271 if self.svp64_en:
272 # store copies of predicate masks
273 self.srcmask = Signal(64)
274 self.dstmask = Signal(64)
275
276 def fetch_fsm(self, m, core, pc, svstate, nia, is_svp64_mode,
277 fetch_pc_ready_o, fetch_pc_valid_i,
278 fetch_insn_valid_o, fetch_insn_ready_i):
279 """fetch FSM
280
281 this FSM performs fetch of raw instruction data, partial-decodes
282 it 32-bit at a time to detect SVP64 prefixes, and will optionally
283 read a 2nd 32-bit quantity if that occurs.
284 """
285 comb = m.d.comb
286 sync = m.d.sync
287 pdecode2 = self.pdecode2
288 cur_state = self.cur_state
289 dec_opcode_i = pdecode2.dec.raw_opcode_in # raw opcode
290
291 msr_read = Signal(reset=1)
292
293 with m.FSM(name='fetch_fsm'):
294
295 # waiting (zzz)
296 with m.State("IDLE"):
297 comb += fetch_pc_ready_o.eq(1)
298 with m.If(fetch_pc_valid_i):
299 # instruction allowed to go: start by reading the PC
300 # capture the PC and also drop it into Insn Memory
301 # we have joined a pair of combinatorial memory
302 # lookups together. this is Generally Bad.
303 comb += self.imem.a_pc_i.eq(pc)
304 comb += self.imem.a_valid_i.eq(1)
305 comb += self.imem.f_valid_i.eq(1)
306 sync += cur_state.pc.eq(pc)
307 sync += cur_state.svstate.eq(svstate) # and svstate
308
309 # initiate read of MSR. arrives one clock later
310 comb += self.state_r_msr.ren.eq(1 << StateRegs.MSR)
311 sync += msr_read.eq(0)
312
313 m.next = "INSN_READ" # move to "wait for bus" phase
314
315 # dummy pause to find out why simulation is not keeping up
316 with m.State("INSN_READ"):
317 # one cycle later, msr/sv read arrives. valid only once.
318 with m.If(~msr_read):
319 sync += msr_read.eq(1) # yeah don't read it again
320 sync += cur_state.msr.eq(self.state_r_msr.data_o)
321 with m.If(self.imem.f_busy_o): # zzz...
322 # busy: stay in wait-read
323 comb += self.imem.a_valid_i.eq(1)
324 comb += self.imem.f_valid_i.eq(1)
325 with m.Else():
326 # not busy: instruction fetched
327 insn = get_insn(self.imem.f_instr_o, cur_state.pc)
328 if self.svp64_en:
329 svp64 = self.svp64
330 # decode the SVP64 prefix, if any
331 comb += svp64.raw_opcode_in.eq(insn)
332 comb += svp64.bigendian.eq(self.core_bigendian_i)
333 # pass the decoded prefix (if any) to PowerDecoder2
334 sync += pdecode2.sv_rm.eq(svp64.svp64_rm)
335 # remember whether this is a prefixed instruction, so
336 # the FSM can readily loop when VL==0
337 sync += is_svp64_mode.eq(svp64.is_svp64_mode)
338 # calculate the address of the following instruction
339 insn_size = Mux(svp64.is_svp64_mode, 8, 4)
340 sync += nia.eq(cur_state.pc + insn_size)
341 with m.If(~svp64.is_svp64_mode):
342 # with no prefix, store the instruction
343 # and hand it directly to the next FSM
344 sync += dec_opcode_i.eq(insn)
345 m.next = "INSN_READY"
346 with m.Else():
347 # fetch the rest of the instruction from memory
348 comb += self.imem.a_pc_i.eq(cur_state.pc + 4)
349 comb += self.imem.a_valid_i.eq(1)
350 comb += self.imem.f_valid_i.eq(1)
351 m.next = "INSN_READ2"
352 else:
353 # not SVP64 - 32-bit only
354 sync += nia.eq(cur_state.pc + 4)
355 sync += dec_opcode_i.eq(insn)
356 m.next = "INSN_READY"
357
358 with m.State("INSN_READ2"):
359 with m.If(self.imem.f_busy_o): # zzz...
360 # busy: stay in wait-read
361 comb += self.imem.a_valid_i.eq(1)
362 comb += self.imem.f_valid_i.eq(1)
363 with m.Else():
364 # not busy: instruction fetched
365 insn = get_insn(self.imem.f_instr_o, cur_state.pc+4)
366 sync += dec_opcode_i.eq(insn)
367 m.next = "INSN_READY"
368 # TODO: probably can start looking at pdecode2.rm_dec
369 # here or maybe even in INSN_READ state, if svp64_mode
370 # detected, in order to trigger - and wait for - the
371 # predicate reading.
372 if self.svp64_en:
373 pmode = pdecode2.rm_dec.predmode
374 """
375 if pmode != SVP64PredMode.ALWAYS.value:
376 fire predicate loading FSM and wait before
377 moving to INSN_READY
378 else:
379 sync += self.srcmask.eq(-1) # set to all 1s
380 sync += self.dstmask.eq(-1) # set to all 1s
381 m.next = "INSN_READY"
382 """
383
384 with m.State("INSN_READY"):
385 # hand over the instruction, to be decoded
386 comb += fetch_insn_valid_o.eq(1)
387 with m.If(fetch_insn_ready_i):
388 m.next = "IDLE"
389
390 def fetch_predicate_fsm(self, m,
391 pred_insn_valid_i, pred_insn_ready_o,
392 pred_mask_valid_o, pred_mask_ready_i):
393 """fetch_predicate_fsm - obtains (constructs in the case of CR)
394 src/dest predicate masks
395
396 https://bugs.libre-soc.org/show_bug.cgi?id=617
397 the predicates can be read here, by using IntRegs r_ports['pred']
398 or CRRegs r_ports['pred']. in the case of CRs it will have to
399 be done through multiple reads, extracting one relevant at a time.
400 later, a faster way would be to use the 32-bit-wide CR port but
401 this is more complex decoding, here. equivalent code used in
402 ISACaller is "from soc.decoder.isa.caller import get_predcr"
403
404 note: this ENTIRE FSM is not to be called when svp64 is disabled
405 """
406 comb = m.d.comb
407 sync = m.d.sync
408 pdecode2 = self.pdecode2
409 rm_dec = pdecode2.rm_dec # SVP64RMModeDecode
410 predmode = rm_dec.predmode
411 srcpred, dstpred = rm_dec.srcpred, rm_dec.dstpred
412 cr_pred, int_pred = self.cr_pred, self.int_pred # read regfiles
413 # get src/dst step, so we can skip already used mask bits
414 cur_state = self.cur_state
415 srcstep = cur_state.svstate.srcstep
416 dststep = cur_state.svstate.dststep
417
418 # elif predmode == CR:
419 # CR-src sidx, sinvert = get_predcr(m, srcpred)
420 # CR-dst didx, dinvert = get_predcr(m, dstpred)
421 # TODO read CR-src and CR-dst into self.srcmask+dstmask with loop
422 # has to cope with first one then the other
423 # for cr_idx = FSM-state-loop(0..VL-1):
424 # FSM-state-trigger-CR-read:
425 # cr_ren = (1<<7-(cr_idx+SVP64CROffs.CRPred))
426 # comb += cr_pred.ren.eq(cr_ren)
427 # FSM-state-1-clock-later-actual-Read:
428 # cr_field = Signal(4)
429 # cr_bit = Signal(1)
430 # # read the CR field, select the appropriate bit
431 # comb += cr_field.eq(cr_pred.data_o)
432 # comb += cr_bit.eq(cr_field.bit_select(idx)))
433 # # just like in branch BO tests
434 # comd += self.srcmask[cr_idx].eq(inv ^ cr_bit)
435
436 # decode predicates
437 sregread, sinvert, sunary, sall1s = get_predint(m, srcpred, 's')
438 dregread, dinvert, dunary, dall1s = get_predint(m, dstpred, 'd')
439 sidx, scrinvert = get_predcr(m, srcpred, 's')
440 didx, dcrinvert = get_predcr(m, dstpred, 'd')
441
442 with m.FSM(name="fetch_predicate"):
443
444 with m.State("FETCH_PRED_IDLE"):
445 comb += pred_insn_ready_o.eq(1)
446 with m.If(pred_insn_valid_i):
447 with m.If(predmode == SVP64PredMode.INT):
448 # skip fetching destination mask register, when zero
449 with m.If(dall1s):
450 sync += self.dstmask.eq(-1)
451 # directly go to fetch source mask register
452 # guaranteed not to be zero (otherwise predmode
453 # would be SVP64PredMode.ALWAYS, not INT)
454 comb += int_pred.addr.eq(sregread)
455 comb += int_pred.ren.eq(1)
456 m.next = "INT_SRC_READ"
457 # fetch destination predicate register
458 with m.Else():
459 comb += int_pred.addr.eq(dregread)
460 comb += int_pred.ren.eq(1)
461 m.next = "INT_DST_READ"
462 with m.Else():
463 sync += self.srcmask.eq(-1)
464 sync += self.dstmask.eq(-1)
465 m.next = "FETCH_PRED_DONE"
466
467 with m.State("INT_DST_READ"):
468 # store destination mask
469 inv = Repl(dinvert, 64)
470 new_dstmask = Signal(64)
471 with m.If(dunary):
472 # set selected mask bit for 1<<r3 mode
473 dst_shift = Signal(range(64))
474 comb += dst_shift.eq(self.int_pred.data_o & 0b111111)
475 comb += new_dstmask.eq(1 << dst_shift)
476 with m.Else():
477 # invert mask if requested
478 comb += new_dstmask.eq(self.int_pred.data_o ^ inv)
479 # shift-out already used mask bits
480 sync += self.dstmask.eq(new_dstmask >> dststep)
481 # skip fetching source mask register, when zero
482 with m.If(sall1s):
483 sync += self.srcmask.eq(-1)
484 m.next = "FETCH_PRED_DONE"
485 # fetch source predicate register
486 with m.Else():
487 comb += int_pred.addr.eq(sregread)
488 comb += int_pred.ren.eq(1)
489 m.next = "INT_SRC_READ"
490
491 with m.State("INT_SRC_READ"):
492 # store source mask
493 inv = Repl(sinvert, 64)
494 new_srcmask = Signal(64)
495 with m.If(sunary):
496 # set selected mask bit for 1<<r3 mode
497 src_shift = Signal(range(64))
498 comb += src_shift.eq(self.int_pred.data_o & 0b111111)
499 comb += new_srcmask.eq(1 << src_shift)
500 with m.Else():
501 # invert mask if requested
502 comb += new_srcmask.eq(self.int_pred.data_o ^ inv)
503 # shift-out already used mask bits
504 sync += self.srcmask.eq(new_srcmask >> srcstep)
505 m.next = "FETCH_PRED_DONE"
506
507 with m.State("FETCH_PRED_DONE"):
508 comb += pred_mask_valid_o.eq(1)
509 with m.If(pred_mask_ready_i):
510 m.next = "FETCH_PRED_IDLE"
511
512 def issue_fsm(self, m, core, pc_changed, sv_changed, nia,
513 dbg, core_rst, is_svp64_mode,
514 fetch_pc_ready_o, fetch_pc_valid_i,
515 fetch_insn_valid_o, fetch_insn_ready_i,
516 pred_insn_valid_i, pred_insn_ready_o,
517 pred_mask_valid_o, pred_mask_ready_i,
518 exec_insn_valid_i, exec_insn_ready_o,
519 exec_pc_valid_o, exec_pc_ready_i):
520 """issue FSM
521
522 decode / issue FSM. this interacts with the "fetch" FSM
523 through fetch_insn_ready/valid (incoming) and fetch_pc_ready/valid
524 (outgoing). also interacts with the "execute" FSM
525 through exec_insn_ready/valid (outgoing) and exec_pc_ready/valid
526 (incoming).
527 SVP64 RM prefixes have already been set up by the
528 "fetch" phase, so execute is fairly straightforward.
529 """
530
531 comb = m.d.comb
532 sync = m.d.sync
533 pdecode2 = self.pdecode2
534 cur_state = self.cur_state
535
536 # temporaries
537 dec_opcode_i = pdecode2.dec.raw_opcode_in # raw opcode
538
539 # for updating svstate (things like srcstep etc.)
540 update_svstate = Signal() # set this (below) if updating
541 new_svstate = SVSTATERec("new_svstate")
542 comb += new_svstate.eq(cur_state.svstate)
543
544 # precalculate srcstep+1 and dststep+1
545 cur_srcstep = cur_state.svstate.srcstep
546 cur_dststep = cur_state.svstate.dststep
547 next_srcstep = Signal.like(cur_srcstep)
548 next_dststep = Signal.like(cur_dststep)
549 comb += next_srcstep.eq(cur_state.svstate.srcstep+1)
550 comb += next_dststep.eq(cur_state.svstate.dststep+1)
551
552 with m.FSM(name="issue_fsm"):
553
554 # sync with the "fetch" phase which is reading the instruction
555 # at this point, there is no instruction running, that
556 # could inadvertently update the PC.
557 with m.State("ISSUE_START"):
558 # wait on "core stop" release, before next fetch
559 # need to do this here, in case we are in a VL==0 loop
560 with m.If(~dbg.core_stop_o & ~core_rst):
561 comb += fetch_pc_valid_i.eq(1) # tell fetch to start
562 with m.If(fetch_pc_ready_o): # fetch acknowledged us
563 m.next = "INSN_WAIT"
564 with m.Else():
565 # tell core it's stopped, and acknowledge debug handshake
566 comb += dbg.core_stopped_i.eq(1)
567 # while stopped, allow updating the PC and SVSTATE
568 with m.If(self.pc_i.ok):
569 comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
570 comb += self.state_w_pc.data_i.eq(self.pc_i.data)
571 sync += pc_changed.eq(1)
572 with m.If(self.svstate_i.ok):
573 comb += new_svstate.eq(self.svstate_i.data)
574 comb += update_svstate.eq(1)
575 sync += sv_changed.eq(1)
576
577 # wait for an instruction to arrive from Fetch
578 with m.State("INSN_WAIT"):
579 comb += fetch_insn_ready_i.eq(1)
580 with m.If(fetch_insn_valid_o):
581 # loop into ISSUE_START if it's a SVP64 instruction
582 # and VL == 0. this because VL==0 is a for-loop
583 # from 0 to 0 i.e. always, always a NOP.
584 cur_vl = cur_state.svstate.vl
585 with m.If(is_svp64_mode & (cur_vl == 0)):
586 # update the PC before fetching the next instruction
587 # since we are in a VL==0 loop, no instruction was
588 # executed that we could be overwriting
589 comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
590 comb += self.state_w_pc.data_i.eq(nia)
591 comb += self.insn_done.eq(1)
592 m.next = "ISSUE_START"
593 with m.Else():
594 if self.svp64_en:
595 m.next = "PRED_START" # start fetching predicate
596 else:
597 m.next = "DECODE_SV" # skip predication
598
599 with m.State("PRED_START"):
600 comb += pred_insn_valid_i.eq(1) # tell fetch_pred to start
601 with m.If(pred_insn_ready_o): # fetch_pred acknowledged us
602 m.next = "MASK_WAIT"
603
604 with m.State("MASK_WAIT"):
605 comb += pred_mask_ready_i.eq(1) # ready to receive the masks
606 with m.If(pred_mask_valid_o): # predication masks are ready
607 m.next = "PRED_SKIP"
608
609 # skip zeros in predicate
610 with m.State("PRED_SKIP"):
611 with m.If(~is_svp64_mode):
612 m.next = "DECODE_SV" # nothing to do
613 with m.Else():
614 if self.svp64_en:
615 pred_src_zero = pdecode2.rm_dec.pred_sz
616 pred_dst_zero = pdecode2.rm_dec.pred_dz
617
618 # new srcstep, after skipping zeros
619 skip_srcstep = Signal.like(cur_srcstep)
620 # value to be added to the current srcstep
621 src_delta = Signal.like(cur_srcstep)
622 # add leading zeros to srcstep, if not in zero mode
623 with m.If(~pred_src_zero):
624 # priority encoder (count leading zeros)
625 # append guard bit, in case the mask is all zeros
626 pri_enc_src = PriorityEncoder(65)
627 m.submodules.pri_enc_src = pri_enc_src
628 comb += pri_enc_src.i.eq(Cat(self.srcmask,
629 Const(1, 1)))
630 comb += src_delta.eq(pri_enc_src.o)
631 # apply delta to srcstep
632 comb += skip_srcstep.eq(cur_srcstep + src_delta)
633 # shift-out all leading zeros from the mask
634 # plus the leading "one" bit
635 # TODO count leading zeros and shift-out the zero
636 # bits, in the same step, in hardware
637 sync += self.srcmask.eq(self.srcmask >> (src_delta+1))
638
639 # same as above, but for dststep
640 skip_dststep = Signal.like(cur_dststep)
641 dst_delta = Signal.like(cur_dststep)
642 with m.If(~pred_dst_zero):
643 pri_enc_dst = PriorityEncoder(65)
644 m.submodules.pri_enc_dst = pri_enc_dst
645 comb += pri_enc_dst.i.eq(Cat(self.dstmask,
646 Const(1, 1)))
647 comb += dst_delta.eq(pri_enc_dst.o)
648 comb += skip_dststep.eq(cur_dststep + dst_delta)
649 sync += self.dstmask.eq(self.dstmask >> (dst_delta+1))
650
651 # TODO: initialize mask[VL]=1 to avoid passing past VL
652 with m.If((skip_srcstep >= cur_vl) |
653 (skip_dststep >= cur_vl)):
654 # end of VL loop. Update PC and reset src/dst step
655 comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
656 comb += self.state_w_pc.data_i.eq(nia)
657 comb += new_svstate.srcstep.eq(0)
658 comb += new_svstate.dststep.eq(0)
659 comb += update_svstate.eq(1)
660 # synchronize with the simulator
661 comb += self.insn_done.eq(1)
662 # go back to Issue
663 m.next = "ISSUE_START"
664 with m.Else():
665 # update new src/dst step
666 comb += new_svstate.srcstep.eq(skip_srcstep)
667 comb += new_svstate.dststep.eq(skip_dststep)
668 comb += update_svstate.eq(1)
669 # proceed to Decode
670 m.next = "DECODE_SV"
671
672 # after src/dst step have been updated, we are ready
673 # to decode the instruction
674 with m.State("DECODE_SV"):
675 # decode the instruction
676 sync += core.e.eq(pdecode2.e)
677 sync += core.state.eq(cur_state)
678 sync += core.raw_insn_i.eq(dec_opcode_i)
679 sync += core.bigendian_i.eq(self.core_bigendian_i)
680 # set RA_OR_ZERO detection in satellite decoders
681 sync += core.sv_a_nz.eq(pdecode2.sv_a_nz)
682 m.next = "INSN_EXECUTE" # move to "execute"
683
684 # handshake with execution FSM, move to "wait" once acknowledged
685 with m.State("INSN_EXECUTE"):
686 comb += exec_insn_valid_i.eq(1) # trigger execute
687 with m.If(exec_insn_ready_o): # execute acknowledged us
688 m.next = "EXECUTE_WAIT"
689
690 with m.State("EXECUTE_WAIT"):
691 # wait on "core stop" release, at instruction end
692 # need to do this here, in case we are in a VL>1 loop
693 with m.If(~dbg.core_stop_o & ~core_rst):
694 comb += exec_pc_ready_i.eq(1)
695 with m.If(exec_pc_valid_o):
696
697 # was this the last loop iteration?
698 is_last = Signal()
699 cur_vl = cur_state.svstate.vl
700 comb += is_last.eq(next_srcstep == cur_vl)
701
702 # if either PC or SVSTATE were changed by the previous
703 # instruction, go directly back to Fetch, without
704 # updating either PC or SVSTATE
705 with m.If(pc_changed | sv_changed):
706 m.next = "ISSUE_START"
707
708 # also return to Fetch, when no output was a vector
709 # (regardless of SRCSTEP and VL), or when the last
710 # instruction was really the last one of the VL loop
711 with m.Elif((~pdecode2.loop_continue) | is_last):
712 # before going back to fetch, update the PC state
713 # register with the NIA.
714 # ok here we are not reading the branch unit.
715 # TODO: this just blithely overwrites whatever
716 # pipeline updated the PC
717 comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
718 comb += self.state_w_pc.data_i.eq(nia)
719 # reset SRCSTEP before returning to Fetch
720 if self.svp64_en:
721 with m.If(pdecode2.loop_continue):
722 comb += new_svstate.srcstep.eq(0)
723 comb += new_svstate.dststep.eq(0)
724 comb += update_svstate.eq(1)
725 else:
726 comb += new_svstate.srcstep.eq(0)
727 comb += new_svstate.dststep.eq(0)
728 comb += update_svstate.eq(1)
729 m.next = "ISSUE_START"
730
731 # returning to Execute? then, first update SRCSTEP
732 with m.Else():
733 comb += new_svstate.srcstep.eq(next_srcstep)
734 comb += new_svstate.dststep.eq(next_dststep)
735 comb += update_svstate.eq(1)
736 # return to mask skip loop
737 m.next = "PRED_SKIP"
738
739 with m.Else():
740 comb += dbg.core_stopped_i.eq(1)
741 # while stopped, allow updating the PC and SVSTATE
742 with m.If(self.pc_i.ok):
743 comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
744 comb += self.state_w_pc.data_i.eq(self.pc_i.data)
745 sync += pc_changed.eq(1)
746 with m.If(self.svstate_i.ok):
747 comb += new_svstate.eq(self.svstate_i.data)
748 comb += update_svstate.eq(1)
749 sync += sv_changed.eq(1)
750
751 # check if svstate needs updating: if so, write it to State Regfile
752 with m.If(update_svstate):
753 comb += self.state_w_sv.wen.eq(1<<StateRegs.SVSTATE)
754 comb += self.state_w_sv.data_i.eq(new_svstate)
755 sync += cur_state.svstate.eq(new_svstate) # for next clock
756
757 def execute_fsm(self, m, core, pc_changed, sv_changed,
758 exec_insn_valid_i, exec_insn_ready_o,
759 exec_pc_valid_o, exec_pc_ready_i):
760 """execute FSM
761
762 execute FSM. this interacts with the "issue" FSM
763 through exec_insn_ready/valid (incoming) and exec_pc_ready/valid
764 (outgoing). SVP64 RM prefixes have already been set up by the
765 "issue" phase, so execute is fairly straightforward.
766 """
767
768 comb = m.d.comb
769 sync = m.d.sync
770 pdecode2 = self.pdecode2
771
772 # temporaries
773 core_busy_o = core.busy_o # core is busy
774 core_ivalid_i = core.ivalid_i # instruction is valid
775 core_issue_i = core.issue_i # instruction is issued
776 insn_type = core.e.do.insn_type # instruction MicroOp type
777
778 with m.FSM(name="exec_fsm"):
779
780 # waiting for instruction bus (stays there until not busy)
781 with m.State("INSN_START"):
782 comb += exec_insn_ready_o.eq(1)
783 with m.If(exec_insn_valid_i):
784 comb += core_ivalid_i.eq(1) # instruction is valid
785 comb += core_issue_i.eq(1) # and issued
786 sync += sv_changed.eq(0)
787 sync += pc_changed.eq(0)
788 m.next = "INSN_ACTIVE" # move to "wait completion"
789
790 # instruction started: must wait till it finishes
791 with m.State("INSN_ACTIVE"):
792 with m.If(insn_type != MicrOp.OP_NOP):
793 comb += core_ivalid_i.eq(1) # instruction is valid
794 # note changes to PC and SVSTATE
795 with m.If(self.state_nia.wen & (1<<StateRegs.SVSTATE)):
796 sync += sv_changed.eq(1)
797 with m.If(self.state_nia.wen & (1<<StateRegs.PC)):
798 sync += pc_changed.eq(1)
799 with m.If(~core_busy_o): # instruction done!
800 comb += exec_pc_valid_o.eq(1)
801 with m.If(exec_pc_ready_i):
802 comb += self.insn_done.eq(1)
803 m.next = "INSN_START" # back to fetch
804
805 def setup_peripherals(self, m):
806 comb, sync = m.d.comb, m.d.sync
807
808 m.submodules.core = core = DomainRenamer("coresync")(self.core)
809 m.submodules.imem = imem = self.imem
810 m.submodules.dbg = dbg = self.dbg
811 if self.jtag_en:
812 m.submodules.jtag = jtag = self.jtag
813 # TODO: UART2GDB mux, here, from external pin
814 # see https://bugs.libre-soc.org/show_bug.cgi?id=499
815 sync += dbg.dmi.connect_to(jtag.dmi)
816
817 cur_state = self.cur_state
818
819 # 4x 4k SRAM blocks. these simply "exist", they get routed in litex
820 if self.sram4x4k:
821 for i, sram in enumerate(self.sram4k):
822 m.submodules["sram4k_%d" % i] = sram
823 comb += sram.enable.eq(self.wb_sram_en)
824
825 # XICS interrupt handler
826 if self.xics:
827 m.submodules.xics_icp = icp = self.xics_icp
828 m.submodules.xics_ics = ics = self.xics_ics
829 comb += icp.ics_i.eq(ics.icp_o) # connect ICS to ICP
830 sync += cur_state.eint.eq(icp.core_irq_o) # connect ICP to core
831
832 # GPIO test peripheral
833 if self.gpio:
834 m.submodules.simple_gpio = simple_gpio = self.simple_gpio
835
836 # connect one GPIO output to ICS bit 15 (like in microwatt soc.vhdl)
837 # XXX causes litex ECP5 test to get wrong idea about input and output
838 # (but works with verilator sim *sigh*)
839 #if self.gpio and self.xics:
840 # comb += self.int_level_i[15].eq(simple_gpio.gpio_o[0])
841
842 # instruction decoder
843 pdecode = create_pdecode()
844 m.submodules.dec2 = pdecode2 = self.pdecode2
845 if self.svp64_en:
846 m.submodules.svp64 = svp64 = self.svp64
847
848 # convenience
849 dmi, d_reg, d_cr, d_xer, = dbg.dmi, dbg.d_gpr, dbg.d_cr, dbg.d_xer
850 intrf = self.core.regs.rf['int']
851
852 # clock delay power-on reset
853 cd_por = ClockDomain(reset_less=True)
854 cd_sync = ClockDomain()
855 core_sync = ClockDomain("coresync")
856 m.domains += cd_por, cd_sync, core_sync
857
858 ti_rst = Signal(reset_less=True)
859 delay = Signal(range(4), reset=3)
860 with m.If(delay != 0):
861 m.d.por += delay.eq(delay - 1)
862 comb += cd_por.clk.eq(ClockSignal())
863
864 # power-on reset delay
865 core_rst = ResetSignal("coresync")
866 comb += ti_rst.eq(delay != 0 | dbg.core_rst_o | ResetSignal())
867 comb += core_rst.eq(ti_rst)
868
869 # busy/halted signals from core
870 comb += self.busy_o.eq(core.busy_o)
871 comb += pdecode2.dec.bigendian.eq(self.core_bigendian_i)
872
873 # temporary hack: says "go" immediately for both address gen and ST
874 l0 = core.l0
875 ldst = core.fus.fus['ldst0']
876 st_go_edge = rising_edge(m, ldst.st.rel_o)
877 m.d.comb += ldst.ad.go_i.eq(ldst.ad.rel_o) # link addr-go direct to rel
878 m.d.comb += ldst.st.go_i.eq(st_go_edge) # link store-go to rising rel
879
880 return core_rst
881
882 def elaborate(self, platform):
883 m = Module()
884 # convenience
885 comb, sync = m.d.comb, m.d.sync
886 cur_state = self.cur_state
887 pdecode2 = self.pdecode2
888 dbg = self.dbg
889 core = self.core
890
891 # set up peripherals and core
892 core_rst = self.setup_peripherals(m)
893
894 # reset current state if core reset requested
895 with m.If(core_rst):
896 m.d.sync += self.cur_state.eq(0)
897
898 # PC and instruction from I-Memory
899 comb += self.pc_o.eq(cur_state.pc)
900 pc_changed = Signal() # note write to PC
901 sv_changed = Signal() # note write to SVSTATE
902
903 # read state either from incoming override or from regfile
904 # TODO: really should be doing MSR in the same way
905 pc = state_get(m, core_rst, self.pc_i,
906 "pc", # read PC
907 self.state_r_pc, StateRegs.PC)
908 svstate = state_get(m, core_rst, self.svstate_i,
909 "svstate", # read SVSTATE
910 self.state_r_sv, StateRegs.SVSTATE)
911
912 # don't write pc every cycle
913 comb += self.state_w_pc.wen.eq(0)
914 comb += self.state_w_pc.data_i.eq(0)
915
916 # don't read msr every cycle
917 comb += self.state_r_msr.ren.eq(0)
918
919 # address of the next instruction, in the absence of a branch
920 # depends on the instruction size
921 nia = Signal(64)
922
923 # connect up debug signals
924 # TODO comb += core.icache_rst_i.eq(dbg.icache_rst_o)
925 comb += dbg.terminate_i.eq(core.core_terminate_o)
926 comb += dbg.state.pc.eq(pc)
927 comb += dbg.state.svstate.eq(svstate)
928 comb += dbg.state.msr.eq(cur_state.msr)
929
930 # pass the prefix mode from Fetch to Issue, so the latter can loop
931 # on VL==0
932 is_svp64_mode = Signal()
933
934 # there are *THREE* FSMs, fetch (32/64-bit) issue, decode/execute.
935 # these are the handshake signals between fetch and decode/execute
936
937 # fetch FSM can run as soon as the PC is valid
938 fetch_pc_valid_i = Signal() # Execute tells Fetch "start next read"
939 fetch_pc_ready_o = Signal() # Fetch Tells SVSTATE "proceed"
940
941 # fetch FSM hands over the instruction to be decoded / issued
942 fetch_insn_valid_o = Signal()
943 fetch_insn_ready_i = Signal()
944
945 # predicate fetch FSM decodes and fetches the predicate
946 pred_insn_valid_i = Signal()
947 pred_insn_ready_o = Signal()
948
949 # predicate fetch FSM delivers the masks
950 pred_mask_valid_o = Signal()
951 pred_mask_ready_i = Signal()
952
953 # issue FSM delivers the instruction to the be executed
954 exec_insn_valid_i = Signal()
955 exec_insn_ready_o = Signal()
956
957 # execute FSM, hands over the PC/SVSTATE back to the issue FSM
958 exec_pc_valid_o = Signal()
959 exec_pc_ready_i = Signal()
960
961 # the FSMs here are perhaps unusual in that they detect conditions
962 # then "hold" information, combinatorially, for the core
963 # (as opposed to using sync - which would be on a clock's delay)
964 # this includes the actual opcode, valid flags and so on.
965
966 # Fetch, then predicate fetch, then Issue, then Execute.
967 # Issue is where the VL for-loop # lives. the ready/valid
968 # signalling is used to communicate between the four.
969
970 self.fetch_fsm(m, core, pc, svstate, nia, is_svp64_mode,
971 fetch_pc_ready_o, fetch_pc_valid_i,
972 fetch_insn_valid_o, fetch_insn_ready_i)
973
974 self.issue_fsm(m, core, pc_changed, sv_changed, nia,
975 dbg, core_rst, is_svp64_mode,
976 fetch_pc_ready_o, fetch_pc_valid_i,
977 fetch_insn_valid_o, fetch_insn_ready_i,
978 pred_insn_valid_i, pred_insn_ready_o,
979 pred_mask_valid_o, pred_mask_ready_i,
980 exec_insn_valid_i, exec_insn_ready_o,
981 exec_pc_valid_o, exec_pc_ready_i)
982
983 if self.svp64_en:
984 self.fetch_predicate_fsm(m,
985 pred_insn_valid_i, pred_insn_ready_o,
986 pred_mask_valid_o, pred_mask_ready_i)
987
988 self.execute_fsm(m, core, pc_changed, sv_changed,
989 exec_insn_valid_i, exec_insn_ready_o,
990 exec_pc_valid_o, exec_pc_ready_i)
991
992 # whatever was done above, over-ride it if core reset is held
993 with m.If(core_rst):
994 sync += nia.eq(0)
995
996 # this bit doesn't have to be in the FSM: connect up to read
997 # regfiles on demand from DMI
998 self.do_dmi(m, dbg)
999
1000 # DEC and TB inc/dec FSM. copy of DEC is put into CoreState,
1001 # (which uses that in PowerDecoder2 to raise 0x900 exception)
1002 self.tb_dec_fsm(m, cur_state.dec)
1003
1004 return m
1005
1006 def do_dmi(self, m, dbg):
1007 """deals with DMI debug requests
1008
1009 currently only provides read requests for the INT regfile, CR and XER
1010 it will later also deal with *writing* to these regfiles.
1011 """
1012 comb = m.d.comb
1013 sync = m.d.sync
1014 dmi, d_reg, d_cr, d_xer, = dbg.dmi, dbg.d_gpr, dbg.d_cr, dbg.d_xer
1015 intrf = self.core.regs.rf['int']
1016
1017 with m.If(d_reg.req): # request for regfile access being made
1018 # TODO: error-check this
1019 # XXX should this be combinatorial? sync better?
1020 if intrf.unary:
1021 comb += self.int_r.ren.eq(1<<d_reg.addr)
1022 else:
1023 comb += self.int_r.addr.eq(d_reg.addr)
1024 comb += self.int_r.ren.eq(1)
1025 d_reg_delay = Signal()
1026 sync += d_reg_delay.eq(d_reg.req)
1027 with m.If(d_reg_delay):
1028 # data arrives one clock later
1029 comb += d_reg.data.eq(self.int_r.data_o)
1030 comb += d_reg.ack.eq(1)
1031
1032 # sigh same thing for CR debug
1033 with m.If(d_cr.req): # request for regfile access being made
1034 comb += self.cr_r.ren.eq(0b11111111) # enable all
1035 d_cr_delay = Signal()
1036 sync += d_cr_delay.eq(d_cr.req)
1037 with m.If(d_cr_delay):
1038 # data arrives one clock later
1039 comb += d_cr.data.eq(self.cr_r.data_o)
1040 comb += d_cr.ack.eq(1)
1041
1042 # aaand XER...
1043 with m.If(d_xer.req): # request for regfile access being made
1044 comb += self.xer_r.ren.eq(0b111111) # enable all
1045 d_xer_delay = Signal()
1046 sync += d_xer_delay.eq(d_xer.req)
1047 with m.If(d_xer_delay):
1048 # data arrives one clock later
1049 comb += d_xer.data.eq(self.xer_r.data_o)
1050 comb += d_xer.ack.eq(1)
1051
1052 def tb_dec_fsm(self, m, spr_dec):
1053 """tb_dec_fsm
1054
1055 this is a FSM for updating either dec or tb. it runs alternately
1056 DEC, TB, DEC, TB. note that SPR pipeline could have written a new
1057 value to DEC, however the regfile has "passthrough" on it so this
1058 *should* be ok.
1059
1060 see v3.0B p1097-1099 for Timeer Resource and p1065 and p1076
1061 """
1062
1063 comb, sync = m.d.comb, m.d.sync
1064 fast_rf = self.core.regs.rf['fast']
1065 fast_r_dectb = fast_rf.r_ports['issue'] # DEC/TB
1066 fast_w_dectb = fast_rf.w_ports['issue'] # DEC/TB
1067
1068 with m.FSM() as fsm:
1069
1070 # initiates read of current DEC
1071 with m.State("DEC_READ"):
1072 comb += fast_r_dectb.addr.eq(FastRegs.DEC)
1073 comb += fast_r_dectb.ren.eq(1)
1074 m.next = "DEC_WRITE"
1075
1076 # waits for DEC read to arrive (1 cycle), updates with new value
1077 with m.State("DEC_WRITE"):
1078 new_dec = Signal(64)
1079 # TODO: MSR.LPCR 32-bit decrement mode
1080 comb += new_dec.eq(fast_r_dectb.data_o - 1)
1081 comb += fast_w_dectb.addr.eq(FastRegs.DEC)
1082 comb += fast_w_dectb.wen.eq(1)
1083 comb += fast_w_dectb.data_i.eq(new_dec)
1084 sync += spr_dec.eq(new_dec) # copy into cur_state for decoder
1085 m.next = "TB_READ"
1086
1087 # initiates read of current TB
1088 with m.State("TB_READ"):
1089 comb += fast_r_dectb.addr.eq(FastRegs.TB)
1090 comb += fast_r_dectb.ren.eq(1)
1091 m.next = "TB_WRITE"
1092
1093 # waits for read TB to arrive, initiates write of current TB
1094 with m.State("TB_WRITE"):
1095 new_tb = Signal(64)
1096 comb += new_tb.eq(fast_r_dectb.data_o + 1)
1097 comb += fast_w_dectb.addr.eq(FastRegs.TB)
1098 comb += fast_w_dectb.wen.eq(1)
1099 comb += fast_w_dectb.data_i.eq(new_tb)
1100 m.next = "DEC_READ"
1101
1102 return m
1103
1104 def __iter__(self):
1105 yield from self.pc_i.ports()
1106 yield self.pc_o
1107 yield self.memerr_o
1108 yield from self.core.ports()
1109 yield from self.imem.ports()
1110 yield self.core_bigendian_i
1111 yield self.busy_o
1112
1113 def ports(self):
1114 return list(self)
1115
1116 def external_ports(self):
1117 ports = self.pc_i.ports()
1118 ports += [self.pc_o, self.memerr_o, self.core_bigendian_i, self.busy_o,
1119 ]
1120
1121 if self.jtag_en:
1122 ports += list(self.jtag.external_ports())
1123 else:
1124 # don't add DMI if JTAG is enabled
1125 ports += list(self.dbg.dmi.ports())
1126
1127 ports += list(self.imem.ibus.fields.values())
1128 ports += list(self.core.l0.cmpi.lsmem.lsi.slavebus.fields.values())
1129
1130 if self.sram4x4k:
1131 for sram in self.sram4k:
1132 ports += list(sram.bus.fields.values())
1133
1134 if self.xics:
1135 ports += list(self.xics_icp.bus.fields.values())
1136 ports += list(self.xics_ics.bus.fields.values())
1137 ports.append(self.int_level_i)
1138
1139 if self.gpio:
1140 ports += list(self.simple_gpio.bus.fields.values())
1141 ports.append(self.gpio_o)
1142
1143 return ports
1144
1145 def ports(self):
1146 return list(self)
1147
1148
1149 class TestIssuer(Elaboratable):
1150 def __init__(self, pspec):
1151 self.ti = TestIssuerInternal(pspec)
1152
1153 self.pll = DummyPLL()
1154
1155 # PLL direct clock or not
1156 self.pll_en = hasattr(pspec, "use_pll") and pspec.use_pll
1157 if self.pll_en:
1158 self.pll_18_o = Signal(reset_less=True)
1159 self.clk_sel_i = Signal(reset_less=True)
1160
1161 def elaborate(self, platform):
1162 m = Module()
1163 comb = m.d.comb
1164
1165 # TestIssuer runs at direct clock
1166 m.submodules.ti = ti = self.ti
1167 cd_int = ClockDomain("coresync")
1168
1169 if self.pll_en:
1170 # ClockSelect runs at PLL output internal clock rate
1171 m.submodules.pll = pll = self.pll
1172
1173 # add clock domains from PLL
1174 cd_pll = ClockDomain("pllclk")
1175 m.domains += cd_pll
1176
1177 # PLL clock established. has the side-effect of running clklsel
1178 # at the PLL's speed (see DomainRenamer("pllclk") above)
1179 pllclk = ClockSignal("pllclk")
1180 comb += pllclk.eq(pll.clk_pll_o)
1181
1182 # wire up external 24mhz to PLL
1183 comb += pll.clk_24_i.eq(ClockSignal())
1184
1185 # output 18 mhz PLL test signal
1186 comb += self.pll_18_o.eq(pll.pll_18_o)
1187
1188 # input to pll clock selection
1189 comb += Cat(pll.sel_a0_i, pll.sel_a1_i).eq(self.clk_sel_i)
1190
1191 # now wire up ResetSignals. don't mind them being in this domain
1192 pll_rst = ResetSignal("pllclk")
1193 comb += pll_rst.eq(ResetSignal())
1194
1195 # internal clock is set to selector clock-out. has the side-effect of
1196 # running TestIssuer at this speed (see DomainRenamer("intclk") above)
1197 intclk = ClockSignal("coresync")
1198 if self.pll_en:
1199 comb += intclk.eq(pll.clk_pll_o)
1200 else:
1201 comb += intclk.eq(ClockSignal())
1202
1203 return m
1204
1205 def ports(self):
1206 return list(self.ti.ports()) + list(self.pll.ports()) + \
1207 [ClockSignal(), ResetSignal()]
1208
1209 def external_ports(self):
1210 ports = self.ti.external_ports()
1211 ports.append(ClockSignal())
1212 ports.append(ResetSignal())
1213 if self.pll_en:
1214 ports.append(self.clk_sel_i)
1215 ports.append(self.pll_18_o)
1216 ports.append(self.pll.pll_ana_o)
1217 return ports
1218
1219
1220 if __name__ == '__main__':
1221 units = {'alu': 1, 'cr': 1, 'branch': 1, 'trap': 1, 'logical': 1,
1222 'spr': 1,
1223 'div': 1,
1224 'mul': 1,
1225 'shiftrot': 1
1226 }
1227 pspec = TestMemPspec(ldst_ifacetype='bare_wb',
1228 imem_ifacetype='bare_wb',
1229 addr_wid=48,
1230 mask_wid=8,
1231 reg_wid=64,
1232 units=units)
1233 dut = TestIssuer(pspec)
1234 vl = main(dut, ports=dut.ports(), name="test_issuer")
1235
1236 if len(sys.argv) == 1:
1237 vl = rtlil.convert(dut, ports=dut.external_ports(), name="test_issuer")
1238 with open("test_issuer.il", "w") as f:
1239 f.write(vl)