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Make the VL loop reentrant in HDL
[soc.git] / src / soc / simple / issuer.py
1 """simple core issuer
2
3 not in any way intended for production use. this runs a FSM that:
4
5 * reads the Program Counter from StateRegs
6 * reads an instruction from a fixed-size Test Memory
7 * issues it to the Simple Core
8 * waits for it to complete
9 * increments the PC
10 * does it all over again
11
12 the purpose of this module is to verify the functional correctness
13 of the Function Units in the absolute simplest and clearest possible
14 way, and to at provide something that can be further incrementally
15 improved.
16 """
17
18 from nmigen import (Elaboratable, Module, Signal, ClockSignal, ResetSignal,
19 ClockDomain, DomainRenamer, Mux, Const, Repl, Cat)
20 from nmigen.cli import rtlil
21 from nmigen.cli import main
22 import sys
23
24 from nmigen.lib.coding import PriorityEncoder
25
26 from soc.decoder.power_decoder import create_pdecode
27 from soc.decoder.power_decoder2 import PowerDecode2, SVP64PrefixDecoder
28 from soc.decoder.decode2execute1 import IssuerDecode2ToOperand
29 from soc.decoder.decode2execute1 import Data
30 from soc.experiment.testmem import TestMemory # test only for instructions
31 from soc.regfile.regfiles import StateRegs, FastRegs
32 from soc.simple.core import NonProductionCore
33 from soc.config.test.test_loadstore import TestMemPspec
34 from soc.config.ifetch import ConfigFetchUnit
35 from soc.decoder.power_enums import (MicrOp, SVP64PredInt, SVP64PredCR,
36 SVP64PredMode)
37 from soc.debug.dmi import CoreDebug, DMIInterface
38 from soc.debug.jtag import JTAG
39 from soc.config.pinouts import get_pinspecs
40 from soc.config.state import CoreState
41 from soc.interrupts.xics import XICS_ICP, XICS_ICS
42 from soc.bus.simple_gpio import SimpleGPIO
43 from soc.bus.SPBlock512W64B8W import SPBlock512W64B8W
44 from soc.clock.select import ClockSelect
45 from soc.clock.dummypll import DummyPLL
46 from soc.sv.svstate import SVSTATERec
47
48
49 from nmutil.util import rising_edge
50
51 def get_insn(f_instr_o, pc):
52 if f_instr_o.width == 32:
53 return f_instr_o
54 else:
55 # 64-bit: bit 2 of pc decides which word to select
56 return f_instr_o.word_select(pc[2], 32)
57
58 # gets state input or reads from state regfile
59 def state_get(m, state_i, name, regfile, regnum):
60 comb = m.d.comb
61 sync = m.d.sync
62 # read the PC
63 res = Signal(64, reset_less=True, name=name)
64 res_ok_delay = Signal(name="%s_ok_delay" % name)
65 sync += res_ok_delay.eq(~state_i.ok)
66 with m.If(state_i.ok):
67 # incoming override (start from pc_i)
68 comb += res.eq(state_i.data)
69 with m.Else():
70 # otherwise read StateRegs regfile for PC...
71 comb += regfile.ren.eq(1<<regnum)
72 # ... but on a 1-clock delay
73 with m.If(res_ok_delay):
74 comb += res.eq(regfile.data_o)
75 return res
76
77 def get_predint(m, mask, name):
78 """decode SVP64 predicate integer mask field to reg number and invert
79 this is identical to the equivalent function in ISACaller except that
80 it doesn't read the INT directly, it just decodes "what needs to be done"
81 i.e. which INT reg, whether it is shifted and whether it is bit-inverted.
82
83 * all1s is set to indicate that no mask is to be applied.
84 * regread indicates the GPR register number to be read
85 * invert is set to indicate that the register value is to be inverted
86 * unary indicates that the contents of the register is to be shifted 1<<r3
87 """
88 comb = m.d.comb
89 regread = Signal(5, name=name+"regread")
90 invert = Signal(name=name+"invert")
91 unary = Signal(name=name+"unary")
92 all1s = Signal(name=name+"all1s")
93 with m.Switch(mask):
94 with m.Case(SVP64PredInt.ALWAYS.value):
95 comb += all1s.eq(1) # use 0b1111 (all ones)
96 with m.Case(SVP64PredInt.R3_UNARY.value):
97 comb += regread.eq(3)
98 comb += unary.eq(1) # 1<<r3 - shift r3 (single bit)
99 with m.Case(SVP64PredInt.R3.value):
100 comb += regread.eq(3)
101 with m.Case(SVP64PredInt.R3_N.value):
102 comb += regread.eq(3)
103 comb += invert.eq(1)
104 with m.Case(SVP64PredInt.R10.value):
105 comb += regread.eq(10)
106 with m.Case(SVP64PredInt.R10_N.value):
107 comb += regread.eq(10)
108 comb += invert.eq(1)
109 with m.Case(SVP64PredInt.R30.value):
110 comb += regread.eq(30)
111 with m.Case(SVP64PredInt.R30_N.value):
112 comb += regread.eq(30)
113 comb += invert.eq(1)
114 return regread, invert, unary, all1s
115
116 def get_predcr(m, mask, name):
117 """decode SVP64 predicate CR to reg number field and invert status
118 this is identical to _get_predcr in ISACaller
119 """
120 comb = m.d.comb
121 idx = Signal(2, name=name+"idx")
122 invert = Signal(name=name+"crinvert")
123 with m.Switch(mask):
124 with m.Case(SVP64PredCR.LT.value):
125 comb += idx.eq(0)
126 comb += invert.eq(1)
127 with m.Case(SVP64PredCR.GE.value):
128 comb += idx.eq(0)
129 comb += invert.eq(0)
130 with m.Case(SVP64PredCR.GT.value):
131 comb += idx.eq(1)
132 comb += invert.eq(1)
133 with m.Case(SVP64PredCR.LE.value):
134 comb += idx.eq(1)
135 comb += invert.eq(0)
136 with m.Case(SVP64PredCR.EQ.value):
137 comb += idx.eq(2)
138 comb += invert.eq(1)
139 with m.Case(SVP64PredCR.NE.value):
140 comb += idx.eq(1)
141 comb += invert.eq(0)
142 with m.Case(SVP64PredCR.SO.value):
143 comb += idx.eq(3)
144 comb += invert.eq(1)
145 with m.Case(SVP64PredCR.NS.value):
146 comb += idx.eq(3)
147 comb += invert.eq(0)
148 return idx, invert
149
150
151 class TestIssuerInternal(Elaboratable):
152 """TestIssuer - reads instructions from TestMemory and issues them
153
154 efficiency and speed is not the main goal here: functional correctness
155 and code clarity is. optimisations (which almost 100% interfere with
156 easy understanding) come later.
157 """
158 def __init__(self, pspec):
159
160 # test is SVP64 is to be enabled
161 self.svp64_en = hasattr(pspec, "svp64") and (pspec.svp64 == True)
162
163 # and if regfiles are reduced
164 self.regreduce_en = (hasattr(pspec, "regreduce") and
165 (pspec.regreduce == True))
166
167 # JTAG interface. add this right at the start because if it's
168 # added it *modifies* the pspec, by adding enable/disable signals
169 # for parts of the rest of the core
170 self.jtag_en = hasattr(pspec, "debug") and pspec.debug == 'jtag'
171 if self.jtag_en:
172 # XXX MUST keep this up-to-date with litex, and
173 # soc-cocotb-sim, and err.. all needs sorting out, argh
174 subset = ['uart',
175 'mtwi',
176 'eint', 'gpio', 'mspi0',
177 # 'mspi1', - disabled for now
178 # 'pwm', 'sd0', - disabled for now
179 'sdr']
180 self.jtag = JTAG(get_pinspecs(subset=subset))
181 # add signals to pspec to enable/disable icache and dcache
182 # (or data and intstruction wishbone if icache/dcache not included)
183 # https://bugs.libre-soc.org/show_bug.cgi?id=520
184 # TODO: do we actually care if these are not domain-synchronised?
185 # honestly probably not.
186 pspec.wb_icache_en = self.jtag.wb_icache_en
187 pspec.wb_dcache_en = self.jtag.wb_dcache_en
188 self.wb_sram_en = self.jtag.wb_sram_en
189 else:
190 self.wb_sram_en = Const(1)
191
192 # add 4k sram blocks?
193 self.sram4x4k = (hasattr(pspec, "sram4x4kblock") and
194 pspec.sram4x4kblock == True)
195 if self.sram4x4k:
196 self.sram4k = []
197 for i in range(4):
198 self.sram4k.append(SPBlock512W64B8W(name="sram4k_%d" % i,
199 features={'err'}))
200
201 # add interrupt controller?
202 self.xics = hasattr(pspec, "xics") and pspec.xics == True
203 if self.xics:
204 self.xics_icp = XICS_ICP()
205 self.xics_ics = XICS_ICS()
206 self.int_level_i = self.xics_ics.int_level_i
207
208 # add GPIO peripheral?
209 self.gpio = hasattr(pspec, "gpio") and pspec.gpio == True
210 if self.gpio:
211 self.simple_gpio = SimpleGPIO()
212 self.gpio_o = self.simple_gpio.gpio_o
213
214 # main instruction core. suitable for prototyping / demo only
215 self.core = core = NonProductionCore(pspec)
216
217 # instruction decoder. goes into Trap Record
218 pdecode = create_pdecode()
219 self.cur_state = CoreState("cur") # current state (MSR/PC/SVSTATE)
220 self.pdecode2 = PowerDecode2(pdecode, state=self.cur_state,
221 opkls=IssuerDecode2ToOperand,
222 svp64_en=self.svp64_en,
223 regreduce_en=self.regreduce_en)
224 if self.svp64_en:
225 self.svp64 = SVP64PrefixDecoder() # for decoding SVP64 prefix
226
227 # Test Instruction memory
228 self.imem = ConfigFetchUnit(pspec).fu
229
230 # DMI interface
231 self.dbg = CoreDebug()
232
233 # instruction go/monitor
234 self.pc_o = Signal(64, reset_less=True)
235 self.pc_i = Data(64, "pc_i") # set "ok" to indicate "please change me"
236 self.svstate_i = Data(32, "svstate_i") # ditto
237 self.core_bigendian_i = Signal() # TODO: set based on MSR.LE
238 self.busy_o = Signal(reset_less=True)
239 self.memerr_o = Signal(reset_less=True)
240
241 # STATE regfile read /write ports for PC, MSR, SVSTATE
242 staterf = self.core.regs.rf['state']
243 self.state_r_pc = staterf.r_ports['cia'] # PC rd
244 self.state_w_pc = staterf.w_ports['d_wr1'] # PC wr
245 self.state_r_msr = staterf.r_ports['msr'] # MSR rd
246 self.state_r_sv = staterf.r_ports['sv'] # SVSTATE rd
247 self.state_w_sv = staterf.w_ports['sv'] # SVSTATE wr
248
249 # DMI interface access
250 intrf = self.core.regs.rf['int']
251 crrf = self.core.regs.rf['cr']
252 xerrf = self.core.regs.rf['xer']
253 self.int_r = intrf.r_ports['dmi'] # INT read
254 self.cr_r = crrf.r_ports['full_cr_dbg'] # CR read
255 self.xer_r = xerrf.r_ports['full_xer'] # XER read
256
257 if self.svp64_en:
258 # for predication
259 self.int_pred = intrf.r_ports['pred'] # INT predicate read
260 self.cr_pred = crrf.r_ports['cr_pred'] # CR predicate read
261
262 # hack method of keeping an eye on whether branch/trap set the PC
263 self.state_nia = self.core.regs.rf['state'].w_ports['nia']
264 self.state_nia.wen.name = 'state_nia_wen'
265
266 # pulse to synchronize the simulator at instruction end
267 self.insn_done = Signal()
268
269 if self.svp64_en:
270 # store copies of predicate masks
271 self.srcmask = Signal(64)
272 self.dstmask = Signal(64)
273
274 def fetch_fsm(self, m, core, pc, svstate, nia, is_svp64_mode,
275 fetch_pc_ready_o, fetch_pc_valid_i,
276 fetch_insn_valid_o, fetch_insn_ready_i):
277 """fetch FSM
278
279 this FSM performs fetch of raw instruction data, partial-decodes
280 it 32-bit at a time to detect SVP64 prefixes, and will optionally
281 read a 2nd 32-bit quantity if that occurs.
282 """
283 comb = m.d.comb
284 sync = m.d.sync
285 pdecode2 = self.pdecode2
286 cur_state = self.cur_state
287 dec_opcode_i = pdecode2.dec.raw_opcode_in # raw opcode
288
289 msr_read = Signal(reset=1)
290
291 with m.FSM(name='fetch_fsm'):
292
293 # waiting (zzz)
294 with m.State("IDLE"):
295 comb += fetch_pc_ready_o.eq(1)
296 with m.If(fetch_pc_valid_i):
297 # instruction allowed to go: start by reading the PC
298 # capture the PC and also drop it into Insn Memory
299 # we have joined a pair of combinatorial memory
300 # lookups together. this is Generally Bad.
301 comb += self.imem.a_pc_i.eq(pc)
302 comb += self.imem.a_valid_i.eq(1)
303 comb += self.imem.f_valid_i.eq(1)
304 sync += cur_state.pc.eq(pc)
305 sync += cur_state.svstate.eq(svstate) # and svstate
306
307 # initiate read of MSR. arrives one clock later
308 comb += self.state_r_msr.ren.eq(1 << StateRegs.MSR)
309 sync += msr_read.eq(0)
310
311 m.next = "INSN_READ" # move to "wait for bus" phase
312
313 # dummy pause to find out why simulation is not keeping up
314 with m.State("INSN_READ"):
315 # one cycle later, msr/sv read arrives. valid only once.
316 with m.If(~msr_read):
317 sync += msr_read.eq(1) # yeah don't read it again
318 sync += cur_state.msr.eq(self.state_r_msr.data_o)
319 with m.If(self.imem.f_busy_o): # zzz...
320 # busy: stay in wait-read
321 comb += self.imem.a_valid_i.eq(1)
322 comb += self.imem.f_valid_i.eq(1)
323 with m.Else():
324 # not busy: instruction fetched
325 insn = get_insn(self.imem.f_instr_o, cur_state.pc)
326 if self.svp64_en:
327 svp64 = self.svp64
328 # decode the SVP64 prefix, if any
329 comb += svp64.raw_opcode_in.eq(insn)
330 comb += svp64.bigendian.eq(self.core_bigendian_i)
331 # pass the decoded prefix (if any) to PowerDecoder2
332 sync += pdecode2.sv_rm.eq(svp64.svp64_rm)
333 # remember whether this is a prefixed instruction, so
334 # the FSM can readily loop when VL==0
335 sync += is_svp64_mode.eq(svp64.is_svp64_mode)
336 # calculate the address of the following instruction
337 insn_size = Mux(svp64.is_svp64_mode, 8, 4)
338 sync += nia.eq(cur_state.pc + insn_size)
339 with m.If(~svp64.is_svp64_mode):
340 # with no prefix, store the instruction
341 # and hand it directly to the next FSM
342 sync += dec_opcode_i.eq(insn)
343 m.next = "INSN_READY"
344 with m.Else():
345 # fetch the rest of the instruction from memory
346 comb += self.imem.a_pc_i.eq(cur_state.pc + 4)
347 comb += self.imem.a_valid_i.eq(1)
348 comb += self.imem.f_valid_i.eq(1)
349 m.next = "INSN_READ2"
350 else:
351 # not SVP64 - 32-bit only
352 sync += nia.eq(cur_state.pc + 4)
353 sync += dec_opcode_i.eq(insn)
354 m.next = "INSN_READY"
355
356 with m.State("INSN_READ2"):
357 with m.If(self.imem.f_busy_o): # zzz...
358 # busy: stay in wait-read
359 comb += self.imem.a_valid_i.eq(1)
360 comb += self.imem.f_valid_i.eq(1)
361 with m.Else():
362 # not busy: instruction fetched
363 insn = get_insn(self.imem.f_instr_o, cur_state.pc+4)
364 sync += dec_opcode_i.eq(insn)
365 m.next = "INSN_READY"
366 # TODO: probably can start looking at pdecode2.rm_dec
367 # here or maybe even in INSN_READ state, if svp64_mode
368 # detected, in order to trigger - and wait for - the
369 # predicate reading.
370 if self.svp64_en:
371 pmode = pdecode2.rm_dec.predmode
372 """
373 if pmode != SVP64PredMode.ALWAYS.value:
374 fire predicate loading FSM and wait before
375 moving to INSN_READY
376 else:
377 sync += self.srcmask.eq(-1) # set to all 1s
378 sync += self.dstmask.eq(-1) # set to all 1s
379 m.next = "INSN_READY"
380 """
381
382 with m.State("INSN_READY"):
383 # hand over the instruction, to be decoded
384 comb += fetch_insn_valid_o.eq(1)
385 with m.If(fetch_insn_ready_i):
386 m.next = "IDLE"
387
388 def fetch_predicate_fsm(self, m,
389 pred_insn_valid_i, pred_insn_ready_o,
390 pred_mask_valid_o, pred_mask_ready_i):
391 """fetch_predicate_fsm - obtains (constructs in the case of CR)
392 src/dest predicate masks
393
394 https://bugs.libre-soc.org/show_bug.cgi?id=617
395 the predicates can be read here, by using IntRegs r_ports['pred']
396 or CRRegs r_ports['pred']. in the case of CRs it will have to
397 be done through multiple reads, extracting one relevant at a time.
398 later, a faster way would be to use the 32-bit-wide CR port but
399 this is more complex decoding, here. equivalent code used in
400 ISACaller is "from soc.decoder.isa.caller import get_predcr"
401
402 note: this ENTIRE FSM is not to be called when svp64 is disabled
403 """
404 comb = m.d.comb
405 sync = m.d.sync
406 pdecode2 = self.pdecode2
407 rm_dec = pdecode2.rm_dec # SVP64RMModeDecode
408 predmode = rm_dec.predmode
409 srcpred, dstpred = rm_dec.srcpred, rm_dec.dstpred
410 cr_pred, int_pred = self.cr_pred, self.int_pred # read regfiles
411 # get src/dst step, so we can skip already used mask bits
412 cur_state = self.cur_state
413 srcstep = cur_state.svstate.srcstep
414 dststep = cur_state.svstate.dststep
415
416 # elif predmode == CR:
417 # CR-src sidx, sinvert = get_predcr(m, srcpred)
418 # CR-dst didx, dinvert = get_predcr(m, dstpred)
419 # TODO read CR-src and CR-dst into self.srcmask+dstmask with loop
420 # has to cope with first one then the other
421 # for cr_idx = FSM-state-loop(0..VL-1):
422 # FSM-state-trigger-CR-read:
423 # cr_ren = (1<<7-(cr_idx+SVP64CROffs.CRPred))
424 # comb += cr_pred.ren.eq(cr_ren)
425 # FSM-state-1-clock-later-actual-Read:
426 # cr_field = Signal(4)
427 # cr_bit = Signal(1)
428 # # read the CR field, select the appropriate bit
429 # comb += cr_field.eq(cr_pred.data_o)
430 # comb += cr_bit.eq(cr_field.bit_select(idx)))
431 # # just like in branch BO tests
432 # comd += self.srcmask[cr_idx].eq(inv ^ cr_bit)
433
434 # decode predicates
435 sregread, sinvert, sunary, sall1s = get_predint(m, srcpred, 's')
436 dregread, dinvert, dunary, dall1s = get_predint(m, dstpred, 'd')
437 sidx, scrinvert = get_predcr(m, srcpred, 's')
438 didx, dcrinvert = get_predcr(m, dstpred, 'd')
439
440 with m.FSM(name="fetch_predicate"):
441
442 with m.State("FETCH_PRED_IDLE"):
443 comb += pred_insn_ready_o.eq(1)
444 with m.If(pred_insn_valid_i):
445 with m.If(predmode == SVP64PredMode.INT):
446 # skip fetching destination mask register, when zero
447 with m.If(dall1s):
448 sync += self.dstmask.eq(-1)
449 # directly go to fetch source mask register
450 # guaranteed not to be zero (otherwise predmode
451 # would be SVP64PredMode.ALWAYS, not INT)
452 comb += int_pred.addr.eq(sregread)
453 comb += int_pred.ren.eq(1)
454 m.next = "INT_SRC_READ"
455 # fetch destination predicate register
456 with m.Else():
457 comb += int_pred.addr.eq(dregread)
458 comb += int_pred.ren.eq(1)
459 m.next = "INT_DST_READ"
460 with m.Else():
461 sync += self.srcmask.eq(-1)
462 sync += self.dstmask.eq(-1)
463 m.next = "FETCH_PRED_DONE"
464
465 with m.State("INT_DST_READ"):
466 # store destination mask
467 inv = Repl(dinvert, 64)
468 new_dstmask = Signal(64)
469 # invert mask if requested
470 comb += new_dstmask.eq(self.int_pred.data_o ^ inv)
471 # shift-out already used mask bits
472 sync += self.dstmask.eq(new_dstmask >> dststep)
473 # skip fetching source mask register, when zero
474 with m.If(sall1s):
475 sync += self.srcmask.eq(-1)
476 m.next = "FETCH_PRED_DONE"
477 # fetch source predicate register
478 with m.Else():
479 comb += int_pred.addr.eq(sregread)
480 comb += int_pred.ren.eq(1)
481 m.next = "INT_SRC_READ"
482
483 with m.State("INT_SRC_READ"):
484 # store source mask
485 inv = Repl(sinvert, 64)
486 new_srcmask = Signal(64)
487 # invert mask if requested
488 comb += new_srcmask.eq(self.int_pred.data_o ^ inv)
489 # shift-out already used mask bits
490 sync += self.srcmask.eq(new_srcmask >> srcstep)
491 m.next = "FETCH_PRED_DONE"
492
493 with m.State("FETCH_PRED_DONE"):
494 comb += pred_mask_valid_o.eq(1)
495 with m.If(pred_mask_ready_i):
496 m.next = "FETCH_PRED_IDLE"
497
498 def issue_fsm(self, m, core, pc_changed, sv_changed, nia,
499 dbg, core_rst, is_svp64_mode,
500 fetch_pc_ready_o, fetch_pc_valid_i,
501 fetch_insn_valid_o, fetch_insn_ready_i,
502 pred_insn_valid_i, pred_insn_ready_o,
503 pred_mask_valid_o, pred_mask_ready_i,
504 exec_insn_valid_i, exec_insn_ready_o,
505 exec_pc_valid_o, exec_pc_ready_i):
506 """issue FSM
507
508 decode / issue FSM. this interacts with the "fetch" FSM
509 through fetch_insn_ready/valid (incoming) and fetch_pc_ready/valid
510 (outgoing). also interacts with the "execute" FSM
511 through exec_insn_ready/valid (outgoing) and exec_pc_ready/valid
512 (incoming).
513 SVP64 RM prefixes have already been set up by the
514 "fetch" phase, so execute is fairly straightforward.
515 """
516
517 comb = m.d.comb
518 sync = m.d.sync
519 pdecode2 = self.pdecode2
520 cur_state = self.cur_state
521
522 # temporaries
523 dec_opcode_i = pdecode2.dec.raw_opcode_in # raw opcode
524
525 # for updating svstate (things like srcstep etc.)
526 update_svstate = Signal() # set this (below) if updating
527 new_svstate = SVSTATERec("new_svstate")
528 comb += new_svstate.eq(cur_state.svstate)
529
530 # precalculate srcstep+1 and dststep+1
531 cur_srcstep = cur_state.svstate.srcstep
532 cur_dststep = cur_state.svstate.dststep
533 next_srcstep = Signal.like(cur_srcstep)
534 next_dststep = Signal.like(cur_dststep)
535 comb += next_srcstep.eq(cur_state.svstate.srcstep+1)
536 comb += next_dststep.eq(cur_state.svstate.dststep+1)
537
538 with m.FSM(name="issue_fsm"):
539
540 # sync with the "fetch" phase which is reading the instruction
541 # at this point, there is no instruction running, that
542 # could inadvertently update the PC.
543 with m.State("ISSUE_START"):
544 # wait on "core stop" release, before next fetch
545 # need to do this here, in case we are in a VL==0 loop
546 with m.If(~dbg.core_stop_o & ~core_rst):
547 comb += fetch_pc_valid_i.eq(1) # tell fetch to start
548 with m.If(fetch_pc_ready_o): # fetch acknowledged us
549 m.next = "INSN_WAIT"
550 with m.Else():
551 # tell core it's stopped, and acknowledge debug handshake
552 comb += core.core_stopped_i.eq(1)
553 comb += dbg.core_stopped_i.eq(1)
554 # while stopped, allow updating the PC and SVSTATE
555 with m.If(self.pc_i.ok):
556 comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
557 comb += self.state_w_pc.data_i.eq(self.pc_i.data)
558 sync += pc_changed.eq(1)
559 with m.If(self.svstate_i.ok):
560 comb += new_svstate.eq(self.svstate_i.data)
561 comb += update_svstate.eq(1)
562 sync += sv_changed.eq(1)
563
564 # wait for an instruction to arrive from Fetch
565 with m.State("INSN_WAIT"):
566 comb += fetch_insn_ready_i.eq(1)
567 with m.If(fetch_insn_valid_o):
568 # loop into ISSUE_START if it's a SVP64 instruction
569 # and VL == 0. this because VL==0 is a for-loop
570 # from 0 to 0 i.e. always, always a NOP.
571 cur_vl = cur_state.svstate.vl
572 with m.If(is_svp64_mode & (cur_vl == 0)):
573 # update the PC before fetching the next instruction
574 # since we are in a VL==0 loop, no instruction was
575 # executed that we could be overwriting
576 comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
577 comb += self.state_w_pc.data_i.eq(nia)
578 comb += self.insn_done.eq(1)
579 m.next = "ISSUE_START"
580 with m.Else():
581 if self.svp64_en:
582 m.next = "PRED_START" # start fetching predicate
583 else:
584 m.next = "DECODE_SV" # skip predication
585
586 with m.State("PRED_START"):
587 comb += pred_insn_valid_i.eq(1) # tell fetch_pred to start
588 with m.If(pred_insn_ready_o): # fetch_pred acknowledged us
589 m.next = "MASK_WAIT"
590
591 with m.State("MASK_WAIT"):
592 comb += pred_mask_ready_i.eq(1) # ready to receive the masks
593 with m.If(pred_mask_valid_o): # predication masks are ready
594 m.next = "PRED_SKIP"
595
596 # skip zeros in predicate
597 with m.State("PRED_SKIP"):
598 with m.If(~is_svp64_mode):
599 m.next = "DECODE_SV" # nothing to do
600 with m.Else():
601 if self.svp64_en:
602 pred_src_zero = pdecode2.rm_dec.pred_sz
603 pred_dst_zero = pdecode2.rm_dec.pred_dz
604
605 # new srcstep, after skipping zeros
606 skip_srcstep = Signal.like(cur_srcstep)
607 # value to be added to the current srcstep
608 src_delta = Signal.like(cur_srcstep)
609 # add leading zeros to srcstep, if not in zero mode
610 with m.If(~pred_src_zero):
611 # priority encoder (count leading zeros)
612 # append guard bit, in case the mask is all zeros
613 pri_enc_src = PriorityEncoder(65)
614 m.submodules.pri_enc_src = pri_enc_src
615 comb += pri_enc_src.i.eq(Cat(self.srcmask,
616 Const(1, 1)))
617 comb += src_delta.eq(pri_enc_src.o)
618 # apply delta to srcstep
619 comb += skip_srcstep.eq(cur_srcstep + src_delta)
620 # shift-out all leading zeros from the mask
621 # plus the leading "one" bit
622 # TODO count leading zeros and shift-out the zero
623 # bits, in the same step, in hardware
624 sync += self.srcmask.eq(self.srcmask >> (src_delta+1))
625
626 # same as above, but for dststep
627 skip_dststep = Signal.like(cur_dststep)
628 dst_delta = Signal.like(cur_dststep)
629 with m.If(~pred_dst_zero):
630 pri_enc_dst = PriorityEncoder(65)
631 m.submodules.pri_enc_dst = pri_enc_dst
632 comb += pri_enc_dst.i.eq(Cat(self.dstmask,
633 Const(1, 1)))
634 comb += dst_delta.eq(pri_enc_dst.o)
635 comb += skip_dststep.eq(cur_dststep + dst_delta)
636 sync += self.dstmask.eq(self.dstmask >> (dst_delta+1))
637
638 # TODO: initialize mask[VL]=1 to avoid passing past VL
639 with m.If((skip_srcstep >= cur_vl) |
640 (skip_dststep >= cur_vl)):
641 # end of VL loop. Update PC and reset src/dst step
642 comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
643 comb += self.state_w_pc.data_i.eq(nia)
644 comb += new_svstate.srcstep.eq(0)
645 comb += new_svstate.dststep.eq(0)
646 comb += update_svstate.eq(1)
647 # synchronize with the simulator
648 comb += self.insn_done.eq(1)
649 # go back to Issue
650 m.next = "ISSUE_START"
651 with m.Else():
652 # update new src/dst step
653 comb += new_svstate.srcstep.eq(skip_srcstep)
654 comb += new_svstate.dststep.eq(skip_dststep)
655 comb += update_svstate.eq(1)
656 # proceed to Decode
657 m.next = "DECODE_SV"
658
659 # after src/dst step have been updated, we are ready
660 # to decode the instruction
661 with m.State("DECODE_SV"):
662 # decode the instruction
663 sync += core.e.eq(pdecode2.e)
664 sync += core.state.eq(cur_state)
665 sync += core.raw_insn_i.eq(dec_opcode_i)
666 sync += core.bigendian_i.eq(self.core_bigendian_i)
667 # set RA_OR_ZERO detection in satellite decoders
668 sync += core.sv_a_nz.eq(pdecode2.sv_a_nz)
669 m.next = "INSN_EXECUTE" # move to "execute"
670
671 # handshake with execution FSM, move to "wait" once acknowledged
672 with m.State("INSN_EXECUTE"):
673 comb += exec_insn_valid_i.eq(1) # trigger execute
674 with m.If(exec_insn_ready_o): # execute acknowledged us
675 m.next = "EXECUTE_WAIT"
676
677 with m.State("EXECUTE_WAIT"):
678 # wait on "core stop" release, at instruction end
679 # need to do this here, in case we are in a VL>1 loop
680 with m.If(~dbg.core_stop_o & ~core_rst):
681 comb += exec_pc_ready_i.eq(1)
682 with m.If(exec_pc_valid_o):
683
684 # was this the last loop iteration?
685 is_last = Signal()
686 cur_vl = cur_state.svstate.vl
687 comb += is_last.eq(next_srcstep == cur_vl)
688
689 # if either PC or SVSTATE were changed by the previous
690 # instruction, go directly back to Fetch, without
691 # updating either PC or SVSTATE
692 with m.If(pc_changed | sv_changed):
693 m.next = "ISSUE_START"
694
695 # also return to Fetch, when no output was a vector
696 # (regardless of SRCSTEP and VL), or when the last
697 # instruction was really the last one of the VL loop
698 with m.Elif((~pdecode2.loop_continue) | is_last):
699 # before going back to fetch, update the PC state
700 # register with the NIA.
701 # ok here we are not reading the branch unit.
702 # TODO: this just blithely overwrites whatever
703 # pipeline updated the PC
704 comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
705 comb += self.state_w_pc.data_i.eq(nia)
706 # reset SRCSTEP before returning to Fetch
707 if self.svp64_en:
708 with m.If(pdecode2.loop_continue):
709 comb += new_svstate.srcstep.eq(0)
710 comb += new_svstate.dststep.eq(0)
711 comb += update_svstate.eq(1)
712 else:
713 comb += new_svstate.srcstep.eq(0)
714 comb += new_svstate.dststep.eq(0)
715 comb += update_svstate.eq(1)
716 m.next = "ISSUE_START"
717
718 # returning to Execute? then, first update SRCSTEP
719 with m.Else():
720 comb += new_svstate.srcstep.eq(next_srcstep)
721 comb += new_svstate.dststep.eq(next_dststep)
722 comb += update_svstate.eq(1)
723 # return to mask skip loop
724 m.next = "PRED_SKIP"
725
726 with m.Else():
727 comb += core.core_stopped_i.eq(1)
728 comb += dbg.core_stopped_i.eq(1)
729 # while stopped, allow updating the PC and SVSTATE
730 with m.If(self.pc_i.ok):
731 comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
732 comb += self.state_w_pc.data_i.eq(self.pc_i.data)
733 sync += pc_changed.eq(1)
734 with m.If(self.svstate_i.ok):
735 comb += new_svstate.eq(self.svstate_i.data)
736 comb += update_svstate.eq(1)
737 sync += sv_changed.eq(1)
738
739 # check if svstate needs updating: if so, write it to State Regfile
740 with m.If(update_svstate):
741 comb += self.state_w_sv.wen.eq(1<<StateRegs.SVSTATE)
742 comb += self.state_w_sv.data_i.eq(new_svstate)
743 sync += cur_state.svstate.eq(new_svstate) # for next clock
744
745 def execute_fsm(self, m, core, pc_changed, sv_changed,
746 exec_insn_valid_i, exec_insn_ready_o,
747 exec_pc_valid_o, exec_pc_ready_i):
748 """execute FSM
749
750 execute FSM. this interacts with the "issue" FSM
751 through exec_insn_ready/valid (incoming) and exec_pc_ready/valid
752 (outgoing). SVP64 RM prefixes have already been set up by the
753 "issue" phase, so execute is fairly straightforward.
754 """
755
756 comb = m.d.comb
757 sync = m.d.sync
758 pdecode2 = self.pdecode2
759
760 # temporaries
761 core_busy_o = core.busy_o # core is busy
762 core_ivalid_i = core.ivalid_i # instruction is valid
763 core_issue_i = core.issue_i # instruction is issued
764 insn_type = core.e.do.insn_type # instruction MicroOp type
765
766 with m.FSM(name="exec_fsm"):
767
768 # waiting for instruction bus (stays there until not busy)
769 with m.State("INSN_START"):
770 comb += exec_insn_ready_o.eq(1)
771 with m.If(exec_insn_valid_i):
772 comb += core_ivalid_i.eq(1) # instruction is valid
773 comb += core_issue_i.eq(1) # and issued
774 sync += sv_changed.eq(0)
775 sync += pc_changed.eq(0)
776 m.next = "INSN_ACTIVE" # move to "wait completion"
777
778 # instruction started: must wait till it finishes
779 with m.State("INSN_ACTIVE"):
780 with m.If(insn_type != MicrOp.OP_NOP):
781 comb += core_ivalid_i.eq(1) # instruction is valid
782 # note changes to PC and SVSTATE
783 with m.If(self.state_nia.wen & (1<<StateRegs.SVSTATE)):
784 sync += sv_changed.eq(1)
785 with m.If(self.state_nia.wen & (1<<StateRegs.PC)):
786 sync += pc_changed.eq(1)
787 with m.If(~core_busy_o): # instruction done!
788 comb += exec_pc_valid_o.eq(1)
789 with m.If(exec_pc_ready_i):
790 comb += self.insn_done.eq(1)
791 m.next = "INSN_START" # back to fetch
792
793 def setup_peripherals(self, m):
794 comb, sync = m.d.comb, m.d.sync
795
796 m.submodules.core = core = DomainRenamer("coresync")(self.core)
797 m.submodules.imem = imem = self.imem
798 m.submodules.dbg = dbg = self.dbg
799 if self.jtag_en:
800 m.submodules.jtag = jtag = self.jtag
801 # TODO: UART2GDB mux, here, from external pin
802 # see https://bugs.libre-soc.org/show_bug.cgi?id=499
803 sync += dbg.dmi.connect_to(jtag.dmi)
804
805 cur_state = self.cur_state
806
807 # 4x 4k SRAM blocks. these simply "exist", they get routed in litex
808 if self.sram4x4k:
809 for i, sram in enumerate(self.sram4k):
810 m.submodules["sram4k_%d" % i] = sram
811 comb += sram.enable.eq(self.wb_sram_en)
812
813 # XICS interrupt handler
814 if self.xics:
815 m.submodules.xics_icp = icp = self.xics_icp
816 m.submodules.xics_ics = ics = self.xics_ics
817 comb += icp.ics_i.eq(ics.icp_o) # connect ICS to ICP
818 sync += cur_state.eint.eq(icp.core_irq_o) # connect ICP to core
819
820 # GPIO test peripheral
821 if self.gpio:
822 m.submodules.simple_gpio = simple_gpio = self.simple_gpio
823
824 # connect one GPIO output to ICS bit 15 (like in microwatt soc.vhdl)
825 # XXX causes litex ECP5 test to get wrong idea about input and output
826 # (but works with verilator sim *sigh*)
827 #if self.gpio and self.xics:
828 # comb += self.int_level_i[15].eq(simple_gpio.gpio_o[0])
829
830 # instruction decoder
831 pdecode = create_pdecode()
832 m.submodules.dec2 = pdecode2 = self.pdecode2
833 if self.svp64_en:
834 m.submodules.svp64 = svp64 = self.svp64
835
836 # convenience
837 dmi, d_reg, d_cr, d_xer, = dbg.dmi, dbg.d_gpr, dbg.d_cr, dbg.d_xer
838 intrf = self.core.regs.rf['int']
839
840 # clock delay power-on reset
841 cd_por = ClockDomain(reset_less=True)
842 cd_sync = ClockDomain()
843 core_sync = ClockDomain("coresync")
844 m.domains += cd_por, cd_sync, core_sync
845
846 ti_rst = Signal(reset_less=True)
847 delay = Signal(range(4), reset=3)
848 with m.If(delay != 0):
849 m.d.por += delay.eq(delay - 1)
850 comb += cd_por.clk.eq(ClockSignal())
851
852 # power-on reset delay
853 core_rst = ResetSignal("coresync")
854 comb += ti_rst.eq(delay != 0 | dbg.core_rst_o | ResetSignal())
855 comb += core_rst.eq(ti_rst)
856
857 # busy/halted signals from core
858 comb += self.busy_o.eq(core.busy_o)
859 comb += pdecode2.dec.bigendian.eq(self.core_bigendian_i)
860
861 # temporary hack: says "go" immediately for both address gen and ST
862 l0 = core.l0
863 ldst = core.fus.fus['ldst0']
864 st_go_edge = rising_edge(m, ldst.st.rel_o)
865 m.d.comb += ldst.ad.go_i.eq(ldst.ad.rel_o) # link addr-go direct to rel
866 m.d.comb += ldst.st.go_i.eq(st_go_edge) # link store-go to rising rel
867
868 return core_rst
869
870 def elaborate(self, platform):
871 m = Module()
872 # convenience
873 comb, sync = m.d.comb, m.d.sync
874 cur_state = self.cur_state
875 pdecode2 = self.pdecode2
876 dbg = self.dbg
877 core = self.core
878
879 # set up peripherals and core
880 core_rst = self.setup_peripherals(m)
881
882 # PC and instruction from I-Memory
883 comb += self.pc_o.eq(cur_state.pc)
884 pc_changed = Signal() # note write to PC
885 sv_changed = Signal() # note write to SVSTATE
886
887 # read state either from incoming override or from regfile
888 # TODO: really should be doing MSR in the same way
889 pc = state_get(m, self.pc_i, "pc", # read PC
890 self.state_r_pc, StateRegs.PC)
891 svstate = state_get(m, self.svstate_i, "svstate", # read SVSTATE
892 self.state_r_sv, StateRegs.SVSTATE)
893
894 # don't write pc every cycle
895 comb += self.state_w_pc.wen.eq(0)
896 comb += self.state_w_pc.data_i.eq(0)
897
898 # don't read msr every cycle
899 comb += self.state_r_msr.ren.eq(0)
900
901 # address of the next instruction, in the absence of a branch
902 # depends on the instruction size
903 nia = Signal(64, reset_less=True)
904
905 # connect up debug signals
906 # TODO comb += core.icache_rst_i.eq(dbg.icache_rst_o)
907 comb += dbg.terminate_i.eq(core.core_terminate_o)
908 comb += dbg.state.pc.eq(pc)
909 comb += dbg.state.svstate.eq(svstate)
910 comb += dbg.state.msr.eq(cur_state.msr)
911
912 # pass the prefix mode from Fetch to Issue, so the latter can loop
913 # on VL==0
914 is_svp64_mode = Signal()
915
916 # there are *THREE* FSMs, fetch (32/64-bit) issue, decode/execute.
917 # these are the handshake signals between fetch and decode/execute
918
919 # fetch FSM can run as soon as the PC is valid
920 fetch_pc_valid_i = Signal() # Execute tells Fetch "start next read"
921 fetch_pc_ready_o = Signal() # Fetch Tells SVSTATE "proceed"
922
923 # fetch FSM hands over the instruction to be decoded / issued
924 fetch_insn_valid_o = Signal()
925 fetch_insn_ready_i = Signal()
926
927 # predicate fetch FSM decodes and fetches the predicate
928 pred_insn_valid_i = Signal()
929 pred_insn_ready_o = Signal()
930
931 # predicate fetch FSM delivers the masks
932 pred_mask_valid_o = Signal()
933 pred_mask_ready_i = Signal()
934
935 # issue FSM delivers the instruction to the be executed
936 exec_insn_valid_i = Signal()
937 exec_insn_ready_o = Signal()
938
939 # execute FSM, hands over the PC/SVSTATE back to the issue FSM
940 exec_pc_valid_o = Signal()
941 exec_pc_ready_i = Signal()
942
943 # the FSMs here are perhaps unusual in that they detect conditions
944 # then "hold" information, combinatorially, for the core
945 # (as opposed to using sync - which would be on a clock's delay)
946 # this includes the actual opcode, valid flags and so on.
947
948 # Fetch, then predicate fetch, then Issue, then Execute.
949 # Issue is where the VL for-loop # lives. the ready/valid
950 # signalling is used to communicate between the four.
951
952 self.fetch_fsm(m, core, pc, svstate, nia, is_svp64_mode,
953 fetch_pc_ready_o, fetch_pc_valid_i,
954 fetch_insn_valid_o, fetch_insn_ready_i)
955
956 self.issue_fsm(m, core, pc_changed, sv_changed, nia,
957 dbg, core_rst, is_svp64_mode,
958 fetch_pc_ready_o, fetch_pc_valid_i,
959 fetch_insn_valid_o, fetch_insn_ready_i,
960 pred_insn_valid_i, pred_insn_ready_o,
961 pred_mask_valid_o, pred_mask_ready_i,
962 exec_insn_valid_i, exec_insn_ready_o,
963 exec_pc_valid_o, exec_pc_ready_i)
964
965 if self.svp64_en:
966 self.fetch_predicate_fsm(m,
967 pred_insn_valid_i, pred_insn_ready_o,
968 pred_mask_valid_o, pred_mask_ready_i)
969
970 self.execute_fsm(m, core, pc_changed, sv_changed,
971 exec_insn_valid_i, exec_insn_ready_o,
972 exec_pc_valid_o, exec_pc_ready_i)
973
974 # this bit doesn't have to be in the FSM: connect up to read
975 # regfiles on demand from DMI
976 self.do_dmi(m, dbg)
977
978 # DEC and TB inc/dec FSM. copy of DEC is put into CoreState,
979 # (which uses that in PowerDecoder2 to raise 0x900 exception)
980 self.tb_dec_fsm(m, cur_state.dec)
981
982 return m
983
984 def do_dmi(self, m, dbg):
985 """deals with DMI debug requests
986
987 currently only provides read requests for the INT regfile, CR and XER
988 it will later also deal with *writing* to these regfiles.
989 """
990 comb = m.d.comb
991 sync = m.d.sync
992 dmi, d_reg, d_cr, d_xer, = dbg.dmi, dbg.d_gpr, dbg.d_cr, dbg.d_xer
993 intrf = self.core.regs.rf['int']
994
995 with m.If(d_reg.req): # request for regfile access being made
996 # TODO: error-check this
997 # XXX should this be combinatorial? sync better?
998 if intrf.unary:
999 comb += self.int_r.ren.eq(1<<d_reg.addr)
1000 else:
1001 comb += self.int_r.addr.eq(d_reg.addr)
1002 comb += self.int_r.ren.eq(1)
1003 d_reg_delay = Signal()
1004 sync += d_reg_delay.eq(d_reg.req)
1005 with m.If(d_reg_delay):
1006 # data arrives one clock later
1007 comb += d_reg.data.eq(self.int_r.data_o)
1008 comb += d_reg.ack.eq(1)
1009
1010 # sigh same thing for CR debug
1011 with m.If(d_cr.req): # request for regfile access being made
1012 comb += self.cr_r.ren.eq(0b11111111) # enable all
1013 d_cr_delay = Signal()
1014 sync += d_cr_delay.eq(d_cr.req)
1015 with m.If(d_cr_delay):
1016 # data arrives one clock later
1017 comb += d_cr.data.eq(self.cr_r.data_o)
1018 comb += d_cr.ack.eq(1)
1019
1020 # aaand XER...
1021 with m.If(d_xer.req): # request for regfile access being made
1022 comb += self.xer_r.ren.eq(0b111111) # enable all
1023 d_xer_delay = Signal()
1024 sync += d_xer_delay.eq(d_xer.req)
1025 with m.If(d_xer_delay):
1026 # data arrives one clock later
1027 comb += d_xer.data.eq(self.xer_r.data_o)
1028 comb += d_xer.ack.eq(1)
1029
1030 def tb_dec_fsm(self, m, spr_dec):
1031 """tb_dec_fsm
1032
1033 this is a FSM for updating either dec or tb. it runs alternately
1034 DEC, TB, DEC, TB. note that SPR pipeline could have written a new
1035 value to DEC, however the regfile has "passthrough" on it so this
1036 *should* be ok.
1037
1038 see v3.0B p1097-1099 for Timeer Resource and p1065 and p1076
1039 """
1040
1041 comb, sync = m.d.comb, m.d.sync
1042 fast_rf = self.core.regs.rf['fast']
1043 fast_r_dectb = fast_rf.r_ports['issue'] # DEC/TB
1044 fast_w_dectb = fast_rf.w_ports['issue'] # DEC/TB
1045
1046 with m.FSM() as fsm:
1047
1048 # initiates read of current DEC
1049 with m.State("DEC_READ"):
1050 comb += fast_r_dectb.addr.eq(FastRegs.DEC)
1051 comb += fast_r_dectb.ren.eq(1)
1052 m.next = "DEC_WRITE"
1053
1054 # waits for DEC read to arrive (1 cycle), updates with new value
1055 with m.State("DEC_WRITE"):
1056 new_dec = Signal(64)
1057 # TODO: MSR.LPCR 32-bit decrement mode
1058 comb += new_dec.eq(fast_r_dectb.data_o - 1)
1059 comb += fast_w_dectb.addr.eq(FastRegs.DEC)
1060 comb += fast_w_dectb.wen.eq(1)
1061 comb += fast_w_dectb.data_i.eq(new_dec)
1062 sync += spr_dec.eq(new_dec) # copy into cur_state for decoder
1063 m.next = "TB_READ"
1064
1065 # initiates read of current TB
1066 with m.State("TB_READ"):
1067 comb += fast_r_dectb.addr.eq(FastRegs.TB)
1068 comb += fast_r_dectb.ren.eq(1)
1069 m.next = "TB_WRITE"
1070
1071 # waits for read TB to arrive, initiates write of current TB
1072 with m.State("TB_WRITE"):
1073 new_tb = Signal(64)
1074 comb += new_tb.eq(fast_r_dectb.data_o + 1)
1075 comb += fast_w_dectb.addr.eq(FastRegs.TB)
1076 comb += fast_w_dectb.wen.eq(1)
1077 comb += fast_w_dectb.data_i.eq(new_tb)
1078 m.next = "DEC_READ"
1079
1080 return m
1081
1082 def __iter__(self):
1083 yield from self.pc_i.ports()
1084 yield self.pc_o
1085 yield self.memerr_o
1086 yield from self.core.ports()
1087 yield from self.imem.ports()
1088 yield self.core_bigendian_i
1089 yield self.busy_o
1090
1091 def ports(self):
1092 return list(self)
1093
1094 def external_ports(self):
1095 ports = self.pc_i.ports()
1096 ports += [self.pc_o, self.memerr_o, self.core_bigendian_i, self.busy_o,
1097 ]
1098
1099 if self.jtag_en:
1100 ports += list(self.jtag.external_ports())
1101 else:
1102 # don't add DMI if JTAG is enabled
1103 ports += list(self.dbg.dmi.ports())
1104
1105 ports += list(self.imem.ibus.fields.values())
1106 ports += list(self.core.l0.cmpi.lsmem.lsi.slavebus.fields.values())
1107
1108 if self.sram4x4k:
1109 for sram in self.sram4k:
1110 ports += list(sram.bus.fields.values())
1111
1112 if self.xics:
1113 ports += list(self.xics_icp.bus.fields.values())
1114 ports += list(self.xics_ics.bus.fields.values())
1115 ports.append(self.int_level_i)
1116
1117 if self.gpio:
1118 ports += list(self.simple_gpio.bus.fields.values())
1119 ports.append(self.gpio_o)
1120
1121 return ports
1122
1123 def ports(self):
1124 return list(self)
1125
1126
1127 class TestIssuer(Elaboratable):
1128 def __init__(self, pspec):
1129 self.ti = TestIssuerInternal(pspec)
1130
1131 self.pll = DummyPLL()
1132
1133 # PLL direct clock or not
1134 self.pll_en = hasattr(pspec, "use_pll") and pspec.use_pll
1135 if self.pll_en:
1136 self.pll_18_o = Signal(reset_less=True)
1137
1138 def elaborate(self, platform):
1139 m = Module()
1140 comb = m.d.comb
1141
1142 # TestIssuer runs at direct clock
1143 m.submodules.ti = ti = self.ti
1144 cd_int = ClockDomain("coresync")
1145
1146 if self.pll_en:
1147 # ClockSelect runs at PLL output internal clock rate
1148 m.submodules.pll = pll = self.pll
1149
1150 # add clock domains from PLL
1151 cd_pll = ClockDomain("pllclk")
1152 m.domains += cd_pll
1153
1154 # PLL clock established. has the side-effect of running clklsel
1155 # at the PLL's speed (see DomainRenamer("pllclk") above)
1156 pllclk = ClockSignal("pllclk")
1157 comb += pllclk.eq(pll.clk_pll_o)
1158
1159 # wire up external 24mhz to PLL
1160 comb += pll.clk_24_i.eq(ClockSignal())
1161
1162 # output 18 mhz PLL test signal
1163 comb += self.pll_18_o.eq(pll.pll_18_o)
1164
1165 # now wire up ResetSignals. don't mind them being in this domain
1166 pll_rst = ResetSignal("pllclk")
1167 comb += pll_rst.eq(ResetSignal())
1168
1169 # internal clock is set to selector clock-out. has the side-effect of
1170 # running TestIssuer at this speed (see DomainRenamer("intclk") above)
1171 intclk = ClockSignal("coresync")
1172 if self.pll_en:
1173 comb += intclk.eq(pll.clk_pll_o)
1174 else:
1175 comb += intclk.eq(ClockSignal())
1176
1177 return m
1178
1179 def ports(self):
1180 return list(self.ti.ports()) + list(self.pll.ports()) + \
1181 [ClockSignal(), ResetSignal()]
1182
1183 def external_ports(self):
1184 ports = self.ti.external_ports()
1185 ports.append(ClockSignal())
1186 ports.append(ResetSignal())
1187 if self.pll_en:
1188 ports.append(self.pll.clk_sel_i)
1189 ports.append(self.pll_18_o)
1190 ports.append(self.pll.pll_lck_o)
1191 return ports
1192
1193
1194 if __name__ == '__main__':
1195 units = {'alu': 1, 'cr': 1, 'branch': 1, 'trap': 1, 'logical': 1,
1196 'spr': 1,
1197 'div': 1,
1198 'mul': 1,
1199 'shiftrot': 1
1200 }
1201 pspec = TestMemPspec(ldst_ifacetype='bare_wb',
1202 imem_ifacetype='bare_wb',
1203 addr_wid=48,
1204 mask_wid=8,
1205 reg_wid=64,
1206 units=units)
1207 dut = TestIssuer(pspec)
1208 vl = main(dut, ports=dut.ports(), name="test_issuer")
1209
1210 if len(sys.argv) == 1:
1211 vl = rtlil.convert(dut, ports=dut.external_ports(), name="test_issuer")
1212 with open("test_issuer.il", "w") as f:
1213 f.write(vl)