src/soc/simple/issuer.py

   1 """simple core issuer
   2
   3 not in any way intended for production use.  this runs a FSM that:
   4
   5 * reads the Program Counter from StateRegs
   6 * reads an instruction from a fixed-size Test Memory
   7 * issues it to the Simple Core
   8 * waits for it to complete
   9 * increments the PC
  10 * does it all over again
  11
  12 the purpose of this module is to verify the functional correctness
  13 of the Function Units in the absolute simplest and clearest possible
  14 way, and to at provide something that can be further incrementally
  15 improved.
  16 """
  17
  18 from nmigen import (Elaboratable, Module, Signal, ClockSignal, ResetSignal,
  19                     ClockDomain, DomainRenamer, Mux, Const)
  20 from nmigen.cli import rtlil
  21 from nmigen.cli import main
  22 import sys
  23
  24 from soc.decoder.power_decoder import create_pdecode
  25 from soc.decoder.power_decoder2 import PowerDecode2, SVP64PrefixDecoder
  26 from soc.decoder.decode2execute1 import IssuerDecode2ToOperand
  27 from soc.decoder.decode2execute1 import Data
  28 from soc.experiment.testmem import TestMemory # test only for instructions
  29 from soc.regfile.regfiles import StateRegs, FastRegs
  30 from soc.simple.core import NonProductionCore
  31 from soc.config.test.test_loadstore import TestMemPspec
  32 from soc.config.ifetch import ConfigFetchUnit
  33 from soc.decoder.power_enums import MicrOp
  34 from soc.debug.dmi import CoreDebug, DMIInterface
  35 from soc.debug.jtag import JTAG
  36 from soc.config.pinouts import get_pinspecs
  37 from soc.config.state import CoreState
  38 from soc.interrupts.xics import XICS_ICP, XICS_ICS
  39 from soc.bus.simple_gpio import SimpleGPIO
  40 from soc.bus.SPBlock512W64B8W import SPBlock512W64B8W
  41 from soc.clock.select import ClockSelect
  42 from soc.clock.dummypll import DummyPLL
  43 from soc.sv.svstate import SVSTATERec
  44
  45
  46 from nmutil.util import rising_edge
  47
  48 def get_insn(f_instr_o, pc):
  49     if f_instr_o.width == 32:
  50         return f_instr_o
  51     else:
  52         # 64-bit: bit 2 of pc decides which word to select
  53         return f_instr_o.word_select(pc[2], 32)
  54
  55 # gets state input or reads from state regfile
  56 def state_get(m, state_i, name, regfile, regnum):
  57     comb = m.d.comb
  58     sync = m.d.sync
  59     # read the PC
  60     res = Signal(64, reset_less=True, name=name)
  61     res_ok_delay = Signal(name="%s_ok_delay" % name)
  62     sync += res_ok_delay.eq(~state_i.ok)
  63     with m.If(state_i.ok):
  64         # incoming override (start from pc_i)
  65         comb += res.eq(state_i.data)
  66     with m.Else():
  67         # otherwise read StateRegs regfile for PC...
  68         comb += regfile.ren.eq(1<<regnum)
  69     # ... but on a 1-clock delay
  70     with m.If(res_ok_delay):
  71         comb += res.eq(regfile.data_o)
  72     return res
  73
  74
  75 class TestIssuerInternal(Elaboratable):
  76     """TestIssuer - reads instructions from TestMemory and issues them
  77
  78     efficiency and speed is not the main goal here: functional correctness is.
  79     """
  80     def __init__(self, pspec):
  81
  82         # test is SVP64 is to be enabled
  83         self.svp64_en = hasattr(pspec, "svp64") and (pspec.svp64 == True)
  84
  85         # JTAG interface.  add this right at the start because if it's
  86         # added it *modifies* the pspec, by adding enable/disable signals
  87         # for parts of the rest of the core
  88         self.jtag_en = hasattr(pspec, "debug") and pspec.debug == 'jtag'
  89         if self.jtag_en:
  90             subset = {'uart', 'mtwi', 'eint', 'gpio', 'mspi0', 'mspi1',
  91                       'pwm', 'sd0', 'sdr'}
  92             self.jtag = JTAG(get_pinspecs(subset=subset))
  93             # add signals to pspec to enable/disable icache and dcache
  94             # (or data and intstruction wishbone if icache/dcache not included)
  95             # https://bugs.libre-soc.org/show_bug.cgi?id=520
  96             # TODO: do we actually care if these are not domain-synchronised?
  97             # honestly probably not.
  98             pspec.wb_icache_en = self.jtag.wb_icache_en
  99             pspec.wb_dcache_en = self.jtag.wb_dcache_en
 100             self.wb_sram_en = self.jtag.wb_sram_en
 101         else:
 102             self.wb_sram_en = Const(1)
 103
 104         # add 4k sram blocks?
 105         self.sram4x4k = (hasattr(pspec, "sram4x4kblock") and
 106                          pspec.sram4x4kblock == True)
 107         if self.sram4x4k:
 108             self.sram4k = []
 109             for i in range(4):
 110                 self.sram4k.append(SPBlock512W64B8W(name="sram4k_%d" % i,
 111                                                     features={'err'}))
 112
 113         # add interrupt controller?
 114         self.xics = hasattr(pspec, "xics") and pspec.xics == True
 115         if self.xics:
 116             self.xics_icp = XICS_ICP()
 117             self.xics_ics = XICS_ICS()
 118             self.int_level_i = self.xics_ics.int_level_i
 119
 120         # add GPIO peripheral?
 121         self.gpio = hasattr(pspec, "gpio") and pspec.gpio == True
 122         if self.gpio:
 123             self.simple_gpio = SimpleGPIO()
 124             self.gpio_o = self.simple_gpio.gpio_o
 125
 126         # main instruction core25
 127         self.core = core = NonProductionCore(pspec)
 128
 129         # instruction decoder.  goes into Trap Record
 130         pdecode = create_pdecode()
 131         self.cur_state = CoreState("cur") # current state (MSR/PC/EINT/SVSTATE)
 132         self.pdecode2 = PowerDecode2(pdecode, state=self.cur_state,
 133                                      opkls=IssuerDecode2ToOperand,
 134                                      svp64_en=self.svp64_en)
 135         if self.svp64_en:
 136             self.svp64 = SVP64PrefixDecoder() # for decoding SVP64 prefix
 137
 138         # Test Instruction memory
 139         self.imem = ConfigFetchUnit(pspec).fu
 140         # one-row cache of instruction read
 141         self.iline = Signal(64) # one instruction line
 142         self.iprev_adr = Signal(64) # previous address: if different, do read
 143
 144         # DMI interface
 145         self.dbg = CoreDebug()
 146
 147         # instruction go/monitor
 148         self.pc_o = Signal(64, reset_less=True)
 149         self.pc_i = Data(64, "pc_i") # set "ok" to indicate "please change me"
 150         self.svstate_i = Data(32, "svstate_i") # ditto
 151         self.core_bigendian_i = Signal()
 152         self.busy_o = Signal(reset_less=True)
 153         self.memerr_o = Signal(reset_less=True)
 154
 155         # STATE regfile read /write ports for PC, MSR, SVSTATE
 156         staterf = self.core.regs.rf['state']
 157         self.state_r_pc = staterf.r_ports['cia'] # PC rd
 158         self.state_w_pc = staterf.w_ports['d_wr1'] # PC wr
 159         self.state_r_msr = staterf.r_ports['msr'] # MSR rd
 160         self.state_r_sv = staterf.r_ports['sv'] # SVSTATE rd
 161         self.state_w_sv = staterf.w_ports['sv'] # SVSTATE wr
 162
 163         # DMI interface access
 164         intrf = self.core.regs.rf['int']
 165         crrf = self.core.regs.rf['cr']
 166         xerrf = self.core.regs.rf['xer']
 167         self.int_r = intrf.r_ports['dmi'] # INT read
 168         self.cr_r = crrf.r_ports['full_cr_dbg'] # CR read
 169         self.xer_r = xerrf.r_ports['full_xer'] # XER read
 170
 171         # hack method of keeping an eye on whether branch/trap set the PC
 172         self.state_nia = self.core.regs.rf['state'].w_ports['nia']
 173         self.state_nia.wen.name = 'state_nia_wen'
 174
 175         # pulse to synchronize the simulator at instruction end
 176         self.insn_done = Signal()
 177
 178         if self.svp64_en:
 179             # store copies of predicate masks
 180             self.srcmask = Signal(64)
 181             self.dstmask = Signal(64)
 182
 183     def fetch_fsm(self, m, core, pc, svstate, nia, is_svp64_mode,
 184                         fetch_pc_ready_o, fetch_pc_valid_i,
 185                         fetch_insn_valid_o, fetch_insn_ready_i):
 186         """fetch FSM
 187         this FSM performs fetch of raw instruction data, partial-decodes
 188         it 32-bit at a time to detect SVP64 prefixes, and will optionally
 189         read a 2nd 32-bit quantity if that occurs.
 190         """
 191         comb = m.d.comb
 192         sync = m.d.sync
 193         pdecode2 = self.pdecode2
 194         cur_state = self.cur_state
 195         dec_opcode_i = pdecode2.dec.raw_opcode_in # raw opcode
 196
 197         msr_read = Signal(reset=1)
 198
 199         with m.FSM(name='fetch_fsm'):
 200
 201             # waiting (zzz)
 202             with m.State("IDLE"):
 203                 comb += fetch_pc_ready_o.eq(1)
 204                 with m.If(fetch_pc_valid_i):
 205                     # instruction allowed to go: start by reading the PC
 206                     # capture the PC and also drop it into Insn Memory
 207                     # we have joined a pair of combinatorial memory
 208                     # lookups together.  this is Generally Bad.
 209                     comb += self.imem.a_pc_i.eq(pc)
 210                     comb += self.imem.a_valid_i.eq(1)
 211                     comb += self.imem.f_valid_i.eq(1)
 212                     sync += cur_state.pc.eq(pc)
 213                     sync += cur_state.svstate.eq(svstate) # and svstate
 214
 215                     # initiate read of MSR. arrives one clock later
 216                     comb += self.state_r_msr.ren.eq(1 << StateRegs.MSR)
 217                     sync += msr_read.eq(0)
 218
 219                     m.next = "INSN_READ"  # move to "wait for bus" phase
 220
 221             # dummy pause to find out why simulation is not keeping up
 222             with m.State("INSN_READ"):
 223                 # one cycle later, msr/sv read arrives.  valid only once.
 224                 with m.If(~msr_read):
 225                     sync += msr_read.eq(1) # yeah don't read it again
 226                     sync += cur_state.msr.eq(self.state_r_msr.data_o)
 227                 with m.If(self.imem.f_busy_o): # zzz...
 228                     # busy: stay in wait-read
 229                     comb += self.imem.a_valid_i.eq(1)
 230                     comb += self.imem.f_valid_i.eq(1)
 231                 with m.Else():
 232                     # not busy: instruction fetched
 233                     insn = get_insn(self.imem.f_instr_o, cur_state.pc)
 234                     if self.svp64_en:
 235                         svp64 = self.svp64
 236                         # decode the SVP64 prefix, if any
 237                         comb += svp64.raw_opcode_in.eq(insn)
 238                         comb += svp64.bigendian.eq(self.core_bigendian_i)
 239                         # pass the decoded prefix (if any) to PowerDecoder2
 240                         sync += pdecode2.sv_rm.eq(svp64.svp64_rm)
 241                         # remember whether this is a prefixed instruction, so
 242                         # the FSM can readily loop when VL==0
 243                         sync += is_svp64_mode.eq(svp64.is_svp64_mode)
 244                         # calculate the address of the following instruction
 245                         insn_size = Mux(svp64.is_svp64_mode, 8, 4)
 246                         sync += nia.eq(cur_state.pc + insn_size)
 247                         with m.If(~svp64.is_svp64_mode):
 248                             # with no prefix, store the instruction
 249                             # and hand it directly to the next FSM
 250                             sync += dec_opcode_i.eq(insn)
 251                             m.next = "INSN_READY"
 252                         with m.Else():
 253                             # fetch the rest of the instruction from memory
 254                             comb += self.imem.a_pc_i.eq(cur_state.pc + 4)
 255                             comb += self.imem.a_valid_i.eq(1)
 256                             comb += self.imem.f_valid_i.eq(1)
 257                             m.next = "INSN_READ2"
 258                     else:
 259                         # not SVP64 - 32-bit only
 260                         sync += nia.eq(cur_state.pc + 4)
 261                         sync += dec_opcode_i.eq(insn)
 262                         m.next = "INSN_READY"
 263
 264             with m.State("INSN_READ2"):
 265                 with m.If(self.imem.f_busy_o):  # zzz...
 266                     # busy: stay in wait-read
 267                     comb += self.imem.a_valid_i.eq(1)
 268                     comb += self.imem.f_valid_i.eq(1)
 269                 with m.Else():
 270                     # not busy: instruction fetched
 271                     insn = get_insn(self.imem.f_instr_o, cur_state.pc+4)
 272                     sync += dec_opcode_i.eq(insn)
 273                     m.next = "INSN_READY"
 274                     # TODO: probably can start looking at pdecode2.rm_dec
 275                     # here (or maybe even in INSN_READ state, if svp64_mode
 276                     # detected, in order to trigger - and wait for - the
 277                     # predicate reading.
 278
 279             with m.State("INSN_READY"):
 280                 # hand over the instruction, to be decoded
 281                 comb += fetch_insn_valid_o.eq(1)
 282                 with m.If(fetch_insn_ready_i):
 283                     m.next = "IDLE"
 284
 285     def fetch_predicate_fsm(self, m, core, TODO):
 286         """fetch_predicate_fsm - obtains (constructs in the case of CR)
 287            src/dest predicate masks
 288
 289         https://bugs.libre-soc.org/show_bug.cgi?id=617
 290         the predicates can be read here, by using IntRegs r_ports['pred']
 291         or CRRegs r_ports['pred'].  in the case of CRs it will have to
 292         be done through multiple reads, extracting one relevant at a time.
 293         later, a faster way would be to use the 32-bit-wide CR port but
 294         this is more complex decoding, here.  equivalent code used in
 295         ISACaller is "from soc.decoder.isa.caller import get_predcr"
 296         """
 297         comb = m.d.comb
 298         sync = m.d.sync
 299         pdecode2 = self.pdecode2
 300         rm_dec = pdecode2.rm_dec # SVP64RMModeDecode
 301         predmode = rm_dec.predmode
 302         srcpred, dstpred = rm_dec.srcpred, rm_dec.dstpred
 303
 304     def issue_fsm(self, m, core, pc_changed, sv_changed, nia,
 305                   dbg, core_rst, is_svp64_mode,
 306                   fetch_pc_ready_o, fetch_pc_valid_i,
 307                   fetch_insn_valid_o, fetch_insn_ready_i,
 308                   exec_insn_valid_i, exec_insn_ready_o,
 309                   exec_pc_valid_o, exec_pc_ready_i):
 310         """issue FSM
 311
 312         decode / issue FSM.  this interacts with the "fetch" FSM
 313         through fetch_insn_ready/valid (incoming) and fetch_pc_ready/valid
 314         (outgoing). also interacts with the "execute" FSM
 315         through exec_insn_ready/valid (outgoing) and exec_pc_ready/valid
 316         (incoming).
 317         SVP64 RM prefixes have already been set up by the
 318         "fetch" phase, so execute is fairly straightforward.
 319         """
 320
 321         comb = m.d.comb
 322         sync = m.d.sync
 323         pdecode2 = self.pdecode2
 324         cur_state = self.cur_state
 325
 326         # temporaries
 327         dec_opcode_i = pdecode2.dec.raw_opcode_in # raw opcode
 328
 329         # for updating svstate (things like srcstep etc.)
 330         update_svstate = Signal() # set this (below) if updating
 331         new_svstate = SVSTATERec("new_svstate")
 332         comb += new_svstate.eq(cur_state.svstate)
 333
 334         with m.FSM(name="issue_fsm"):
 335
 336             # sync with the "fetch" phase which is reading the instruction
 337             # at this point, there is no instruction running, that
 338             # could inadvertently update the PC.
 339             with m.State("ISSUE_START"):
 340                 # wait on "core stop" release, before next fetch
 341                 # need to do this here, in case we are in a VL==0 loop
 342                 with m.If(~dbg.core_stop_o & ~core_rst):
 343                     comb += fetch_pc_valid_i.eq(1) # tell fetch to start
 344                     with m.If(fetch_pc_ready_o):   # fetch acknowledged us
 345                         m.next = "INSN_WAIT"
 346                 with m.Else():
 347                     # tell core it's stopped, and acknowledge debug handshake
 348                     comb += core.core_stopped_i.eq(1)
 349                     comb += dbg.core_stopped_i.eq(1)
 350                     # while stopped, allow updating the PC and SVSTATE
 351                     with m.If(self.pc_i.ok):
 352                         comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
 353                         comb += self.state_w_pc.data_i.eq(self.pc_i.data)
 354                         sync += pc_changed.eq(1)
 355                     with m.If(self.svstate_i.ok):
 356                         comb += new_svstate.eq(self.svstate_i.data)
 357                         comb += update_svstate.eq(1)
 358                         sync += sv_changed.eq(1)
 359
 360             # decode the instruction when it arrives
 361             with m.State("INSN_WAIT"):
 362                 comb += fetch_insn_ready_i.eq(1)
 363                 with m.If(fetch_insn_valid_o):
 364                     # decode the instruction
 365                     sync += core.e.eq(pdecode2.e)
 366                     sync += core.state.eq(cur_state)
 367                     sync += core.raw_insn_i.eq(dec_opcode_i)
 368                     sync += core.bigendian_i.eq(self.core_bigendian_i)
 369                     # set RA_OR_ZERO detection in satellite decoders
 370                     sync += core.sv_a_nz.eq(pdecode2.sv_a_nz)
 371                     # loop into ISSUE_START if it's a SVP64 instruction
 372                     # and VL == 0.  this because VL==0 is a for-loop
 373                     # from 0 to 0 i.e. always, always a NOP.
 374                     cur_vl = cur_state.svstate.vl
 375                     with m.If(is_svp64_mode & (cur_vl == 0)):
 376                         # update the PC before fetching the next instruction
 377                         # since we are in a VL==0 loop, no instruction was
 378                         # executed that we could be overwriting
 379                         comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
 380                         comb += self.state_w_pc.data_i.eq(nia)
 381                         comb += self.insn_done.eq(1)
 382                         m.next = "ISSUE_START"
 383                     with m.Else():
 384                         m.next = "INSN_EXECUTE"  # move to "execute"
 385
 386             # handshake with execution FSM, move to "wait" once acknowledged
 387             with m.State("INSN_EXECUTE"):
 388                 # with m.If(is_svp64_mode):
 389                 #    TODO advance src/dst step to "skip" over predicated-out
 390                 #    from self.srcmask and self.dstmask
 391                 #    https://bugs.libre-soc.org/show_bug.cgi?id=617#c3
 392                 #    but still without exceeding VL in either case
 393                 comb += exec_insn_valid_i.eq(1) # trigger execute
 394                 with m.If(exec_insn_ready_o):   # execute acknowledged us
 395                     m.next = "EXECUTE_WAIT"
 396
 397             with m.State("EXECUTE_WAIT"):
 398                 # wait on "core stop" release, at instruction end
 399                 # need to do this here, in case we are in a VL>1 loop
 400                 with m.If(~dbg.core_stop_o & ~core_rst):
 401                     comb += exec_pc_ready_i.eq(1)
 402                     with m.If(exec_pc_valid_o):
 403                         # precalculate srcstep+1 and dststep+1
 404                         next_srcstep = Signal.like(cur_state.svstate.srcstep)
 405                         next_dststep = Signal.like(cur_state.svstate.dststep)
 406                         comb += next_srcstep.eq(cur_state.svstate.srcstep+1)
 407                         comb += next_dststep.eq(cur_state.svstate.dststep+1)
 408
 409                         # was this the last loop iteration?
 410                         is_last = Signal()
 411                         cur_vl = cur_state.svstate.vl
 412                         comb += is_last.eq(next_srcstep == cur_vl)
 413
 414                         # if either PC or SVSTATE were changed by the previous
 415                         # instruction, go directly back to Fetch, without
 416                         # updating either PC or SVSTATE
 417                         with m.If(pc_changed | sv_changed):
 418                             m.next = "ISSUE_START"
 419
 420                         # also return to Fetch, when no output was a vector
 421                         # (regardless of SRCSTEP and VL), or when the last
 422                         # instruction was really the last one of the VL loop
 423                         with m.Elif((~pdecode2.loop_continue) | is_last):
 424                             # before going back to fetch, update the PC state
 425                             # register with the NIA.
 426                             # ok here we are not reading the branch unit.
 427                             # TODO: this just blithely overwrites whatever
 428                             #       pipeline updated the PC
 429                             comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
 430                             comb += self.state_w_pc.data_i.eq(nia)
 431                             # reset SRCSTEP before returning to Fetch
 432                             with m.If(pdecode2.loop_continue):
 433                                 comb += new_svstate.srcstep.eq(0)
 434                                 comb += new_svstate.dststep.eq(0)
 435                                 comb += update_svstate.eq(1)
 436                             m.next = "ISSUE_START"
 437
 438                         # returning to Execute? then, first update SRCSTEP
 439                         with m.Else():
 440                             comb += new_svstate.srcstep.eq(next_srcstep)
 441                             comb += new_svstate.dststep.eq(next_dststep)
 442                             comb += update_svstate.eq(1)
 443                             m.next = "DECODE_SV"
 444
 445                 with m.Else():
 446                     comb += core.core_stopped_i.eq(1)
 447                     comb += dbg.core_stopped_i.eq(1)
 448                     # while stopped, allow updating the PC and SVSTATE
 449                     with m.If(self.pc_i.ok):
 450                         comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
 451                         comb += self.state_w_pc.data_i.eq(self.pc_i.data)
 452                         sync += pc_changed.eq(1)
 453                     with m.If(self.svstate_i.ok):
 454                         comb += new_svstate.eq(self.svstate_i.data)
 455                         comb += update_svstate.eq(1)
 456                         sync += sv_changed.eq(1)
 457
 458             # need to decode the instruction again, after updating SRCSTEP
 459             # in the previous state.
 460             # mostly a copy of INSN_WAIT, but without the actual wait
 461             with m.State("DECODE_SV"):
 462                 # decode the instruction
 463                 sync += core.e.eq(pdecode2.e)
 464                 sync += core.state.eq(cur_state)
 465                 sync += core.bigendian_i.eq(self.core_bigendian_i)
 466                 sync += core.sv_a_nz.eq(pdecode2.sv_a_nz)
 467                 m.next = "INSN_EXECUTE"  # move to "execute"
 468
 469         # check if svstate needs updating: if so, write it to State Regfile
 470         with m.If(update_svstate):
 471             comb += self.state_w_sv.wen.eq(1<<StateRegs.SVSTATE)
 472             comb += self.state_w_sv.data_i.eq(new_svstate)
 473             sync += cur_state.svstate.eq(new_svstate) # for next clock
 474
 475     def execute_fsm(self, m, core, pc_changed, sv_changed,
 476                     exec_insn_valid_i, exec_insn_ready_o,
 477                     exec_pc_valid_o, exec_pc_ready_i):
 478         """execute FSM
 479
 480         execute FSM. this interacts with the "issue" FSM
 481         through exec_insn_ready/valid (incoming) and exec_pc_ready/valid
 482         (outgoing). SVP64 RM prefixes have already been set up by the
 483         "issue" phase, so execute is fairly straightforward.
 484         """
 485
 486         comb = m.d.comb
 487         sync = m.d.sync
 488         pdecode2 = self.pdecode2
 489
 490         # temporaries
 491         core_busy_o = core.busy_o                 # core is busy
 492         core_ivalid_i = core.ivalid_i             # instruction is valid
 493         core_issue_i = core.issue_i               # instruction is issued
 494         insn_type = core.e.do.insn_type           # instruction MicroOp type
 495
 496         with m.FSM(name="exec_fsm"):
 497
 498             # waiting for instruction bus (stays there until not busy)
 499             with m.State("INSN_START"):
 500                 comb += exec_insn_ready_o.eq(1)
 501                 with m.If(exec_insn_valid_i):
 502                     comb += core_ivalid_i.eq(1)  # instruction is valid
 503                     comb += core_issue_i.eq(1)  # and issued
 504                     sync += sv_changed.eq(0)
 505                     sync += pc_changed.eq(0)
 506                     m.next = "INSN_ACTIVE"  # move to "wait completion"
 507
 508             # instruction started: must wait till it finishes
 509             with m.State("INSN_ACTIVE"):
 510                 with m.If(insn_type != MicrOp.OP_NOP):
 511                     comb += core_ivalid_i.eq(1) # instruction is valid
 512                 # note changes to PC and SVSTATE
 513                 with m.If(self.state_nia.wen & (1<<StateRegs.SVSTATE)):
 514                     sync += sv_changed.eq(1)
 515                 with m.If(self.state_nia.wen & (1<<StateRegs.PC)):
 516                     sync += pc_changed.eq(1)
 517                 with m.If(~core_busy_o): # instruction done!
 518                     comb += exec_pc_valid_o.eq(1)
 519                     with m.If(exec_pc_ready_i):
 520                         comb += self.insn_done.eq(1)
 521                         m.next = "INSN_START"  # back to fetch
 522
 523     def elaborate(self, platform):
 524         m = Module()
 525         comb, sync = m.d.comb, m.d.sync
 526
 527         m.submodules.core = core = DomainRenamer("coresync")(self.core)
 528         m.submodules.imem = imem = self.imem
 529         m.submodules.dbg = dbg = self.dbg
 530         if self.jtag_en:
 531             m.submodules.jtag = jtag = self.jtag
 532             # TODO: UART2GDB mux, here, from external pin
 533             # see https://bugs.libre-soc.org/show_bug.cgi?id=499
 534             sync += dbg.dmi.connect_to(jtag.dmi)
 535
 536         cur_state = self.cur_state
 537
 538         # 4x 4k SRAM blocks.  these simply "exist", they get routed in litex
 539         if self.sram4x4k:
 540             for i, sram in enumerate(self.sram4k):
 541                 m.submodules["sram4k_%d" % i] = sram
 542                 comb += sram.enable.eq(self.wb_sram_en)
 543
 544         # XICS interrupt handler
 545         if self.xics:
 546             m.submodules.xics_icp = icp = self.xics_icp
 547             m.submodules.xics_ics = ics = self.xics_ics
 548             comb += icp.ics_i.eq(ics.icp_o)           # connect ICS to ICP
 549             sync += cur_state.eint.eq(icp.core_irq_o) # connect ICP to core
 550
 551         # GPIO test peripheral
 552         if self.gpio:
 553             m.submodules.simple_gpio = simple_gpio = self.simple_gpio
 554
 555         # connect one GPIO output to ICS bit 15 (like in microwatt soc.vhdl)
 556         # XXX causes litex ECP5 test to get wrong idea about input and output
 557         # (but works with verilator sim *sigh*)
 558         #if self.gpio and self.xics:
 559         #   comb += self.int_level_i[15].eq(simple_gpio.gpio_o[0])
 560
 561         # instruction decoder
 562         pdecode = create_pdecode()
 563         m.submodules.dec2 = pdecode2 = self.pdecode2
 564         if self.svp64_en:
 565             m.submodules.svp64 = svp64 = self.svp64
 566
 567         # convenience
 568         dmi, d_reg, d_cr, d_xer, = dbg.dmi, dbg.d_gpr, dbg.d_cr, dbg.d_xer
 569         intrf = self.core.regs.rf['int']
 570
 571         # clock delay power-on reset
 572         cd_por  = ClockDomain(reset_less=True)
 573         cd_sync = ClockDomain()
 574         core_sync = ClockDomain("coresync")
 575         m.domains += cd_por, cd_sync, core_sync
 576
 577         ti_rst = Signal(reset_less=True)
 578         delay = Signal(range(4), reset=3)
 579         with m.If(delay != 0):
 580             m.d.por += delay.eq(delay - 1)
 581         comb += cd_por.clk.eq(ClockSignal())
 582
 583         # power-on reset delay
 584         core_rst = ResetSignal("coresync")
 585         comb += ti_rst.eq(delay != 0 | dbg.core_rst_o | ResetSignal())
 586         comb += core_rst.eq(ti_rst)
 587
 588         # busy/halted signals from core
 589         comb += self.busy_o.eq(core.busy_o)
 590         comb += pdecode2.dec.bigendian.eq(self.core_bigendian_i)
 591
 592         # temporary hack: says "go" immediately for both address gen and ST
 593         l0 = core.l0
 594         ldst = core.fus.fus['ldst0']
 595         st_go_edge = rising_edge(m, ldst.st.rel_o)
 596         m.d.comb += ldst.ad.go_i.eq(ldst.ad.rel_o) # link addr-go direct to rel
 597         m.d.comb += ldst.st.go_i.eq(st_go_edge) # link store-go to rising rel
 598
 599         # PC and instruction from I-Memory
 600         comb += self.pc_o.eq(cur_state.pc)
 601         pc_changed = Signal() # note write to PC
 602         sv_changed = Signal() # note write to SVSTATE
 603
 604         # read state either from incoming override or from regfile
 605         # TODO: really should be doing MSR in the same say
 606         pc = state_get(m, self.pc_i, "pc",                  # read PC
 607                             self.state_r_pc, StateRegs.PC)
 608         svstate = state_get(m, self.svstate_i, "svstate",   # read SVSTATE
 609                             self.state_r_sv, StateRegs.SVSTATE)
 610
 611         # don't write pc every cycle
 612         comb += self.state_w_pc.wen.eq(0)
 613         comb += self.state_w_pc.data_i.eq(0)
 614
 615         # don't read msr every cycle
 616         comb += self.state_r_msr.ren.eq(0)
 617
 618         # address of the next instruction, in the absence of a branch
 619         # depends on the instruction size
 620         nia = Signal(64, reset_less=True)
 621
 622         # connect up debug signals
 623         # TODO comb += core.icache_rst_i.eq(dbg.icache_rst_o)
 624         comb += dbg.terminate_i.eq(core.core_terminate_o)
 625         comb += dbg.state.pc.eq(pc)
 626         comb += dbg.state.svstate.eq(svstate)
 627         comb += dbg.state.msr.eq(cur_state.msr)
 628
 629         # pass the prefix mode from Fetch to Issue, so the latter can loop
 630         # on VL==0
 631         is_svp64_mode = Signal()
 632
 633         # there are *THREE* FSMs, fetch (32/64-bit) issue, decode/execute.
 634         # these are the handshake signals between fetch and decode/execute
 635
 636         # fetch FSM can run as soon as the PC is valid
 637         fetch_pc_valid_i = Signal() # Execute tells Fetch "start next read"
 638         fetch_pc_ready_o = Signal() # Fetch Tells SVSTATE "proceed"
 639
 640         # fetch FSM hands over the instruction to be decoded / issued
 641         fetch_insn_valid_o = Signal()
 642         fetch_insn_ready_i = Signal()
 643
 644         # issue FSM delivers the instruction to the be executed
 645         exec_insn_valid_i = Signal()
 646         exec_insn_ready_o = Signal()
 647
 648         # execute FSM, hands over the PC/SVSTATE back to the issue FSM
 649         exec_pc_valid_o = Signal()
 650         exec_pc_ready_i = Signal()
 651
 652         # the FSMs here are perhaps unusual in that they detect conditions
 653         # then "hold" information, combinatorially, for the core
 654         # (as opposed to using sync - which would be on a clock's delay)
 655         # this includes the actual opcode, valid flags and so on.
 656
 657         # Fetch, then Issue, then Execute. Issue is where the VL for-loop
 658         # lives.  the ready/valid signalling is used to communicate between
 659         # the three.
 660
 661         self.fetch_fsm(m, core, pc, svstate, nia, is_svp64_mode,
 662                        fetch_pc_ready_o, fetch_pc_valid_i,
 663                        fetch_insn_valid_o, fetch_insn_ready_i)
 664
 665         self.issue_fsm(m, core, pc_changed, sv_changed, nia,
 666                        dbg, core_rst, is_svp64_mode,
 667                        fetch_pc_ready_o, fetch_pc_valid_i,
 668                        fetch_insn_valid_o, fetch_insn_ready_i,
 669                        exec_insn_valid_i, exec_insn_ready_o,
 670                        exec_pc_valid_o, exec_pc_ready_i)
 671
 672         self.execute_fsm(m, core, pc_changed, sv_changed,
 673                          exec_insn_valid_i, exec_insn_ready_o,
 674                          exec_pc_valid_o, exec_pc_ready_i)
 675
 676         # this bit doesn't have to be in the FSM: connect up to read
 677         # regfiles on demand from DMI
 678         self.do_dmi(m, dbg)
 679
 680         # DEC and TB inc/dec FSM.  copy of DEC is put into CoreState,
 681         # (which uses that in PowerDecoder2 to raise 0x900 exception)
 682         self.tb_dec_fsm(m, cur_state.dec)
 683
 684         return m
 685
 686     def do_dmi(self, m, dbg):
 687         comb = m.d.comb
 688         sync = m.d.sync
 689         dmi, d_reg, d_cr, d_xer, = dbg.dmi, dbg.d_gpr, dbg.d_cr, dbg.d_xer
 690         intrf = self.core.regs.rf['int']
 691
 692         with m.If(d_reg.req): # request for regfile access being made
 693             # TODO: error-check this
 694             # XXX should this be combinatorial?  sync better?
 695             if intrf.unary:
 696                 comb += self.int_r.ren.eq(1<<d_reg.addr)
 697             else:
 698                 comb += self.int_r.addr.eq(d_reg.addr)
 699                 comb += self.int_r.ren.eq(1)
 700         d_reg_delay  = Signal()
 701         sync += d_reg_delay.eq(d_reg.req)
 702         with m.If(d_reg_delay):
 703             # data arrives one clock later
 704             comb += d_reg.data.eq(self.int_r.data_o)
 705             comb += d_reg.ack.eq(1)
 706
 707         # sigh same thing for CR debug
 708         with m.If(d_cr.req): # request for regfile access being made
 709             comb += self.cr_r.ren.eq(0b11111111) # enable all
 710         d_cr_delay  = Signal()
 711         sync += d_cr_delay.eq(d_cr.req)
 712         with m.If(d_cr_delay):
 713             # data arrives one clock later
 714             comb += d_cr.data.eq(self.cr_r.data_o)
 715             comb += d_cr.ack.eq(1)
 716
 717         # aaand XER...
 718         with m.If(d_xer.req): # request for regfile access being made
 719             comb += self.xer_r.ren.eq(0b111111) # enable all
 720         d_xer_delay  = Signal()
 721         sync += d_xer_delay.eq(d_xer.req)
 722         with m.If(d_xer_delay):
 723             # data arrives one clock later
 724             comb += d_xer.data.eq(self.xer_r.data_o)
 725             comb += d_xer.ack.eq(1)
 726
 727     def tb_dec_fsm(self, m, spr_dec):
 728         """tb_dec_fsm
 729
 730         this is a FSM for updating either dec or tb.  it runs alternately
 731         DEC, TB, DEC, TB.  note that SPR pipeline could have written a new
 732         value to DEC, however the regfile has "passthrough" on it so this
 733         *should* be ok.
 734
 735         see v3.0B p1097-1099 for Timeer Resource and p1065 and p1076
 736         """
 737
 738         comb, sync = m.d.comb, m.d.sync
 739         fast_rf = self.core.regs.rf['fast']
 740         fast_r_dectb = fast_rf.r_ports['issue'] # DEC/TB
 741         fast_w_dectb = fast_rf.w_ports['issue'] # DEC/TB
 742
 743         with m.FSM() as fsm:
 744
 745             # initiates read of current DEC
 746             with m.State("DEC_READ"):
 747                 comb += fast_r_dectb.addr.eq(FastRegs.DEC)
 748                 comb += fast_r_dectb.ren.eq(1)
 749                 m.next = "DEC_WRITE"
 750
 751             # waits for DEC read to arrive (1 cycle), updates with new value
 752             with m.State("DEC_WRITE"):
 753                 new_dec = Signal(64)
 754                 # TODO: MSR.LPCR 32-bit decrement mode
 755                 comb += new_dec.eq(fast_r_dectb.data_o - 1)
 756                 comb += fast_w_dectb.addr.eq(FastRegs.DEC)
 757                 comb += fast_w_dectb.wen.eq(1)
 758                 comb += fast_w_dectb.data_i.eq(new_dec)
 759                 sync += spr_dec.eq(new_dec) # copy into cur_state for decoder
 760                 m.next = "TB_READ"
 761
 762             # initiates read of current TB
 763             with m.State("TB_READ"):
 764                 comb += fast_r_dectb.addr.eq(FastRegs.TB)
 765                 comb += fast_r_dectb.ren.eq(1)
 766                 m.next = "TB_WRITE"
 767
 768             # waits for read TB to arrive, initiates write of current TB
 769             with m.State("TB_WRITE"):
 770                 new_tb = Signal(64)
 771                 comb += new_tb.eq(fast_r_dectb.data_o + 1)
 772                 comb += fast_w_dectb.addr.eq(FastRegs.TB)
 773                 comb += fast_w_dectb.wen.eq(1)
 774                 comb += fast_w_dectb.data_i.eq(new_tb)
 775                 m.next = "DEC_READ"
 776
 777         return m
 778
 779     def __iter__(self):
 780         yield from self.pc_i.ports()
 781         yield self.pc_o
 782         yield self.memerr_o
 783         yield from self.core.ports()
 784         yield from self.imem.ports()
 785         yield self.core_bigendian_i
 786         yield self.busy_o
 787
 788     def ports(self):
 789         return list(self)
 790
 791     def external_ports(self):
 792         ports = self.pc_i.ports()
 793         ports += [self.pc_o, self.memerr_o, self.core_bigendian_i, self.busy_o,
 794                 ]
 795
 796         if self.jtag_en:
 797             ports += list(self.jtag.external_ports())
 798         else:
 799             # don't add DMI if JTAG is enabled
 800             ports += list(self.dbg.dmi.ports())
 801
 802         ports += list(self.imem.ibus.fields.values())
 803         ports += list(self.core.l0.cmpi.lsmem.lsi.slavebus.fields.values())
 804
 805         if self.sram4x4k:
 806             for sram in self.sram4k:
 807                 ports += list(sram.bus.fields.values())
 808
 809         if self.xics:
 810             ports += list(self.xics_icp.bus.fields.values())
 811             ports += list(self.xics_ics.bus.fields.values())
 812             ports.append(self.int_level_i)
 813
 814         if self.gpio:
 815             ports += list(self.simple_gpio.bus.fields.values())
 816             ports.append(self.gpio_o)
 817
 818         return ports
 819
 820     def ports(self):
 821         return list(self)
 822
 823
 824 class TestIssuer(Elaboratable):
 825     def __init__(self, pspec):
 826         self.ti = TestIssuerInternal(pspec)
 827
 828         self.pll = DummyPLL()
 829
 830         # PLL direct clock or not
 831         self.pll_en = hasattr(pspec, "use_pll") and pspec.use_pll
 832         if self.pll_en:
 833             self.pll_18_o = Signal(reset_less=True)
 834
 835     def elaborate(self, platform):
 836         m = Module()
 837         comb = m.d.comb
 838
 839         # TestIssuer runs at direct clock
 840         m.submodules.ti = ti = self.ti
 841         cd_int = ClockDomain("coresync")
 842
 843         if self.pll_en:
 844             # ClockSelect runs at PLL output internal clock rate
 845             m.submodules.pll = pll = self.pll
 846
 847             # add clock domains from PLL
 848             cd_pll = ClockDomain("pllclk")
 849             m.domains += cd_pll
 850
 851             # PLL clock established.  has the side-effect of running clklsel
 852             # at the PLL's speed (see DomainRenamer("pllclk") above)
 853             pllclk = ClockSignal("pllclk")
 854             comb += pllclk.eq(pll.clk_pll_o)
 855
 856             # wire up external 24mhz to PLL
 857             comb += pll.clk_24_i.eq(ClockSignal())
 858
 859             # output 18 mhz PLL test signal
 860             comb += self.pll_18_o.eq(pll.pll_18_o)
 861
 862             # now wire up ResetSignals.  don't mind them being in this domain
 863             pll_rst = ResetSignal("pllclk")
 864             comb += pll_rst.eq(ResetSignal())
 865
 866         # internal clock is set to selector clock-out.  has the side-effect of
 867         # running TestIssuer at this speed (see DomainRenamer("intclk") above)
 868         intclk = ClockSignal("coresync")
 869         if self.pll_en:
 870             comb += intclk.eq(pll.clk_pll_o)
 871         else:
 872             comb += intclk.eq(ClockSignal())
 873
 874         return m
 875
 876     def ports(self):
 877         return list(self.ti.ports()) + list(self.pll.ports()) + \
 878                [ClockSignal(), ResetSignal()]
 879
 880     def external_ports(self):
 881         ports = self.ti.external_ports()
 882         ports.append(ClockSignal())
 883         ports.append(ResetSignal())
 884         if self.pll_en:
 885             ports.append(self.pll.clk_sel_i)
 886             ports.append(self.pll_18_o)
 887             ports.append(self.pll.pll_lck_o)
 888         return ports
 889
 890
 891 if __name__ == '__main__':
 892     units = {'alu': 1, 'cr': 1, 'branch': 1, 'trap': 1, 'logical': 1,
 893              'spr': 1,
 894              'div': 1,
 895              'mul': 1,
 896              'shiftrot': 1
 897             }
 898     pspec = TestMemPspec(ldst_ifacetype='bare_wb',
 899                          imem_ifacetype='bare_wb',
 900                          addr_wid=48,
 901                          mask_wid=8,
 902                          reg_wid=64,
 903                          units=units)
 904     dut = TestIssuer(pspec)
 905     vl = main(dut, ports=dut.ports(), name="test_issuer")
 906
 907     if len(sys.argv) == 1:
 908         vl = rtlil.convert(dut, ports=dut.external_ports(), name="test_issuer")
 909         with open("test_issuer.il", "w") as f:
 910             f.write(vl)