src/soc/simple/issuer.py

   1 """simple core issuer
   2
   3 not in any way intended for production use.  this runs a FSM that:
   4
   5 * reads the Program Counter from StateRegs
   6 * reads an instruction from a fixed-size Test Memory
   7 * issues it to the Simple Core
   8 * waits for it to complete
   9 * increments the PC
  10 * does it all over again
  11
  12 the purpose of this module is to verify the functional correctness
  13 of the Function Units in the absolute simplest and clearest possible
  14 way, and to at provide something that can be further incrementally
  15 improved.
  16 """
  17
  18 from nmigen import (Elaboratable, Module, Signal, ClockSignal, ResetSignal,
  19                     ClockDomain, DomainRenamer)
  20 from nmigen.cli import rtlil
  21 from nmigen.cli import main
  22 import sys
  23
  24 from soc.decoder.power_decoder import create_pdecode
  25 from soc.decoder.power_decoder2 import PowerDecode2
  26 from soc.decoder.decode2execute1 import Data
  27 from soc.experiment.testmem import TestMemory # test only for instructions
  28 from soc.regfile.regfiles import StateRegs, FastRegs
  29 from soc.simple.core import NonProductionCore
  30 from soc.config.test.test_loadstore import TestMemPspec
  31 from soc.config.ifetch import ConfigFetchUnit
  32 from soc.decoder.power_enums import MicrOp
  33 from soc.debug.dmi import CoreDebug, DMIInterface
  34 from soc.config.state import CoreState
  35 from soc.interrupts.xics import XICS_ICP, XICS_ICS
  36 from soc.bus.simple_gpio import SimpleGPIO
  37
  38 from nmutil.util import rising_edge
  39
  40
  41 class TestIssuer(Elaboratable):
  42     """TestIssuer - reads instructions from TestMemory and issues them
  43
  44     efficiency and speed is not the main goal here: functional correctness is.
  45     """
  46     def __init__(self, pspec):
  47
  48         # add interrupt controller?
  49         self.xics = hasattr(pspec, "xics") and pspec.xics == True
  50         if self.xics:
  51             self.xics_icp = XICS_ICP()
  52             self.xics_ics = XICS_ICS()
  53             self.int_level_i = self.xics_ics.int_level_i
  54
  55         # add GPIO peripheral?
  56         self.gpio = hasattr(pspec, "gpio") and pspec.gpio == True
  57         if self.gpio:
  58             self.simple_gpio = SimpleGPIO()
  59             self.gpio_o = self.simple_gpio.gpio_o
  60
  61         # main instruction core
  62         self.core = core = NonProductionCore(pspec)
  63
  64         # instruction decoder
  65         pdecode = create_pdecode()
  66         self.pdecode2 = PowerDecode2(pdecode)   # decoder
  67
  68         # Test Instruction memory
  69         self.imem = ConfigFetchUnit(pspec).fu
  70         # one-row cache of instruction read
  71         self.iline = Signal(64) # one instruction line
  72         self.iprev_adr = Signal(64) # previous address: if different, do read
  73
  74         # DMI interface
  75         self.dbg = CoreDebug()
  76
  77         # instruction go/monitor
  78         self.pc_o = Signal(64, reset_less=True)
  79         self.pc_i = Data(64, "pc_i") # set "ok" to indicate "please change me"
  80         self.core_bigendian_i = Signal()
  81         self.busy_o = Signal(reset_less=True)
  82         self.memerr_o = Signal(reset_less=True)
  83
  84         # FAST regfile read /write ports for PC, MSR, DEC/TB
  85         staterf = self.core.regs.rf['state']
  86         self.state_r_pc = staterf.r_ports['cia'] # PC rd
  87         self.state_w_pc = staterf.w_ports['d_wr1'] # PC wr
  88         self.state_r_msr = staterf.r_ports['msr'] # MSR rd
  89
  90         # DMI interface access
  91         intrf = self.core.regs.rf['int']
  92         crrf = self.core.regs.rf['cr']
  93         xerrf = self.core.regs.rf['xer']
  94         self.int_r = intrf.r_ports['dmi'] # INT read
  95         self.cr_r = crrf.r_ports['full_cr_dbg'] # CR read
  96         self.xer_r = xerrf.r_ports['full_xer'] # XER read
  97
  98         # hack method of keeping an eye on whether branch/trap set the PC
  99         self.state_nia = self.core.regs.rf['state'].w_ports['nia']
 100         self.state_nia.wen.name = 'state_nia_wen'
 101
 102     def elaborate(self, platform):
 103         m = Module()
 104         comb, sync = m.d.comb, m.d.sync
 105
 106         m.submodules.core = core = DomainRenamer("coresync")(self.core)
 107         m.submodules.imem = imem = self.imem
 108         m.submodules.dbg = dbg = self.dbg
 109
 110         # current state (MSR/PC at the moment
 111         cur_state = CoreState("cur")
 112
 113         # XICS interrupt handler
 114         if self.xics:
 115             m.submodules.xics_icp = icp = self.xics_icp
 116             m.submodules.xics_ics = ics = self.xics_ics
 117             comb += icp.ics_i.eq(ics.icp_o)           # connect ICS to ICP
 118             sync += cur_state.eint.eq(icp.core_irq_o) # connect ICP to core
 119
 120         # GPIO test peripheral
 121         if self.gpio:
 122             m.submodules.simple_gpio = simple_gpio = self.simple_gpio
 123
 124         # connect one GPIO output to ICS bit 15 (like in microwatt soc.vhdl)
 125         if self.gpio and self.xics:
 126             comb += self.int_level_i[15].eq(simple_gpio.gpio_o[0])
 127
 128         # instruction decoder
 129         pdecode = create_pdecode()
 130         m.submodules.dec2 = pdecode2 = self.pdecode2
 131
 132         # convenience
 133         dmi, d_reg, d_cr, d_xer, = dbg.dmi, dbg.d_gpr, dbg.d_cr, dbg.d_xer
 134         intrf = self.core.regs.rf['int']
 135
 136         # clock delay power-on reset
 137         cd_por  = ClockDomain(reset_less=True)
 138         cd_sync = ClockDomain()
 139         core_sync = ClockDomain("coresync")
 140         m.domains += cd_por, cd_sync, core_sync
 141
 142         delay = Signal(range(4), reset=3)
 143         with m.If(delay != 0):
 144             m.d.por += delay.eq(delay - 1)
 145         comb += cd_por.clk.eq(ClockSignal())
 146         comb += core_sync.clk.eq(ClockSignal())
 147         # power-on reset delay
 148         comb += core.core_reset_i.eq(delay != 0 | dbg.core_rst_o)
 149
 150         # busy/halted signals from core
 151         comb += self.busy_o.eq(core.busy_o)
 152         comb += pdecode2.dec.bigendian.eq(self.core_bigendian_i)
 153
 154         # temporary hack: says "go" immediately for both address gen and ST
 155         l0 = core.l0
 156         ldst = core.fus.fus['ldst0']
 157         st_go_edge = rising_edge(m, ldst.st.rel_o)
 158         m.d.comb += ldst.ad.go_i.eq(ldst.ad.rel_o) # link addr-go direct to rel
 159         m.d.comb += ldst.st.go_i.eq(st_go_edge) # link store-go to rising rel
 160
 161         # PC and instruction from I-Memory
 162         pc_changed = Signal() # note write to PC
 163         comb += self.pc_o.eq(cur_state.pc)
 164         ilatch = Signal(32)
 165
 166         # next instruction (+4 on current)
 167         nia = Signal(64, reset_less=True)
 168         comb += nia.eq(cur_state.pc + 4)
 169
 170         # read the PC
 171         pc = Signal(64, reset_less=True)
 172         pc_ok_delay = Signal()
 173         sync += pc_ok_delay.eq(~self.pc_i.ok)
 174         with m.If(self.pc_i.ok):
 175             # incoming override (start from pc_i)
 176             comb += pc.eq(self.pc_i.data)
 177         with m.Else():
 178             # otherwise read StateRegs regfile for PC...
 179             comb += self.state_r_pc.ren.eq(1<<StateRegs.PC)
 180         # ... but on a 1-clock delay
 181         with m.If(pc_ok_delay):
 182             comb += pc.eq(self.state_r_pc.data_o)
 183
 184         # don't write pc every cycle
 185         comb += self.state_w_pc.wen.eq(0)
 186         comb += self.state_w_pc.data_i.eq(0)
 187
 188         # don't read msr every cycle
 189         comb += self.state_r_msr.ren.eq(0)
 190         msr_read = Signal(reset=1)
 191
 192         # connect up debug signals
 193         # TODO comb += core.icache_rst_i.eq(dbg.icache_rst_o)
 194         comb += dbg.terminate_i.eq(core.core_terminate_o)
 195         comb += dbg.state.pc.eq(pc)
 196         #comb += dbg.state.pc.eq(cur_state.pc)
 197         comb += dbg.state.msr.eq(cur_state.msr)
 198
 199         # temporaries
 200         core_busy_o = core.busy_o                 # core is busy
 201         core_ivalid_i = core.ivalid_i             # instruction is valid
 202         core_issue_i = core.issue_i               # instruction is issued
 203         dec_opcode_i = pdecode2.dec.raw_opcode_in # raw opcode
 204
 205         insn_type = core.e.do.insn_type
 206         dec_state = pdecode2.state
 207
 208         # actually use a nmigen FSM for the first time (w00t)
 209         # this FSM is perhaps unusual in that it detects conditions
 210         # then "holds" information, combinatorially, for the core
 211         # (as opposed to using sync - which would be on a clock's delay)
 212         # this includes the actual opcode, valid flags and so on.
 213         with m.FSM() as fsm:
 214
 215             # waiting (zzz)
 216             with m.State("IDLE"):
 217                 sync += pc_changed.eq(0)
 218                 sync += core.e.eq(0)
 219                 with m.If(~dbg.core_stop_o & ~core.core_reset_i):
 220                     # instruction allowed to go: start by reading the PC
 221                     # capture the PC and also drop it into Insn Memory
 222                     # we have joined a pair of combinatorial memory
 223                     # lookups together.  this is Generally Bad.
 224                     comb += self.imem.a_pc_i.eq(pc)
 225                     comb += self.imem.a_valid_i.eq(1)
 226                     comb += self.imem.f_valid_i.eq(1)
 227                     sync += cur_state.pc.eq(pc)
 228
 229                     # initiate read of MSR.  arrives one clock later
 230                     comb += self.state_r_msr.ren.eq(1<<StateRegs.MSR)
 231                     sync += msr_read.eq(0)
 232
 233                     m.next = "INSN_READ" # move to "wait for bus" phase
 234                 with m.Else():
 235                     comb += core.core_stopped_i.eq(1)
 236                     comb += dbg.core_stopped_i.eq(1)
 237
 238             # dummy pause to find out why simulation is not keeping up
 239             with m.State("INSN_READ"):
 240                 # one cycle later, msr read arrives.  valid only once.
 241                 with m.If(~msr_read):
 242                     sync += msr_read.eq(1) # yeah don't read it again
 243                     sync += cur_state.msr.eq(self.state_r_msr.data_o)
 244                 with m.If(self.imem.f_busy_o): # zzz...
 245                     # busy: stay in wait-read
 246                     comb += self.imem.a_valid_i.eq(1)
 247                     comb += self.imem.f_valid_i.eq(1)
 248                 with m.Else():
 249                     # not busy: instruction fetched
 250                     f_instr_o = self.imem.f_instr_o
 251                     if f_instr_o.width == 32:
 252                         insn = f_instr_o
 253                     else:
 254                         insn = f_instr_o.word_select(cur_state.pc[2], 32)
 255                     comb += dec_opcode_i.eq(insn) # actual opcode
 256                     comb += dec_state.eq(cur_state)
 257                     sync += core.e.eq(pdecode2.e)
 258                     sync += ilatch.eq(insn) # latch current insn
 259                     # also drop PC and MSR into decode "state"
 260                     m.next = "INSN_START" # move to "start"
 261
 262             # waiting for instruction bus (stays there until not busy)
 263             with m.State("INSN_START"):
 264                 comb += core_ivalid_i.eq(1) # instruction is valid
 265                 comb += core_issue_i.eq(1)  # and issued
 266
 267                 m.next = "INSN_ACTIVE" # move to "wait completion"
 268
 269             # instruction started: must wait till it finishes
 270             with m.State("INSN_ACTIVE"):
 271                 with m.If(insn_type != MicrOp.OP_NOP):
 272                     comb += core_ivalid_i.eq(1) # instruction is valid
 273                 with m.If(self.state_nia.wen & (1<<StateRegs.PC)):
 274                     sync += pc_changed.eq(1)
 275                 with m.If(~core_busy_o): # instruction done!
 276                     # ok here we are not reading the branch unit.  TODO
 277                     # this just blithely overwrites whatever pipeline
 278                     # updated the PC
 279                     with m.If(~pc_changed):
 280                         comb += self.state_w_pc.wen.eq(1<<StateRegs.PC)
 281                         comb += self.state_w_pc.data_i.eq(nia)
 282                     sync += core.e.eq(0)
 283                     m.next = "IDLE" # back to idle
 284
 285         # this bit doesn't have to be in the FSM: connect up to read
 286         # regfiles on demand from DMI
 287         with m.If(d_reg.req): # request for regfile access being made
 288             # TODO: error-check this
 289             # XXX should this be combinatorial?  sync better?
 290             if intrf.unary:
 291                 comb += self.int_r.ren.eq(1<<d_reg.addr)
 292             else:
 293                 comb += self.int_r.addr.eq(d_reg.addr)
 294                 comb += self.int_r.ren.eq(1)
 295         d_reg_delay  = Signal()
 296         sync += d_reg_delay.eq(d_reg.req)
 297         with m.If(d_reg_delay):
 298             # data arrives one clock later
 299             comb += d_reg.data.eq(self.int_r.data_o)
 300             comb += d_reg.ack.eq(1)
 301
 302         # sigh same thing for CR debug
 303         with m.If(d_cr.req): # request for regfile access being made
 304             comb += self.cr_r.ren.eq(0b11111111) # enable all
 305         d_cr_delay  = Signal()
 306         sync += d_cr_delay.eq(d_cr.req)
 307         with m.If(d_cr_delay):
 308             # data arrives one clock later
 309             comb += d_cr.data.eq(self.cr_r.data_o)
 310             comb += d_cr.ack.eq(1)
 311
 312         # aaand XER...
 313         with m.If(d_xer.req): # request for regfile access being made
 314             comb += self.xer_r.ren.eq(0b111111) # enable all
 315         d_xer_delay  = Signal()
 316         sync += d_xer_delay.eq(d_xer.req)
 317         with m.If(d_xer_delay):
 318             # data arrives one clock later
 319             comb += d_xer.data.eq(self.xer_r.data_o)
 320             comb += d_xer.ack.eq(1)
 321
 322         # DEC and TB inc/dec FSM
 323         self.tb_dec_fsm(m, cur_state.dec)
 324
 325         return m
 326
 327     def tb_dec_fsm(self, m, spr_dec):
 328         """tb_dec_fsm
 329
 330         this is a FSM for updating either dec or tb.  it runs alternately
 331         DEC, TB, DEC, TB.  note that SPR pipeline could have written a new
 332         value to DEC, however the regfile has "passthrough" on it so this
 333         *should* be ok.
 334
 335         see v3.0B p1097-1099 for Timeer Resource and p1065 and p1076
 336         """
 337
 338         comb, sync = m.d.comb, m.d.sync
 339         fast_rf = self.core.regs.rf['fast']
 340         fast_r_dectb = fast_rf.r_ports['issue'] # DEC/TB
 341         fast_w_dectb = fast_rf.w_ports['issue'] # DEC/TB
 342
 343         with m.FSM() as fsm:
 344
 345             # initiates read of current DEC
 346             with m.State("DEC_READ"):
 347                 comb += fast_r_dectb.addr.eq(FastRegs.DEC)
 348                 comb += fast_r_dectb.ren.eq(1)
 349                 m.next = "DEC_WRITE"
 350
 351             # waits for DEC read to arrive (1 cycle), updates with new value
 352             with m.State("DEC_WRITE"):
 353                 new_dec = Signal(64)
 354                 # TODO: MSR.LPCR 32-bit decrement mode
 355                 comb += new_dec.eq(fast_r_dectb.data_o - 1)
 356                 comb += fast_w_dectb.addr.eq(FastRegs.DEC)
 357                 comb += fast_w_dectb.wen.eq(1)
 358                 comb += fast_w_dectb.data_i.eq(new_dec)
 359                 sync += spr_dec.eq(new_dec) # copy into cur_state for decoder
 360                 m.next = "TB_READ"
 361
 362             # initiates read of current TB
 363             with m.State("TB_READ"):
 364                 comb += fast_r_dectb.addr.eq(FastRegs.TB)
 365                 comb += fast_r_dectb.ren.eq(1)
 366                 m.next = "TB_WRITE"
 367
 368             # waits for read TB to arrive, initiates write of current TB
 369             with m.State("TB_WRITE"):
 370                 new_tb = Signal(64)
 371                 comb += new_tb.eq(fast_r_dectb.data_o + 1)
 372                 comb += fast_w_dectb.addr.eq(FastRegs.TB)
 373                 comb += fast_w_dectb.wen.eq(1)
 374                 comb += fast_w_dectb.data_i.eq(new_tb)
 375                 m.next = "DEC_READ"
 376
 377         return m
 378
 379     def __iter__(self):
 380         yield from self.pc_i.ports()
 381         yield self.pc_o
 382         yield self.memerr_o
 383         yield from self.core.ports()
 384         yield from self.imem.ports()
 385         yield self.core_bigendian_i
 386         yield self.busy_o
 387
 388     def ports(self):
 389         return list(self)
 390
 391     def external_ports(self):
 392         ports = self.pc_i.ports()
 393         ports += [self.pc_o, self.memerr_o, self.core_bigendian_i, self.busy_o,
 394                   ClockSignal(), ResetSignal(),
 395                 ]
 396         ports += list(self.dbg.dmi.ports())
 397         ports += list(self.imem.ibus.fields.values())
 398         ports += list(self.core.l0.cmpi.lsmem.lsi.slavebus.fields.values())
 399
 400         if self.xics:
 401             ports += list(self.xics_icp.bus.fields.values())
 402             ports += list(self.xics_ics.bus.fields.values())
 403             ports.append(self.int_level_i)
 404
 405         if self.gpio:
 406             ports += list(self.simple_gpio.bus.fields.values())
 407             ports.append(self.gpio_o)
 408
 409         return ports
 410
 411     def ports(self):
 412         return list(self)
 413
 414
 415 if __name__ == '__main__':
 416     units = {'alu': 1, 'cr': 1, 'branch': 1, 'trap': 1, 'logical': 1,
 417              'spr': 1,
 418              'div': 1,
 419              'mul': 1,
 420              'shiftrot': 1
 421             }
 422     pspec = TestMemPspec(ldst_ifacetype='bare_wb',
 423                          imem_ifacetype='bare_wb',
 424                          addr_wid=48,
 425                          mask_wid=8,
 426                          reg_wid=64,
 427                          units=units)
 428     dut = TestIssuer(pspec)
 429     vl = main(dut, ports=dut.ports(), name="test_issuer")
 430
 431     if len(sys.argv) == 1:
 432         vl = rtlil.convert(dut, ports=dut.external_ports(), name="test_issuer")
 433         with open("test_issuer.il", "w") as f:
 434             f.write(vl)