src/soc/simple/issuer.py

   1 """simple core issuer
   2
   3 not in any way intended for production use.  this runs a FSM that:
   4
   5 * reads the Program Counter from StateRegs
   6 * reads an instruction from a fixed-size Test Memory
   7 * issues it to the Simple Core
   8 * waits for it to complete
   9 * increments the PC
  10 * does it all over again
  11
  12 the purpose of this module is to verify the functional correctness
  13 of the Function Units in the absolute simplest and clearest possible
  14 way, and to at provide something that can be further incrementally
  15 improved.
  16 """
  17
  18 from nmigen import (Elaboratable, Module, Signal, ClockSignal, ResetSignal,
  19                     ClockDomain, DomainRenamer)
  20 from nmigen.cli import rtlil
  21 from nmigen.cli import main
  22 import sys
  23
  24 from soc.decoder.decode2execute1 import Data
  25 from soc.experiment.testmem import TestMemory # test only for instructions
  26 from soc.regfile.regfiles import StateRegs
  27 from soc.simple.core import NonProductionCore
  28 from soc.config.test.test_loadstore import TestMemPspec
  29 from soc.config.ifetch import ConfigFetchUnit
  30 from soc.decoder.power_enums import MicrOp
  31 from soc.debug.dmi import CoreDebug, DMIInterface
  32 from soc.config.state import CoreState
  33
  34 from nmutil.util import rising_edge
  35
  36
  37 class TestIssuer(Elaboratable):
  38     """TestIssuer - reads instructions from TestMemory and issues them
  39
  40     efficiency and speed is not the main goal here: functional correctness is.
  41     """
  42     def __init__(self, pspec):
  43         # main instruction core
  44         self.core = core = NonProductionCore(pspec)
  45
  46         # Test Instruction memory
  47         self.imem = ConfigFetchUnit(pspec).fu
  48         # one-row cache of instruction read
  49         self.iline = Signal(64) # one instruction line
  50         self.iprev_adr = Signal(64) # previous address: if different, do read
  51
  52         # DMI interface
  53         self.dbg = CoreDebug()
  54
  55         # instruction go/monitor
  56         self.pc_o = Signal(64, reset_less=True)
  57         self.pc_i = Data(64, "pc_i") # set "ok" to indicate "please change me"
  58         self.core_bigendian_i = Signal()
  59         self.busy_o = Signal(reset_less=True)
  60         self.memerr_o = Signal(reset_less=True)
  61
  62         # FAST regfile read /write ports for PC and MSR
  63         self.state_r_pc = self.core.regs.rf['state'].r_ports['cia'] # PC rd
  64         self.state_w_pc = self.core.regs.rf['state'].w_ports['d_wr1'] # PC wr
  65         self.state_r_msr = self.core.regs.rf['state'].r_ports['msr'] # MSR rd
  66
  67         # DMI interface access
  68         intrf = self.core.regs.rf['int']
  69         self.int_r = intrf.r_ports['dmi'] # INT read
  70
  71         # hack method of keeping an eye on whether branch/trap set the PC
  72         self.state_nia = self.core.regs.rf['state'].w_ports['nia']
  73         self.state_nia.wen.name = 'state_nia_wen'
  74
  75     def elaborate(self, platform):
  76         m = Module()
  77         comb, sync = m.d.comb, m.d.sync
  78
  79         m.submodules.core = core = DomainRenamer("coresync")(self.core)
  80         m.submodules.imem = imem = self.imem
  81         m.submodules.dbg = dbg = self.dbg
  82
  83         # convenience
  84         dmi = dbg.dmi
  85         d_reg = dbg.dbg_gpr
  86         intrf = self.core.regs.rf['int']
  87
  88         # clock delay power-on reset
  89         cd_por  = ClockDomain(reset_less=True)
  90         cd_sync = ClockDomain()
  91         core_sync = ClockDomain("coresync")
  92         m.domains += cd_por, cd_sync, core_sync
  93
  94         delay = Signal(range(4), reset=1)
  95         with m.If(delay != 0):
  96             m.d.por += delay.eq(delay - 1)
  97         comb += cd_por.clk.eq(ClockSignal())
  98         comb += core_sync.clk.eq(ClockSignal())
  99         # XXX TODO: power-on reset delay (later)
 100         #comb += core.core_reset_i.eq(delay != 0 | dbg.core_rst_o)
 101
 102         # busy/halted signals from core
 103         comb += self.busy_o.eq(core.busy_o)
 104         comb += core.bigendian_i.eq(self.core_bigendian_i)
 105
 106         # current state (MSR/PC at the moment
 107         cur_state = CoreState("cur")
 108
 109         # temporary hack: says "go" immediately for both address gen and ST
 110         l0 = core.l0
 111         ldst = core.fus.fus['ldst0']
 112         st_go_edge = rising_edge(m, ldst.st.rel_o)
 113         m.d.comb += ldst.ad.go_i.eq(ldst.ad.rel_o) # link addr-go direct to rel
 114         m.d.comb += ldst.st.go_i.eq(st_go_edge) # link store-go to rising rel
 115
 116         # PC and instruction from I-Memory
 117         current_insn = Signal(32) # current fetched instruction (note sync)
 118         pc_changed = Signal() # note write to PC
 119         comb += self.pc_o.eq(cur_state.pc)
 120         ilatch = Signal(32)
 121
 122         # next instruction (+4 on current)
 123         nia = Signal(64, reset_less=True)
 124         comb += nia.eq(cur_state.pc + 4)
 125
 126         # read the PC
 127         pc = Signal(64, reset_less=True)
 128         with m.If(self.pc_i.ok):
 129             # incoming override (start from pc_i)
 130             comb += pc.eq(self.pc_i.data)
 131         with m.Else():
 132             # otherwise read StateRegs regfile for PC
 133             comb += self.state_r_pc.ren.eq(1<<StateRegs.PC)
 134             comb += pc.eq(self.state_r_pc.data_o)
 135
 136         # don't write pc every cycle
 137         sync += self.state_w_pc.wen.eq(0)
 138         sync += self.state_w_pc.data_i.eq(0)
 139
 140         # don't read msr every cycle
 141         sync += self.state_r_msr.ren.eq(0)
 142
 143         # connect up debug signals
 144         # TODO comb += core.icache_rst_i.eq(dbg.icache_rst_o)
 145         comb += core.core_stopped_i.eq(dbg.core_stop_o)
 146         comb += core.core_reset_i.eq(dbg.core_rst_o)
 147         comb += dbg.terminate_i.eq(core.core_terminate_o)
 148         comb += dbg.state.pc.eq(pc)
 149         comb += dbg.state.msr.eq(cur_state.msr)
 150
 151         # temporaries
 152         core_busy_o = core.busy_o         # core is busy
 153         core_ivalid_i = core.ivalid_i     # instruction is valid
 154         core_issue_i = core.issue_i       # instruction is issued
 155         core_be_i = core.bigendian_i      # bigendian mode
 156         core_opcode_i = core.raw_opcode_i # raw opcode
 157
 158         insn_type = core.pdecode2.e.do.insn_type
 159         insn_state = core.pdecode2.state
 160
 161         # actually use a nmigen FSM for the first time (w00t)
 162         # this FSM is perhaps unusual in that it detects conditions
 163         # then "holds" information, combinatorially, for the core
 164         # (as opposed to using sync - which would be on a clock's delay)
 165         # this includes the actual opcode, valid flags and so on.
 166         with m.FSM() as fsm:
 167
 168             # waiting (zzz)
 169             with m.State("IDLE"):
 170                 sync += pc_changed.eq(0)
 171                 with m.If(~dbg.core_stop_o):
 172                     # instruction allowed to go: start by reading the PC
 173                     # capture the PC and also drop it into Insn Memory
 174                     # we have joined a pair of combinatorial memory
 175                     # lookups together.  this is Generally Bad.
 176                     comb += self.imem.a_pc_i.eq(pc)
 177                     comb += self.imem.a_valid_i.eq(1)
 178                     comb += self.imem.f_valid_i.eq(1)
 179                     sync += cur_state.pc.eq(pc)
 180
 181                     # read MSR, latch it, and put it in decode "state"
 182                     sync += self.state_r_msr.ren.eq(1<<StateRegs.MSR)
 183                     sync += cur_state.msr.eq(self.state_r_msr.data_o)
 184
 185                     m.next = "INSN_READ" # move to "wait for bus" phase
 186
 187             # waiting for instruction bus (stays there until not busy)
 188             with m.State("INSN_READ"):
 189                 with m.If(self.imem.f_busy_o): # zzz...
 190                     # busy: stay in wait-read
 191                     comb += self.imem.a_valid_i.eq(1)
 192                     comb += self.imem.f_valid_i.eq(1)
 193                 with m.Else():
 194                     # not busy: instruction fetched
 195                     f_instr_o = self.imem.f_instr_o
 196                     if f_instr_o.width == 32:
 197                         insn = f_instr_o
 198                     else:
 199                         insn = f_instr_o.word_select(cur_state.pc[2], 32)
 200                     comb += current_insn.eq(insn)
 201                     comb += core_ivalid_i.eq(1) # instruction is valid
 202                     comb += core_issue_i.eq(1)  # and issued
 203                     comb += core_opcode_i.eq(current_insn) # actual opcode
 204                     sync += ilatch.eq(current_insn) # latch current insn
 205
 206                     # also drop PC and MSR into decode "state"
 207                     comb += insn_state.eq(cur_state)
 208
 209                     m.next = "INSN_ACTIVE" # move to "wait completion"
 210
 211             # instruction started: must wait till it finishes
 212             with m.State("INSN_ACTIVE"):
 213                 with m.If(insn_type != MicrOp.OP_NOP):
 214                     comb += core_ivalid_i.eq(1) # instruction is valid
 215                 comb += core_opcode_i.eq(ilatch) # actual opcode
 216                 comb += insn_state.eq(cur_state)     # and MSR and PC
 217                 with m.If(self.state_nia.wen):
 218                     sync += pc_changed.eq(1)
 219                 with m.If(~core_busy_o): # instruction done!
 220                     # ok here we are not reading the branch unit.  TODO
 221                     # this just blithely overwrites whatever pipeline
 222                     # updated the PC
 223                     with m.If(~pc_changed):
 224                         sync += self.state_w_pc.wen.eq(1<<StateRegs.PC)
 225                         sync += self.state_w_pc.data_i.eq(nia)
 226                     m.next = "IDLE" # back to idle
 227
 228         # this bit doesn't have to be in the FSM: connect up to read
 229         # regfiles on demand from DMI
 230
 231         with m.If(d_reg.req): # request for regfile access being made
 232             # TODO: error-check this
 233             # XXX should this be combinatorial?  sync better?
 234             if intrf.unary:
 235                 comb += self.int_r.ren.eq(1<<d_reg.addr)
 236             else:
 237                 comb += self.int_r.addr.eq(d_reg.addr)
 238                 comb += self.int_r.ren.eq(1)
 239             comb += d_reg.data.eq(self.int_r.data_o)
 240             comb += d_reg.ack.eq(1)
 241
 242         return m
 243
 244     def __iter__(self):
 245         yield from self.pc_i.ports()
 246         yield self.pc_o
 247         yield self.memerr_o
 248         yield from self.core.ports()
 249         yield from self.imem.ports()
 250         yield self.core_bigendian_i
 251         yield self.busy_o
 252
 253     def ports(self):
 254         return list(self)
 255
 256     def external_ports(self):
 257         return self.pc_i.ports() + [self.pc_o,
 258                                     self.memerr_o,
 259                                     self.core_bigendian_i,
 260                                     ClockSignal(),
 261                                     ResetSignal(),
 262                                     self.busy_o,
 263                                     ] + \
 264                 list(self.dbg.dmi.ports()) + \
 265                 list(self.imem.ibus.fields.values()) + \
 266                 list(self.core.l0.cmpi.lsmem.lsi.dbus.fields.values())
 267
 268     def ports(self):
 269         return list(self)
 270
 271
 272 if __name__ == '__main__':
 273     units = {'alu': 1, 'cr': 1, 'branch': 1, 'trap': 1, 'logical': 1,
 274              'spr': 1,
 275              'div': 1,
 276              'mul': 1,
 277              'shiftrot': 1
 278             }
 279     pspec = TestMemPspec(ldst_ifacetype='bare_wb',
 280                          imem_ifacetype='bare_wb',
 281                          addr_wid=48,
 282                          mask_wid=8,
 283                          reg_wid=64,
 284                          units=units)
 285     dut = TestIssuer(pspec)
 286     vl = main(dut, ports=dut.ports(), name="test_issuer")
 287
 288     if len(sys.argv) == 1:
 289         vl = rtlil.convert(dut, ports=dut.external_ports(), name="test_issuer")
 290         with open("test_issuer.il", "w") as f:
 291             f.write(vl)