src/soc/simple/issuer.py

   1 """simple core issuer
   2
   3 not in any way intended for production use.  this runs a FSM that:
   4
   5 * reads the Program Counter from StateRegs
   6 * reads an instruction from a fixed-size Test Memory
   7 * issues it to the Simple Core
   8 * waits for it to complete
   9 * increments the PC
  10 * does it all over again
  11
  12 the purpose of this module is to verify the functional correctness
  13 of the Function Units in the absolute simplest and clearest possible
  14 way, and to at provide something that can be further incrementally
  15 improved.
  16 """
  17
  18 from nmigen import (Elaboratable, Module, Signal, ClockSignal, ResetSignal,
  19                     ClockDomain, DomainRenamer, Mux, Const)
  20 from nmigen.cli import rtlil
  21 from nmigen.cli import main
  22 import sys
  23
  24 from soc.decoder.power_decoder import create_pdecode
  25 from soc.decoder.power_decoder2 import PowerDecode2, SVP64PrefixDecoder
  26 from soc.decoder.decode2execute1 import IssuerDecode2ToOperand
  27 from soc.decoder.decode2execute1 import Data
  28 from soc.experiment.testmem import TestMemory # test only for instructions
  29 from soc.regfile.regfiles import StateRegs, FastRegs
  30 from soc.simple.core import NonProductionCore
  31 from soc.config.test.test_loadstore import TestMemPspec
  32 from soc.config.ifetch import ConfigFetchUnit
  33 from soc.decoder.power_enums import MicrOp
  34 from soc.debug.dmi import CoreDebug, DMIInterface
  35 from soc.debug.jtag import JTAG
  36 from soc.config.pinouts import get_pinspecs
  37 from soc.config.state import CoreState
  38 from soc.interrupts.xics import XICS_ICP, XICS_ICS
  39 from soc.bus.simple_gpio import SimpleGPIO
  40 from soc.bus.SPBlock512W64B8W import SPBlock512W64B8W
  41 from soc.clock.select import ClockSelect
  42 from soc.clock.dummypll import DummyPLL
  43 from soc.sv.svstate import SVSTATERec
  44
  45
  46 from nmutil.util import rising_edge
  47
  48 def get_insn(f_instr_o, pc):
  49     if f_instr_o.width == 32:
  50         return f_instr_o
  51     else:
  52         # 64-bit: bit 2 of pc decides which word to select
  53         return f_instr_o.word_select(pc[2], 32)
  54
  55
  56 class TestIssuerInternal(Elaboratable):
  57     """TestIssuer - reads instructions from TestMemory and issues them
  58
  59     efficiency and speed is not the main goal here: functional correctness is.
  60     """
  61     def __init__(self, pspec):
  62
  63         # JTAG interface.  add this right at the start because if it's
  64         # added it *modifies* the pspec, by adding enable/disable signals
  65         # for parts of the rest of the core
  66         self.jtag_en = hasattr(pspec, "debug") and pspec.debug == 'jtag'
  67         if self.jtag_en:
  68             subset = {'uart', 'mtwi', 'eint', 'gpio', 'mspi0', 'mspi1',
  69                       'pwm', 'sd0', 'sdr'}
  70             self.jtag = JTAG(get_pinspecs(subset=subset))
  71             # add signals to pspec to enable/disable icache and dcache
  72             # (or data and intstruction wishbone if icache/dcache not included)
  73             # https://bugs.libre-soc.org/show_bug.cgi?id=520
  74             # TODO: do we actually care if these are not domain-synchronised?
  75             # honestly probably not.
  76             pspec.wb_icache_en = self.jtag.wb_icache_en
  77             pspec.wb_dcache_en = self.jtag.wb_dcache_en
  78             self.wb_sram_en = self.jtag.wb_sram_en
  79         else:
  80             self.wb_sram_en = Const(1)
  81
  82         # add 4k sram blocks?
  83         self.sram4x4k = (hasattr(pspec, "sram4x4kblock") and
  84                          pspec.sram4x4kblock == True)
  85         if self.sram4x4k:
  86             self.sram4k = []
  87             for i in range(4):
  88                 self.sram4k.append(SPBlock512W64B8W(name="sram4k_%d" % i))
  89
  90         # add interrupt controller?
  91         self.xics = hasattr(pspec, "xics") and pspec.xics == True
  92         if self.xics:
  93             self.xics_icp = XICS_ICP()
  94             self.xics_ics = XICS_ICS()
  95             self.int_level_i = self.xics_ics.int_level_i
  96
  97         # add GPIO peripheral?
  98         self.gpio = hasattr(pspec, "gpio") and pspec.gpio == True
  99         if self.gpio:
 100             self.simple_gpio = SimpleGPIO()
 101             self.gpio_o = self.simple_gpio.gpio_o
 102
 103         # main instruction core25
 104         self.core = core = NonProductionCore(pspec)
 105
 106         # instruction decoder.  goes into Trap Record
 107         pdecode = create_pdecode()
 108         self.cur_state = CoreState("cur") # current state (MSR/PC/EINT/SVSTATE)
 109         self.pdecode2 = PowerDecode2(pdecode, state=self.cur_state,
 110                                      opkls=IssuerDecode2ToOperand)
 111         self.svp64 = SVP64PrefixDecoder() # for decoding SVP64 prefix
 112
 113         # Test Instruction memory
 114         self.imem = ConfigFetchUnit(pspec).fu
 115         # one-row cache of instruction read
 116         self.iline = Signal(64) # one instruction line
 117         self.iprev_adr = Signal(64) # previous address: if different, do read
 118
 119         # DMI interface
 120         self.dbg = CoreDebug()
 121
 122         # instruction go/monitor
 123         self.pc_o = Signal(64, reset_less=True)
 124         self.pc_i = Data(64, "pc_i") # set "ok" to indicate "please change me"
 125         self.svstate_i = Data(32, "svstate_i") # ditto
 126         self.core_bigendian_i = Signal()
 127         self.busy_o = Signal(reset_less=True)
 128         self.memerr_o = Signal(reset_less=True)
 129
 130         # STATE regfile read /write ports for PC, MSR, SVSTATE
 131         staterf = self.core.regs.rf['state']
 132         self.state_r_pc = staterf.r_ports['cia'] # PC rd
 133         self.state_w_pc = staterf.w_ports['d_wr1'] # PC wr
 134         self.state_r_msr = staterf.r_ports['msr'] # MSR rd
 135         self.state_r_sv = staterf.r_ports['sv'] # SVSTATE rd
 136         self.state_w_sv = staterf.w_ports['sv'] # SVSTATE wr
 137
 138         # DMI interface access
 139         intrf = self.core.regs.rf['int']
 140         crrf = self.core.regs.rf['cr']
 141         xerrf = self.core.regs.rf['xer']
 142         self.int_r = intrf.r_ports['dmi'] # INT read
 143         self.cr_r = crrf.r_ports['full_cr_dbg'] # CR read
 144         self.xer_r = xerrf.r_ports['full_xer'] # XER read
 145
 146         # hack method of keeping an eye on whether branch/trap set the PC
 147         self.state_nia = self.core.regs.rf['state'].w_ports['nia']
 148         self.state_nia.wen.name = 'state_nia_wen'
 149
 150     def fetch_fsm(self, m, core, dbg, pc, svstate, pc_changed, insn_done,
 151                         core_rst, cur_state,
 152                         fetch_pc_ready_o, fetch_pc_valid_i,
 153                         fetch_insn_valid_o, fetch_insn_ready_i):
 154         """fetch FSM
 155         this FSM performs fetch of raw instruction data, partial-decodes
 156         it 32-bit at a time to detect SVP64 prefixes, and will optionally
 157         read a 2nd 32-bit quantity if that occurs.
 158         """
 159         comb = m.d.comb
 160         sync = m.d.sync
 161         pdecode2 = self.pdecode2
 162         svp64 = self.svp64
 163
 164         # latches copy of raw fetched instruction
 165         fetch_insn_o = Signal(32, reset_less=True)
 166         dec_opcode_i = pdecode2.dec.raw_opcode_in # raw opcode
 167         sync += dec_opcode_i.eq(fetch_insn_o)  # actual opcode
 168
 169         msr_read = Signal(reset=1)
 170
 171         # address of the next instruction, in the absence of a branch
 172         # depends on the instruction size
 173         nia = Signal(64, reset_less=True)
 174
 175         with m.FSM(name='fetch_fsm'):
 176
 177             # waiting (zzz)
 178             with m.State("IDLE"):
 179                 with m.If(~dbg.core_stop_o & ~core_rst):
 180                     comb += fetch_pc_ready_o.eq(1)
 181                     with m.If(fetch_pc_valid_i):
 182                         # instruction allowed to go: start by reading the PC
 183                         # capture the PC and also drop it into Insn Memory
 184                         # we have joined a pair of combinatorial memory
 185                         # lookups together.  this is Generally Bad.
 186                         comb += self.imem.a_pc_i.eq(pc)
 187                         comb += self.imem.a_valid_i.eq(1)
 188                         comb += self.imem.f_valid_i.eq(1)
 189                         sync += cur_state.pc.eq(pc)
 190                         sync += cur_state.svstate.eq(svstate) # and svstate
 191
 192                         # initiate read of MSR. arrives one clock later
 193                         comb += self.state_r_msr.ren.eq(1 << StateRegs.MSR)
 194                         sync += msr_read.eq(0)
 195
 196                         m.next = "INSN_READ"  # move to "wait for bus" phase
 197                 with m.Else():
 198                     comb += core.core_stopped_i.eq(1)
 199                     comb += dbg.core_stopped_i.eq(1)
 200
 201             # dummy pause to find out why simulation is not keeping up
 202             with m.State("INSN_READ"):
 203                 # one cycle later, msr/sv read arrives.  valid only once.
 204                 with m.If(~msr_read):
 205                     sync += msr_read.eq(1) # yeah don't read it again
 206                     sync += cur_state.msr.eq(self.state_r_msr.data_o)
 207                 with m.If(self.imem.f_busy_o): # zzz...
 208                     # busy: stay in wait-read
 209                     comb += self.imem.a_valid_i.eq(1)
 210                     comb += self.imem.f_valid_i.eq(1)
 211                 with m.Else():
 212                     # not busy: instruction fetched
 213                     insn = get_insn(self.imem.f_instr_o, cur_state.pc)
 214                     # decode the SVP64 prefix, if any
 215                     comb += svp64.raw_opcode_in.eq(insn)
 216                     comb += svp64.bigendian.eq(self.core_bigendian_i)
 217                     # pass the decoded prefix (if any) to PowerDecoder2
 218                     sync += pdecode2.sv_rm.eq(svp64.svp64_rm)
 219                     # calculate the address of the following instruction
 220                     insn_size = Mux(svp64.is_svp64_mode, 8, 4)
 221                     sync += nia.eq(cur_state.pc + insn_size)
 222                     with m.If(~svp64.is_svp64_mode):
 223                         # with no prefix, store the instruction
 224                         # and hand it directly to the next FSM
 225                         comb += fetch_insn_o.eq(insn)
 226                         m.next = "INSN_READY"
 227                     with m.Else():
 228                         # fetch the rest of the instruction from memory
 229                         comb += self.imem.a_pc_i.eq(cur_state.pc + 4)
 230                         comb += self.imem.a_valid_i.eq(1)
 231                         comb += self.imem.f_valid_i.eq(1)
 232                         m.next = "INSN_READ2"
 233
 234             with m.State("INSN_READ2"):
 235                 with m.If(self.imem.f_busy_o):  # zzz...
 236                     # busy: stay in wait-read
 237                     comb += self.imem.a_valid_i.eq(1)
 238                     comb += self.imem.f_valid_i.eq(1)
 239                 with m.Else():
 240                     # not busy: instruction fetched
 241                     insn = get_insn(self.imem.f_instr_o, cur_state.pc+4)
 242                     comb += fetch_insn_o.eq(insn)
 243                     m.next = "INSN_READY"
 244
 245             with m.State("INSN_READY"):
 246                 # hand over the instruction, to be decoded
 247                 comb += fetch_insn_valid_o.eq(1)
 248                 with m.If(fetch_insn_ready_i):
 249                     m.next = "IDLE"
 250
 251         # code-morph: moving the actual PC-setting out of "execute"
 252         # so that it's easier to move this into an "issue" FSM.
 253
 254         # ok here we are not reading the branch unit.  TODO
 255         # this just blithely overwrites whatever pipeline
 256         # updated the PC
 257         core_busy_o = core.busy_o                 # core is busy
 258         with m.If(insn_done & (~pc_changed) & (~core_busy_o)):
 259             comb += self.state_w_pc.wen.eq(1<<StateRegs.PC)
 260             comb += self.state_w_pc.data_i.eq(nia)
 261
 262     def issue_fsm(self, m, core, cur_state, pc_changed, sv_changed,
 263                   fetch_pc_ready_o, fetch_pc_valid_i,
 264                   fetch_insn_valid_o, fetch_insn_ready_i,
 265                   exec_insn_valid_i, exec_insn_ready_o,
 266                   exec_pc_valid_o, exec_pc_ready_i):
 267         """issue FSM
 268
 269         decode / issue FSM.  this interacts with the "fetch" FSM
 270         through fetch_insn_ready/valid (incoming) and fetch_pc_ready/valid
 271         (outgoing). also interacts with the "execute" FSM
 272         through exec_insn_ready/valid (outgoing) and exec_pc_ready/valid
 273         (incoming).
 274         SVP64 RM prefixes have already been set up by the
 275         "fetch" phase, so execute is fairly straightforward.
 276         """
 277
 278         comb = m.d.comb
 279         sync = m.d.sync
 280         pdecode2 = self.pdecode2
 281
 282         # temporaries
 283         dec_opcode_i = pdecode2.dec.raw_opcode_in # raw opcode
 284
 285         # for updating svstate (things like srcstep etc.)
 286         update_svstate = Signal() # set this (below) if updating
 287         new_svstate = SVSTATERec("new_svstate")
 288         comb += new_svstate.eq(cur_state.svstate)
 289
 290         with m.FSM(name="issue_fsm"):
 291
 292             # go fetch the instruction at the current PC
 293             # at this point, there is no instruction running, that
 294             # could inadvertently update the PC.
 295             with m.State("INSN_FETCH"):
 296                 # TODO: update PC here, before fetch
 297                 comb += fetch_pc_valid_i.eq(1)
 298                 with m.If(fetch_pc_ready_o):
 299                     m.next = "INSN_WAIT"
 300
 301             # decode the instruction when it arrives
 302             with m.State("INSN_WAIT"):
 303                 comb += fetch_insn_ready_i.eq(1)
 304                 with m.If(fetch_insn_valid_o):
 305                     # decode the instruction
 306                     sync += core.e.eq(pdecode2.e)
 307                     sync += core.state.eq(cur_state)
 308                     sync += core.raw_insn_i.eq(dec_opcode_i)
 309                     sync += core.bigendian_i.eq(self.core_bigendian_i)
 310                     # TODO: loop into INSN_FETCH if it's a vector instruction
 311                     #       and VL == 0.  this because VL==0 is a for-loop
 312                     #       from 0 to 0 i.e. always, always a NOP.
 313                     m.next = "INSN_EXECUTE"  # move to "execute"
 314
 315             with m.State("INSN_EXECUTE"):
 316                 comb += exec_insn_valid_i.eq(1)
 317                 with m.If(exec_insn_ready_o):
 318                     m.next = "EXECUTE_WAIT"
 319
 320             with m.State("EXECUTE_WAIT"):
 321                 comb += exec_pc_ready_i.eq(1)
 322                 with m.If(exec_pc_valid_o):
 323                     # TODO: update SRCSTEP here (in new_svstate)
 324                     #       and set update_svstate to True *as long as*
 325                     #       PC / SVSTATE was not modified.  that's an
 326                     #       exception (or setvl was called)
 327                     # TODO: loop into INSN_EXECUTE if it's a vector instruction
 328                     #       and SRCSTEP != VL-1 and PowerDecoder.no_out_vec
 329                     #       is True
 330                     #       unless PC / SVSTATE was modified, in that case do
 331                     #       go back to INSN_FETCH.
 332                     m.next = "INSN_FETCH"
 333
 334         # check if svstate needs updating: if so, write it to State Regfile
 335         with m.If(update_svstate):
 336             comb += self.state_w_sv.wen.eq(1<<StateRegs.SVSTATE)
 337             comb += self.state_w_sv.data_i.eq(new_svstate)
 338             sync += cur_state.svstate.eq(new_svstate) # for next clock
 339
 340     def execute_fsm(self, m, core, insn_done, pc_changed, sv_changed,
 341                     exec_insn_valid_i, exec_insn_ready_o,
 342                     exec_pc_valid_o, exec_pc_ready_i):
 343         """execute FSM
 344
 345         execute FSM. this interacts with the "issue" FSM
 346         through exec_insn_ready/valid (incoming) and exec_pc_ready/valid
 347         (outgoing). SVP64 RM prefixes have already been set up by the
 348         "issue" phase, so execute is fairly straightforward.
 349         """
 350
 351         comb = m.d.comb
 352         sync = m.d.sync
 353         pdecode2 = self.pdecode2
 354         svp64 = self.svp64
 355
 356         # temporaries
 357         core_busy_o = core.busy_o                 # core is busy
 358         core_ivalid_i = core.ivalid_i             # instruction is valid
 359         core_issue_i = core.issue_i               # instruction is issued
 360         insn_type = core.e.do.insn_type           # instruction MicroOp type
 361
 362         with m.FSM(name="exec_fsm"):
 363
 364             # waiting for instruction bus (stays there until not busy)
 365             with m.State("INSN_START"):
 366                 comb += exec_insn_ready_o.eq(1)
 367                 with m.If(exec_insn_valid_i):
 368                     comb += core_ivalid_i.eq(1)  # instruction is valid
 369                     comb += core_issue_i.eq(1)  # and issued
 370                     m.next = "INSN_ACTIVE"  # move to "wait completion"
 371
 372             # instruction started: must wait till it finishes
 373             with m.State("INSN_ACTIVE"):
 374                 with m.If(insn_type != MicrOp.OP_NOP):
 375                     comb += core_ivalid_i.eq(1) # instruction is valid
 376                 # note changes to PC and SVSTATE
 377                 with m.If(self.state_nia.wen & (1<<StateRegs.SVSTATE)):
 378                     sync += sv_changed.eq(1)
 379                 with m.If(self.state_nia.wen & (1<<StateRegs.PC)):
 380                     sync += pc_changed.eq(1)
 381                 with m.If(~core_busy_o): # instruction done!
 382                     comb += insn_done.eq(1)
 383                     sync += core.e.eq(0)
 384                     sync += core.raw_insn_i.eq(0)
 385                     sync += core.bigendian_i.eq(0)
 386                     sync += sv_changed.eq(0)
 387                     sync += pc_changed.eq(0)
 388                     comb += exec_pc_valid_o.eq(1)
 389                     with m.If(exec_pc_ready_i):
 390                         m.next = "INSN_START"  # back to fetch
 391
 392     def elaborate(self, platform):
 393         m = Module()
 394         comb, sync = m.d.comb, m.d.sync
 395
 396         m.submodules.core = core = DomainRenamer("coresync")(self.core)
 397         m.submodules.imem = imem = self.imem
 398         m.submodules.dbg = dbg = self.dbg
 399         if self.jtag_en:
 400             m.submodules.jtag = jtag = self.jtag
 401             # TODO: UART2GDB mux, here, from external pin
 402             # see https://bugs.libre-soc.org/show_bug.cgi?id=499
 403             sync += dbg.dmi.connect_to(jtag.dmi)
 404
 405         cur_state = self.cur_state
 406
 407         # 4x 4k SRAM blocks.  these simply "exist", they get routed in litex
 408         if self.sram4x4k:
 409             for i, sram in enumerate(self.sram4k):
 410                 m.submodules["sram4k_%d" % i] = sram
 411                 comb += sram.enable.eq(self.wb_sram_en)
 412
 413         # XICS interrupt handler
 414         if self.xics:
 415             m.submodules.xics_icp = icp = self.xics_icp
 416             m.submodules.xics_ics = ics = self.xics_ics
 417             comb += icp.ics_i.eq(ics.icp_o)           # connect ICS to ICP
 418             sync += cur_state.eint.eq(icp.core_irq_o) # connect ICP to core
 419
 420         # GPIO test peripheral
 421         if self.gpio:
 422             m.submodules.simple_gpio = simple_gpio = self.simple_gpio
 423
 424         # connect one GPIO output to ICS bit 15 (like in microwatt soc.vhdl)
 425         # XXX causes litex ECP5 test to get wrong idea about input and output
 426         # (but works with verilator sim *sigh*)
 427         #if self.gpio and self.xics:
 428         #   comb += self.int_level_i[15].eq(simple_gpio.gpio_o[0])
 429
 430         # instruction decoder
 431         pdecode = create_pdecode()
 432         m.submodules.dec2 = pdecode2 = self.pdecode2
 433         m.submodules.svp64 = svp64 = self.svp64
 434
 435         # convenience
 436         dmi, d_reg, d_cr, d_xer, = dbg.dmi, dbg.d_gpr, dbg.d_cr, dbg.d_xer
 437         intrf = self.core.regs.rf['int']
 438
 439         # clock delay power-on reset
 440         cd_por  = ClockDomain(reset_less=True)
 441         cd_sync = ClockDomain()
 442         core_sync = ClockDomain("coresync")
 443         m.domains += cd_por, cd_sync, core_sync
 444
 445         ti_rst = Signal(reset_less=True)
 446         delay = Signal(range(4), reset=3)
 447         with m.If(delay != 0):
 448             m.d.por += delay.eq(delay - 1)
 449         comb += cd_por.clk.eq(ClockSignal())
 450
 451         # power-on reset delay
 452         core_rst = ResetSignal("coresync")
 453         comb += ti_rst.eq(delay != 0 | dbg.core_rst_o | ResetSignal())
 454         comb += core_rst.eq(ti_rst)
 455
 456         # busy/halted signals from core
 457         comb += self.busy_o.eq(core.busy_o)
 458         comb += pdecode2.dec.bigendian.eq(self.core_bigendian_i)
 459
 460         # temporary hack: says "go" immediately for both address gen and ST
 461         l0 = core.l0
 462         ldst = core.fus.fus['ldst0']
 463         st_go_edge = rising_edge(m, ldst.st.rel_o)
 464         m.d.comb += ldst.ad.go_i.eq(ldst.ad.rel_o) # link addr-go direct to rel
 465         m.d.comb += ldst.st.go_i.eq(st_go_edge) # link store-go to rising rel
 466
 467         # PC and instruction from I-Memory
 468         comb += self.pc_o.eq(cur_state.pc)
 469         pc_changed = Signal() # note write to PC
 470         sv_changed = Signal() # note write to SVSTATE
 471         insn_done = Signal()  # fires just once
 472
 473         # read the PC
 474         pc = Signal(64, reset_less=True)
 475         pc_ok_delay = Signal()
 476         sync += pc_ok_delay.eq(~self.pc_i.ok)
 477         with m.If(self.pc_i.ok):
 478             # incoming override (start from pc_i)
 479             comb += pc.eq(self.pc_i.data)
 480         with m.Else():
 481             # otherwise read StateRegs regfile for PC...
 482             comb += self.state_r_pc.ren.eq(1<<StateRegs.PC)
 483         # ... but on a 1-clock delay
 484         with m.If(pc_ok_delay):
 485             comb += pc.eq(self.state_r_pc.data_o)
 486
 487         # read svstate
 488         svstate = Signal(64, reset_less=True)
 489         svstate_ok_delay = Signal()
 490         sync += svstate_ok_delay.eq(~self.svstate_i.ok)
 491         with m.If(self.svstate_i.ok):
 492             # incoming override (start from svstate__i)
 493             comb += svstate.eq(self.svstate_i.data)
 494         with m.Else():
 495             # otherwise read StateRegs regfile for SVSTATE...
 496             comb += self.state_r_sv.ren.eq(1 << StateRegs.SVSTATE)
 497         # ... but on a 1-clock delay
 498         with m.If(svstate_ok_delay):
 499             comb += svstate.eq(self.state_r_sv.data_o)
 500
 501         # don't write pc every cycle
 502         comb += self.state_w_pc.wen.eq(0)
 503         comb += self.state_w_pc.data_i.eq(0)
 504
 505         # don't read msr every cycle
 506         comb += self.state_r_msr.ren.eq(0)
 507
 508         # connect up debug signals
 509         # TODO comb += core.icache_rst_i.eq(dbg.icache_rst_o)
 510         comb += dbg.terminate_i.eq(core.core_terminate_o)
 511         comb += dbg.state.pc.eq(pc)
 512         comb += dbg.state.svstate.eq(svstate)
 513         comb += dbg.state.msr.eq(cur_state.msr)
 514
 515         # there are *TWO* FSMs, one fetch (32/64-bit) one decode/execute.
 516         # these are the handshake signals between fetch and decode/execute
 517
 518         # fetch FSM can run as soon as the PC is valid
 519         fetch_pc_valid_i = Signal() # Execute tells Fetch "start next read"
 520         fetch_pc_ready_o = Signal() # Fetch Tells SVSTATE "proceed"
 521
 522         # fetch FSM hands over the instruction to be decoded / issued
 523         fetch_insn_valid_o = Signal()
 524         fetch_insn_ready_i = Signal()
 525
 526         # issue FSM delivers the instruction to the be executed
 527         exec_insn_valid_i = Signal()
 528         exec_insn_ready_o = Signal()
 529
 530         # execute FSM, hands over the PC/SVSTATE back to the issue FSM
 531         exec_pc_valid_o = Signal()
 532         exec_pc_ready_i = Signal()
 533
 534         # actually use a nmigen FSM for the first time (w00t)
 535         # this FSM is perhaps unusual in that it detects conditions
 536         # then "holds" information, combinatorially, for the core
 537         # (as opposed to using sync - which would be on a clock's delay)
 538         # this includes the actual opcode, valid flags and so on.
 539
 540         self.fetch_fsm(m, core, dbg, pc, svstate, pc_changed, insn_done,
 541                        core_rst, cur_state,
 542                        fetch_pc_ready_o, fetch_pc_valid_i,
 543                        fetch_insn_valid_o, fetch_insn_ready_i)
 544
 545         # TODO: an SVSTATE-based for-loop FSM that goes in between
 546         # fetch pc/insn ready/valid and advances SVSTATE.srcstep
 547         # until it reaches VL-1 or PowerDecoder2.no_out_vec is True.
 548         self.issue_fsm(m, core, cur_state, pc_changed, sv_changed,
 549                        fetch_pc_ready_o, fetch_pc_valid_i,
 550                        fetch_insn_valid_o, fetch_insn_ready_i,
 551                        exec_insn_valid_i, exec_insn_ready_o,
 552                        exec_pc_ready_i, exec_pc_valid_o)
 553
 554         self.execute_fsm(m, core, insn_done, pc_changed, sv_changed,
 555                          exec_insn_valid_i, exec_insn_ready_o,
 556                          exec_pc_ready_i, exec_pc_valid_o)
 557
 558         # this bit doesn't have to be in the FSM: connect up to read
 559         # regfiles on demand from DMI
 560         with m.If(d_reg.req): # request for regfile access being made
 561             # TODO: error-check this
 562             # XXX should this be combinatorial?  sync better?
 563             if intrf.unary:
 564                 comb += self.int_r.ren.eq(1<<d_reg.addr)
 565             else:
 566                 comb += self.int_r.addr.eq(d_reg.addr)
 567                 comb += self.int_r.ren.eq(1)
 568         d_reg_delay  = Signal()
 569         sync += d_reg_delay.eq(d_reg.req)
 570         with m.If(d_reg_delay):
 571             # data arrives one clock later
 572             comb += d_reg.data.eq(self.int_r.data_o)
 573             comb += d_reg.ack.eq(1)
 574
 575         # sigh same thing for CR debug
 576         with m.If(d_cr.req): # request for regfile access being made
 577             comb += self.cr_r.ren.eq(0b11111111) # enable all
 578         d_cr_delay  = Signal()
 579         sync += d_cr_delay.eq(d_cr.req)
 580         with m.If(d_cr_delay):
 581             # data arrives one clock later
 582             comb += d_cr.data.eq(self.cr_r.data_o)
 583             comb += d_cr.ack.eq(1)
 584
 585         # aaand XER...
 586         with m.If(d_xer.req): # request for regfile access being made
 587             comb += self.xer_r.ren.eq(0b111111) # enable all
 588         d_xer_delay  = Signal()
 589         sync += d_xer_delay.eq(d_xer.req)
 590         with m.If(d_xer_delay):
 591             # data arrives one clock later
 592             comb += d_xer.data.eq(self.xer_r.data_o)
 593             comb += d_xer.ack.eq(1)
 594
 595         # DEC and TB inc/dec FSM.  copy of DEC is put into CoreState,
 596         # (which uses that in PowerDecoder2 to raise 0x900 exception)
 597         self.tb_dec_fsm(m, cur_state.dec)
 598
 599         return m
 600
 601     def tb_dec_fsm(self, m, spr_dec):
 602         """tb_dec_fsm
 603
 604         this is a FSM for updating either dec or tb.  it runs alternately
 605         DEC, TB, DEC, TB.  note that SPR pipeline could have written a new
 606         value to DEC, however the regfile has "passthrough" on it so this
 607         *should* be ok.
 608
 609         see v3.0B p1097-1099 for Timeer Resource and p1065 and p1076
 610         """
 611
 612         comb, sync = m.d.comb, m.d.sync
 613         fast_rf = self.core.regs.rf['fast']
 614         fast_r_dectb = fast_rf.r_ports['issue'] # DEC/TB
 615         fast_w_dectb = fast_rf.w_ports['issue'] # DEC/TB
 616
 617         with m.FSM() as fsm:
 618
 619             # initiates read of current DEC
 620             with m.State("DEC_READ"):
 621                 comb += fast_r_dectb.addr.eq(FastRegs.DEC)
 622                 comb += fast_r_dectb.ren.eq(1)
 623                 m.next = "DEC_WRITE"
 624
 625             # waits for DEC read to arrive (1 cycle), updates with new value
 626             with m.State("DEC_WRITE"):
 627                 new_dec = Signal(64)
 628                 # TODO: MSR.LPCR 32-bit decrement mode
 629                 comb += new_dec.eq(fast_r_dectb.data_o - 1)
 630                 comb += fast_w_dectb.addr.eq(FastRegs.DEC)
 631                 comb += fast_w_dectb.wen.eq(1)
 632                 comb += fast_w_dectb.data_i.eq(new_dec)
 633                 sync += spr_dec.eq(new_dec) # copy into cur_state for decoder
 634                 m.next = "TB_READ"
 635
 636             # initiates read of current TB
 637             with m.State("TB_READ"):
 638                 comb += fast_r_dectb.addr.eq(FastRegs.TB)
 639                 comb += fast_r_dectb.ren.eq(1)
 640                 m.next = "TB_WRITE"
 641
 642             # waits for read TB to arrive, initiates write of current TB
 643             with m.State("TB_WRITE"):
 644                 new_tb = Signal(64)
 645                 comb += new_tb.eq(fast_r_dectb.data_o + 1)
 646                 comb += fast_w_dectb.addr.eq(FastRegs.TB)
 647                 comb += fast_w_dectb.wen.eq(1)
 648                 comb += fast_w_dectb.data_i.eq(new_tb)
 649                 m.next = "DEC_READ"
 650
 651         return m
 652
 653     def __iter__(self):
 654         yield from self.pc_i.ports()
 655         yield self.pc_o
 656         yield self.memerr_o
 657         yield from self.core.ports()
 658         yield from self.imem.ports()
 659         yield self.core_bigendian_i
 660         yield self.busy_o
 661
 662     def ports(self):
 663         return list(self)
 664
 665     def external_ports(self):
 666         ports = self.pc_i.ports()
 667         ports += [self.pc_o, self.memerr_o, self.core_bigendian_i, self.busy_o,
 668                 ]
 669
 670         if self.jtag_en:
 671             ports += list(self.jtag.external_ports())
 672         else:
 673             # don't add DMI if JTAG is enabled
 674             ports += list(self.dbg.dmi.ports())
 675
 676         ports += list(self.imem.ibus.fields.values())
 677         ports += list(self.core.l0.cmpi.lsmem.lsi.slavebus.fields.values())
 678
 679         if self.sram4x4k:
 680             for sram in self.sram4k:
 681                 ports += list(sram.bus.fields.values())
 682
 683         if self.xics:
 684             ports += list(self.xics_icp.bus.fields.values())
 685             ports += list(self.xics_ics.bus.fields.values())
 686             ports.append(self.int_level_i)
 687
 688         if self.gpio:
 689             ports += list(self.simple_gpio.bus.fields.values())
 690             ports.append(self.gpio_o)
 691
 692         return ports
 693
 694     def ports(self):
 695         return list(self)
 696
 697
 698 class TestIssuer(Elaboratable):
 699     def __init__(self, pspec):
 700         self.ti = TestIssuerInternal(pspec)
 701
 702         self.pll = DummyPLL()
 703
 704         # PLL direct clock or not
 705         self.pll_en = hasattr(pspec, "use_pll") and pspec.use_pll
 706         if self.pll_en:
 707             self.pll_18_o = Signal(reset_less=True)
 708
 709     def elaborate(self, platform):
 710         m = Module()
 711         comb = m.d.comb
 712
 713         # TestIssuer runs at direct clock
 714         m.submodules.ti = ti = self.ti
 715         cd_int = ClockDomain("coresync")
 716
 717         if self.pll_en:
 718             # ClockSelect runs at PLL output internal clock rate
 719             m.submodules.pll = pll = self.pll
 720
 721             # add clock domains from PLL
 722             cd_pll = ClockDomain("pllclk")
 723             m.domains += cd_pll
 724
 725             # PLL clock established.  has the side-effect of running clklsel
 726             # at the PLL's speed (see DomainRenamer("pllclk") above)
 727             pllclk = ClockSignal("pllclk")
 728             comb += pllclk.eq(pll.clk_pll_o)
 729
 730             # wire up external 24mhz to PLL
 731             comb += pll.clk_24_i.eq(ClockSignal())
 732
 733             # output 18 mhz PLL test signal
 734             comb += self.pll_18_o.eq(pll.pll_18_o)
 735
 736             # now wire up ResetSignals.  don't mind them being in this domain
 737             pll_rst = ResetSignal("pllclk")
 738             comb += pll_rst.eq(ResetSignal())
 739
 740         # internal clock is set to selector clock-out.  has the side-effect of
 741         # running TestIssuer at this speed (see DomainRenamer("intclk") above)
 742         intclk = ClockSignal("coresync")
 743         if self.pll_en:
 744             comb += intclk.eq(pll.clk_pll_o)
 745         else:
 746             comb += intclk.eq(ClockSignal())
 747
 748         return m
 749
 750     def ports(self):
 751         return list(self.ti.ports()) + list(self.pll.ports()) + \
 752                [ClockSignal(), ResetSignal()]
 753
 754     def external_ports(self):
 755         ports = self.ti.external_ports()
 756         ports.append(ClockSignal())
 757         ports.append(ResetSignal())
 758         if self.pll_en:
 759             ports.append(self.pll.clk_sel_i)
 760             ports.append(self.pll_18_o)
 761             ports.append(self.pll.pll_lck_o)
 762         return ports
 763
 764
 765 if __name__ == '__main__':
 766     units = {'alu': 1, 'cr': 1, 'branch': 1, 'trap': 1, 'logical': 1,
 767              'spr': 1,
 768              'div': 1,
 769              'mul': 1,
 770              'shiftrot': 1
 771             }
 772     pspec = TestMemPspec(ldst_ifacetype='bare_wb',
 773                          imem_ifacetype='bare_wb',
 774                          addr_wid=48,
 775                          mask_wid=8,
 776                          reg_wid=64,
 777                          units=units)
 778     dut = TestIssuer(pspec)
 779     vl = main(dut, ports=dut.ports(), name="test_issuer")
 780
 781     if len(sys.argv) == 1:
 782         vl = rtlil.convert(dut, ports=dut.external_ports(), name="test_issuer")
 783         with open("test_issuer.il", "w") as f:
 784             f.write(vl)