src/soc/simple/issuer.py

   1 """simple core issuer
   2
   3 not in any way intended for production use.  this runs a FSM that:
   4
   5 * reads the Program Counter from FastRegs
   6 * reads an instruction from a fixed-size Test Memory
   7 * issues it to the Simple Core
   8 * waits for it to complete
   9 * increments the PC
  10 * does it all over again
  11
  12 the purpose of this module is to verify the functional correctness
  13 of the Function Units in the absolute simplest and clearest possible
  14 way, and to at provide something that can be further incrementally
  15 improved.
  16 """
  17
  18 from nmigen import (Elaboratable, Module, Signal, ClockSignal, ResetSignal,
  19                     ClockDomain, DomainRenamer)
  20 from nmigen.cli import rtlil
  21 from nmigen.cli import main
  22 import sys
  23
  24 from soc.decoder.decode2execute1 import Data
  25 from soc.experiment.testmem import TestMemory # test only for instructions
  26 from soc.regfile.regfiles import FastRegs
  27 from soc.simple.core import NonProductionCore
  28 from soc.config.test.test_loadstore import TestMemPspec
  29 from soc.config.ifetch import ConfigFetchUnit
  30 from soc.decoder.power_enums import MicrOp
  31 from soc.debug.dmi import CoreDebug, DMIInterface
  32 from soc.config.state import CoreState
  33
  34
  35 class TestIssuer(Elaboratable):
  36     """TestIssuer - reads instructions from TestMemory and issues them
  37
  38     efficiency and speed is not the main goal here: functional correctness is.
  39     """
  40     def __init__(self, pspec):
  41         # main instruction core
  42         self.core = core = NonProductionCore(pspec)
  43
  44         # Test Instruction memory
  45         self.imem = ConfigFetchUnit(pspec).fu
  46         # one-row cache of instruction read
  47         self.iline = Signal(64) # one instruction line
  48         self.iprev_adr = Signal(64) # previous address: if different, do read
  49
  50         # DMI interface
  51         self.dbg = CoreDebug()
  52         self.dmi = self.dbg.dmi
  53
  54         # instruction go/monitor
  55         self.pc_o = Signal(64, reset_less=True)
  56         self.pc_i = Data(64, "pc_i") # set "ok" to indicate "please change me"
  57         self.core_bigendian_i = Signal()
  58         self.busy_o = Signal(reset_less=True)
  59         self.memerr_o = Signal(reset_less=True)
  60
  61         # FAST regfile read /write ports for PC and MSR
  62         self.fast_r_pc = self.core.regs.rf['fast'].r_ports['cia'] # PC rd
  63         self.fast_w_pc = self.core.regs.rf['fast'].w_ports['d_wr1'] # PC wr
  64         self.fast_r_msr = self.core.regs.rf['fast'].r_ports['msr'] # MSR rd
  65
  66         # hack method of keeping an eye on whether branch/trap set the PC
  67         self.fast_nia = self.core.regs.rf['fast'].w_ports['nia']
  68         self.fast_nia.wen.name = 'fast_nia_wen'
  69
  70     def elaborate(self, platform):
  71         m = Module()
  72         comb, sync = m.d.comb, m.d.sync
  73
  74         m.submodules.core = core = DomainRenamer("coresync")(self.core)
  75         m.submodules.imem = imem = self.imem
  76         m.submodules.dbg = dbg = self.dbg
  77
  78         # clock delay power-on reset
  79         cd_por  = ClockDomain(reset_less=True)
  80         cd_sync = ClockDomain()
  81         core_sync = ClockDomain("coresync")
  82         m.domains += cd_por, cd_sync, core_sync
  83
  84         delay = Signal(range(4), reset=1)
  85         with m.If(delay != 0):
  86             m.d.por += delay.eq(delay - 1)
  87         comb += cd_por.clk.eq(ClockSignal())
  88         comb += core_sync.clk.eq(ClockSignal())
  89         # XXX TODO: power-on reset delay (later)
  90         #comb += core.core_reset_i.eq(delay != 0 | dbg.core_rst_o)
  91         comb += core.core_reset_i.eq(dbg.core_rst_o)
  92
  93         # busy/halted signals from core
  94         comb += self.busy_o.eq(core.busy_o)
  95         comb += core.bigendian_i.eq(self.core_bigendian_i)
  96
  97         # current state (MSR/PC at the moment
  98         cur_state = CoreState("cur")
  99
 100         # temporary hack: says "go" immediately for both address gen and ST
 101         l0 = core.l0
 102         ldst = core.fus.fus['ldst0']
 103         m.d.comb += ldst.ad.go_i.eq(ldst.ad.rel_o) # link addr-go direct to rel
 104         m.d.comb += ldst.st.go_i.eq(ldst.st.rel_o) # link store-go direct to rel
 105
 106         # PC and instruction from I-Memory
 107         current_insn = Signal(32) # current fetched instruction (note sync)
 108         pc_changed = Signal() # note write to PC
 109         comb += self.pc_o.eq(cur_state.pc)
 110         ilatch = Signal(32)
 111
 112         # MSR (temp and latched)
 113         msr = Signal(64, reset_less=True)
 114
 115         # next instruction (+4 on current)
 116         nia = Signal(64, reset_less=True)
 117         comb += nia.eq(cur_state.pc + 4)
 118
 119         # connect up debug signals
 120         comb += core.core_stopped_i.eq(dbg.core_stop_o)
 121         # TODO comb += core.reset_i.eq(dbg.core_rst_o)
 122         # TODO comb += core.icache_rst_i.eq(dbg.icache_rst_o)
 123         comb += dbg.terminate_i.eq(core.core_terminate_o)
 124         comb += dbg.state.eq(cur_state)
 125
 126         # temporaries
 127         core_busy_o = core.busy_o         # core is busy
 128         core_ivalid_i = core.ivalid_i     # instruction is valid
 129         core_issue_i = core.issue_i       # instruction is issued
 130         core_be_i = core.bigendian_i      # bigendian mode
 131         core_opcode_i = core.raw_opcode_i # raw opcode
 132
 133         insn_type = core.pdecode2.e.do.insn_type
 134         insn_state = core.pdecode2.state
 135
 136         # actually use a nmigen FSM for the first time (w00t)
 137         # this FSM is perhaps unusual in that it detects conditions
 138         # then "holds" information, combinatorially, for the core
 139         # (as opposed to using sync - which would be on a clock's delay)
 140         # this includes the actual opcode, valid flags and so on.
 141         with m.FSM() as fsm:
 142
 143             # waiting (zzz)
 144             with m.State("IDLE"):
 145                 sync += pc_changed.eq(0)
 146                 with m.If(~dbg.core_stop_o):
 147                     # instruction allowed to go: start by reading the PC
 148                     pc = Signal(64, reset_less=True)
 149                     with m.If(self.pc_i.ok):
 150                         # incoming override (start from pc_i)
 151                         comb += pc.eq(self.pc_i.data)
 152                     with m.Else():
 153                         # otherwise read FastRegs regfile for PC
 154                         comb += self.fast_r_pc.ren.eq(1<<FastRegs.PC)
 155                         comb += pc.eq(self.fast_r_pc.data_o)
 156                     # capture the PC and also drop it into Insn Memory
 157                     # we have joined a pair of combinatorial memory
 158                     # lookups together.  this is Generally Bad.
 159                     comb += self.imem.a_pc_i.eq(pc)
 160                     comb += self.imem.a_valid_i.eq(1)
 161                     comb += self.imem.f_valid_i.eq(1)
 162                     sync += cur_state.pc.eq(pc)
 163                     m.next = "INSN_READ" # move to "wait for bus" phase
 164
 165             # waiting for instruction bus (stays there until not busy)
 166             with m.State("INSN_READ"):
 167                 with m.If(self.imem.f_busy_o): # zzz...
 168                     # busy: stay in wait-read
 169                     comb += self.imem.a_valid_i.eq(1)
 170                     comb += self.imem.f_valid_i.eq(1)
 171                 with m.Else():
 172                     # not busy: instruction fetched
 173                     f_instr_o = self.imem.f_instr_o
 174                     if f_instr_o.width == 32:
 175                         insn = f_instr_o
 176                     else:
 177                         insn = f_instr_o.word_select(cur_state.pc[2], 32)
 178                     comb += current_insn.eq(insn)
 179                     comb += core_ivalid_i.eq(1) # instruction is valid
 180                     comb += core_issue_i.eq(1)  # and issued
 181                     comb += core_opcode_i.eq(current_insn) # actual opcode
 182                     sync += ilatch.eq(current_insn) # latch current insn
 183
 184                     # read MSR, latch it, and put it in decode "state"
 185                     comb += self.fast_r_msr.ren.eq(1<<FastRegs.MSR)
 186                     comb += msr.eq(self.fast_r_msr.data_o)
 187                     comb += insn_state.msr.eq(msr)
 188                     sync += cur_state.msr.eq(msr) # latch current MSR
 189
 190                     # also drop PC into decode "state"
 191                     comb += insn_state.pc.eq(cur_state.pc)
 192
 193                     m.next = "INSN_ACTIVE" # move to "wait completion"
 194
 195             # instruction started: must wait till it finishes
 196             with m.State("INSN_ACTIVE"):
 197                 with m.If(insn_type != MicrOp.OP_NOP):
 198                     comb += core_ivalid_i.eq(1) # instruction is valid
 199                 comb += core_opcode_i.eq(ilatch) # actual opcode
 200                 comb += insn_state.eq(cur_state)     # and MSR and PC
 201                 with m.If(self.fast_nia.wen):
 202                     sync += pc_changed.eq(1)
 203                 with m.If(~core_busy_o): # instruction done!
 204                     # ok here we are not reading the branch unit.  TODO
 205                     # this just blithely overwrites whatever pipeline
 206                     # updated the PC
 207                     with m.If(~pc_changed):
 208                         comb += self.fast_w_pc.wen.eq(1<<FastRegs.PC)
 209                         comb += self.fast_w_pc.data_i.eq(nia)
 210                     m.next = "IDLE" # back to idle
 211
 212         return m
 213
 214     def __iter__(self):
 215         yield from self.pc_i.ports()
 216         yield self.pc_o
 217         yield self.memerr_o
 218         yield from self.core.ports()
 219         yield from self.imem.ports()
 220         yield self.core_bigendian_i
 221         yield self.busy_o
 222
 223     def ports(self):
 224         return list(self)
 225
 226     def external_ports(self):
 227         return self.pc_i.ports() + [self.pc_o,
 228                                     self.memerr_o,
 229                                     self.busy_o,
 230                                     ] + \
 231                 list(self.dbg.dmi.ports()) + \
 232                 list(self.imem.ibus.fields.values()) + \
 233                 list(self.core.l0.cmpi.lsmem.lsi.dbus.fields.values())
 234
 235     def ports(self):
 236         return list(self)
 237
 238
 239 if __name__ == '__main__':
 240     units = {'alu': 1, 'cr': 1, 'branch': 1, 'trap': 1, 'logical': 1,
 241              'spr': 1,
 242              'mul': 1,
 243              'shiftrot': 1}
 244     pspec = TestMemPspec(ldst_ifacetype='bare_wb',
 245                          imem_ifacetype='bare_wb',
 246                          addr_wid=48,
 247                          mask_wid=8,
 248                          reg_wid=64,
 249                          units=units)
 250     dut = TestIssuer(pspec)
 251     vl = main(dut, ports=dut.ports(), name="test_issuer")
 252
 253     if len(sys.argv) == 1:
 254         vl = rtlil.convert(dut, ports=dut.external_ports(), name="test_issuer")
 255         with open("test_issuer.il", "w") as f:
 256             f.write(vl)