src/soc/simple/issuer.py

   1 """simple core issuer
   2
   3 not in any way intended for production use.  this runs a FSM that:
   4
   5 * reads the Program Counter from StateRegs
   6 * reads an instruction from a fixed-size Test Memory
   7 * issues it to the Simple Core
   8 * waits for it to complete
   9 * increments the PC
  10 * does it all over again
  11
  12 the purpose of this module is to verify the functional correctness
  13 of the Function Units in the absolute simplest and clearest possible
  14 way, and to at provide something that can be further incrementally
  15 improved.
  16 """
  17
  18 from nmigen import (Elaboratable, Module, Signal, ClockSignal, ResetSignal,
  19                     ClockDomain, DomainRenamer, Mux, Const)
  20 from nmigen.cli import rtlil
  21 from nmigen.cli import main
  22 import sys
  23
  24 from soc.decoder.power_decoder import create_pdecode
  25 from soc.decoder.power_decoder2 import PowerDecode2, SVP64PrefixDecoder
  26 from soc.decoder.decode2execute1 import IssuerDecode2ToOperand
  27 from soc.decoder.decode2execute1 import Data
  28 from soc.experiment.testmem import TestMemory # test only for instructions
  29 from soc.regfile.regfiles import StateRegs, FastRegs
  30 from soc.simple.core import NonProductionCore
  31 from soc.config.test.test_loadstore import TestMemPspec
  32 from soc.config.ifetch import ConfigFetchUnit
  33 from soc.decoder.power_enums import MicrOp
  34 from soc.debug.dmi import CoreDebug, DMIInterface
  35 from soc.debug.jtag import JTAG
  36 from soc.config.pinouts import get_pinspecs
  37 from soc.config.state import CoreState
  38 from soc.interrupts.xics import XICS_ICP, XICS_ICS
  39 from soc.bus.simple_gpio import SimpleGPIO
  40 from soc.bus.SPBlock512W64B8W import SPBlock512W64B8W
  41 from soc.clock.select import ClockSelect
  42 from soc.clock.dummypll import DummyPLL
  43 from soc.sv.svstate import SVSTATERec
  44
  45
  46 from nmutil.util import rising_edge
  47
  48 def get_insn(f_instr_o, pc):
  49     if f_instr_o.width == 32:
  50         return f_instr_o
  51     else:
  52         # 64-bit: bit 2 of pc decides which word to select
  53         return f_instr_o.word_select(pc[2], 32)
  54
  55
  56 class TestIssuerInternal(Elaboratable):
  57     """TestIssuer - reads instructions from TestMemory and issues them
  58
  59     efficiency and speed is not the main goal here: functional correctness is.
  60     """
  61     def __init__(self, pspec):
  62
  63         # JTAG interface.  add this right at the start because if it's
  64         # added it *modifies* the pspec, by adding enable/disable signals
  65         # for parts of the rest of the core
  66         self.jtag_en = hasattr(pspec, "debug") and pspec.debug == 'jtag'
  67         if self.jtag_en:
  68             subset = {'uart', 'mtwi', 'eint', 'gpio', 'mspi0', 'mspi1',
  69                       'pwm', 'sd0', 'sdr'}
  70             self.jtag = JTAG(get_pinspecs(subset=subset))
  71             # add signals to pspec to enable/disable icache and dcache
  72             # (or data and intstruction wishbone if icache/dcache not included)
  73             # https://bugs.libre-soc.org/show_bug.cgi?id=520
  74             # TODO: do we actually care if these are not domain-synchronised?
  75             # honestly probably not.
  76             pspec.wb_icache_en = self.jtag.wb_icache_en
  77             pspec.wb_dcache_en = self.jtag.wb_dcache_en
  78             self.wb_sram_en = self.jtag.wb_sram_en
  79         else:
  80             self.wb_sram_en = Const(1)
  81
  82         # add 4k sram blocks?
  83         self.sram4x4k = (hasattr(pspec, "sram4x4kblock") and
  84                          pspec.sram4x4kblock == True)
  85         if self.sram4x4k:
  86             self.sram4k = []
  87             for i in range(4):
  88                 self.sram4k.append(SPBlock512W64B8W(name="sram4k_%d" % i))
  89
  90         # add interrupt controller?
  91         self.xics = hasattr(pspec, "xics") and pspec.xics == True
  92         if self.xics:
  93             self.xics_icp = XICS_ICP()
  94             self.xics_ics = XICS_ICS()
  95             self.int_level_i = self.xics_ics.int_level_i
  96
  97         # add GPIO peripheral?
  98         self.gpio = hasattr(pspec, "gpio") and pspec.gpio == True
  99         if self.gpio:
 100             self.simple_gpio = SimpleGPIO()
 101             self.gpio_o = self.simple_gpio.gpio_o
 102
 103         # main instruction core25
 104         self.core = core = NonProductionCore(pspec)
 105
 106         # instruction decoder.  goes into Trap Record
 107         pdecode = create_pdecode()
 108         self.cur_state = CoreState("cur") # current state (MSR/PC/EINT/SVSTATE)
 109         self.pdecode2 = PowerDecode2(pdecode, state=self.cur_state,
 110                                      opkls=IssuerDecode2ToOperand)
 111         self.svp64 = SVP64PrefixDecoder() # for decoding SVP64 prefix
 112
 113         # Test Instruction memory
 114         self.imem = ConfigFetchUnit(pspec).fu
 115         # one-row cache of instruction read
 116         self.iline = Signal(64) # one instruction line
 117         self.iprev_adr = Signal(64) # previous address: if different, do read
 118
 119         # DMI interface
 120         self.dbg = CoreDebug()
 121
 122         # instruction go/monitor
 123         self.pc_o = Signal(64, reset_less=True)
 124         self.pc_i = Data(64, "pc_i") # set "ok" to indicate "please change me"
 125         self.core_bigendian_i = Signal()
 126         self.busy_o = Signal(reset_less=True)
 127         self.memerr_o = Signal(reset_less=True)
 128
 129         # STATE regfile read /write ports for PC, MSR, SVSTATE
 130         staterf = self.core.regs.rf['state']
 131         self.state_r_pc = staterf.r_ports['cia'] # PC rd
 132         self.state_w_pc = staterf.w_ports['d_wr1'] # PC wr
 133         self.state_r_msr = staterf.r_ports['msr'] # MSR rd
 134         self.state_r_sv = staterf.r_ports['sv'] # SVSTATE rd
 135         self.state_w_sv = staterf.w_ports['sv'] # SVSTATE wr
 136
 137         # DMI interface access
 138         intrf = self.core.regs.rf['int']
 139         crrf = self.core.regs.rf['cr']
 140         xerrf = self.core.regs.rf['xer']
 141         self.int_r = intrf.r_ports['dmi'] # INT read
 142         self.cr_r = crrf.r_ports['full_cr_dbg'] # CR read
 143         self.xer_r = xerrf.r_ports['full_xer'] # XER read
 144
 145         # hack method of keeping an eye on whether branch/trap set the PC
 146         self.state_nia = self.core.regs.rf['state'].w_ports['nia']
 147         self.state_nia.wen.name = 'state_nia_wen'
 148
 149     def elaborate(self, platform):
 150         m = Module()
 151         comb, sync = m.d.comb, m.d.sync
 152
 153         m.submodules.core = core = DomainRenamer("coresync")(self.core)
 154         m.submodules.imem = imem = self.imem
 155         m.submodules.dbg = dbg = self.dbg
 156         if self.jtag_en:
 157             m.submodules.jtag = jtag = self.jtag
 158             # TODO: UART2GDB mux, here, from external pin
 159             # see https://bugs.libre-soc.org/show_bug.cgi?id=499
 160             sync += dbg.dmi.connect_to(jtag.dmi)
 161
 162         cur_state = self.cur_state
 163
 164         # 4x 4k SRAM blocks.  these simply "exist", they get routed in litex
 165         if self.sram4x4k:
 166             for i, sram in enumerate(self.sram4k):
 167                 m.submodules["sram4k_%d" % i] = sram
 168                 comb += sram.enable.eq(self.wb_sram_en)
 169
 170         # XICS interrupt handler
 171         if self.xics:
 172             m.submodules.xics_icp = icp = self.xics_icp
 173             m.submodules.xics_ics = ics = self.xics_ics
 174             comb += icp.ics_i.eq(ics.icp_o)           # connect ICS to ICP
 175             sync += cur_state.eint.eq(icp.core_irq_o) # connect ICP to core
 176
 177         # GPIO test peripheral
 178         if self.gpio:
 179             m.submodules.simple_gpio = simple_gpio = self.simple_gpio
 180
 181         # connect one GPIO output to ICS bit 15 (like in microwatt soc.vhdl)
 182         # XXX causes litex ECP5 test to get wrong idea about input and output
 183         # (but works with verilator sim *sigh*)
 184         #if self.gpio and self.xics:
 185         #   comb += self.int_level_i[15].eq(simple_gpio.gpio_o[0])
 186
 187         # instruction decoder
 188         pdecode = create_pdecode()
 189         m.submodules.dec2 = pdecode2 = self.pdecode2
 190         m.submodules.svp64 = svp64 = self.svp64
 191
 192         # convenience
 193         dmi, d_reg, d_cr, d_xer, = dbg.dmi, dbg.d_gpr, dbg.d_cr, dbg.d_xer
 194         intrf = self.core.regs.rf['int']
 195
 196         # clock delay power-on reset
 197         cd_por  = ClockDomain(reset_less=True)
 198         cd_sync = ClockDomain()
 199         core_sync = ClockDomain("coresync")
 200         m.domains += cd_por, cd_sync, core_sync
 201
 202         ti_rst = Signal(reset_less=True)
 203         delay = Signal(range(4), reset=3)
 204         with m.If(delay != 0):
 205             m.d.por += delay.eq(delay - 1)
 206         comb += cd_por.clk.eq(ClockSignal())
 207
 208         # power-on reset delay
 209         core_rst = ResetSignal("coresync")
 210         comb += ti_rst.eq(delay != 0 | dbg.core_rst_o | ResetSignal())
 211         comb += core_rst.eq(ti_rst)
 212
 213         # busy/halted signals from core
 214         comb += self.busy_o.eq(core.busy_o)
 215         comb += pdecode2.dec.bigendian.eq(self.core_bigendian_i)
 216
 217         # temporary hack: says "go" immediately for both address gen and ST
 218         l0 = core.l0
 219         ldst = core.fus.fus['ldst0']
 220         st_go_edge = rising_edge(m, ldst.st.rel_o)
 221         m.d.comb += ldst.ad.go_i.eq(ldst.ad.rel_o) # link addr-go direct to rel
 222         m.d.comb += ldst.st.go_i.eq(st_go_edge) # link store-go to rising rel
 223
 224         # PC and instruction from I-Memory
 225         pc_changed = Signal() # note write to PC
 226         comb += self.pc_o.eq(cur_state.pc)
 227         ilatch = Signal(32)
 228
 229         # address of the next instruction, in the absence of a branch
 230         # depends on the instruction size
 231         nia = Signal(64, reset_less=True)
 232
 233         # read the PC
 234         pc = Signal(64, reset_less=True)
 235         pc_ok_delay = Signal()
 236         sync += pc_ok_delay.eq(~self.pc_i.ok)
 237         with m.If(self.pc_i.ok):
 238             # incoming override (start from pc_i)
 239             comb += pc.eq(self.pc_i.data)
 240         with m.Else():
 241             # otherwise read StateRegs regfile for PC...
 242             comb += self.state_r_pc.ren.eq(1<<StateRegs.PC)
 243         # ... but on a 1-clock delay
 244         with m.If(pc_ok_delay):
 245             comb += pc.eq(self.state_r_pc.data_o)
 246
 247         # don't write pc every cycle
 248         comb += self.state_w_pc.wen.eq(0)
 249         comb += self.state_w_pc.data_i.eq(0)
 250
 251         # don't read msr or svstate every cycle
 252         comb += self.state_r_sv.ren.eq(0)
 253         comb += self.state_r_msr.ren.eq(0)
 254         msr_read = Signal(reset=1)
 255         sv_read = Signal(reset=1)
 256
 257         # connect up debug signals
 258         # TODO comb += core.icache_rst_i.eq(dbg.icache_rst_o)
 259         comb += dbg.terminate_i.eq(core.core_terminate_o)
 260         comb += dbg.state.pc.eq(pc)
 261         #comb += dbg.state.pc.eq(cur_state.pc)
 262         comb += dbg.state.msr.eq(cur_state.msr)
 263
 264         # temporaries
 265         core_busy_o = core.busy_o                 # core is busy
 266         core_ivalid_i = core.ivalid_i             # instruction is valid
 267         core_issue_i = core.issue_i               # instruction is issued
 268         dec_opcode_i = pdecode2.dec.raw_opcode_in # raw opcode
 269         insn_type = core.e.do.insn_type           # instruction MicroOp type
 270
 271         # there are *TWO* FSMs, one fetch (32/64-bit) one decode/execute.
 272         # these are the handshake signals between fetch and decode/execute
 273
 274         # fetch FSM can run as soon as the PC is valid
 275         fetch_pc_valid_i = Signal()
 276         fetch_pc_ready_o = Signal()
 277         # when done, deliver the instruction to the next FSM
 278         fetch_insn_valid_o = Signal()
 279         fetch_insn_ready_i = Signal()
 280
 281         # latches copy of raw fetched instruction
 282         fetch_insn_o = Signal(32, reset_less=True)
 283
 284         # actually use a nmigen FSM for the first time (w00t)
 285         # this FSM is perhaps unusual in that it detects conditions
 286         # then "holds" information, combinatorially, for the core
 287         # (as opposed to using sync - which would be on a clock's delay)
 288         # this includes the actual opcode, valid flags and so on.
 289
 290         # this FSM performs fetch of raw instruction data, partial-decodes
 291         # it 32-bit at a time to detect SVP64 prefixes, and will optionally
 292         # read a 2nd 32-bit quantity if that occurs.
 293
 294         with m.FSM(name='fetch_fsm'):
 295
 296             # waiting (zzz)
 297             with m.State("IDLE"):
 298                 with m.If(~dbg.core_stop_o & ~core_rst):
 299                     comb += fetch_pc_ready_o.eq(1)
 300                     with m.If(fetch_pc_valid_i):
 301                         # instruction allowed to go: start by reading the PC
 302                         # capture the PC and also drop it into Insn Memory
 303                         # we have joined a pair of combinatorial memory
 304                         # lookups together.  this is Generally Bad.
 305                         comb += self.imem.a_pc_i.eq(pc)
 306                         comb += self.imem.a_valid_i.eq(1)
 307                         comb += self.imem.f_valid_i.eq(1)
 308                         sync += cur_state.pc.eq(pc)
 309
 310                         # initiate read of MSR/SVSTATE. arrives one clock later
 311                         comb += self.state_r_msr.ren.eq(1 << StateRegs.MSR)
 312                         comb += self.state_r_sv.ren.eq(1 << StateRegs.SVSTATE)
 313                         sync += msr_read.eq(0)
 314                         sync += sv_read.eq(0)
 315
 316                         m.next = "INSN_READ"  # move to "wait for bus" phase
 317                 with m.Else():
 318                     comb += core.core_stopped_i.eq(1)
 319                     comb += dbg.core_stopped_i.eq(1)
 320
 321             # dummy pause to find out why simulation is not keeping up
 322             with m.State("INSN_READ"):
 323                 # one cycle later, msr/sv read arrives.  valid only once.
 324                 with m.If(~msr_read):
 325                     sync += msr_read.eq(1) # yeah don't read it again
 326                     sync += cur_state.msr.eq(self.state_r_msr.data_o)
 327                 with m.If(~sv_read):
 328                     sync += sv_read.eq(1) # yeah don't read it again
 329                     sync += cur_state.svstate.eq(self.state_r_sv.data_o)
 330                 with m.If(self.imem.f_busy_o): # zzz...
 331                     # busy: stay in wait-read
 332                     comb += self.imem.a_valid_i.eq(1)
 333                     comb += self.imem.f_valid_i.eq(1)
 334                 with m.Else():
 335                     # not busy: instruction fetched
 336                     insn = get_insn(self.imem.f_instr_o, cur_state.pc)
 337                     # decode the SVP64 prefix, if any
 338                     comb += svp64.raw_opcode_in.eq(insn)
 339                     comb += svp64.bigendian.eq(self.core_bigendian_i)
 340                     # pass the decoded prefix (if any) to PowerDecoder2
 341                     sync += pdecode2.sv_rm.eq(svp64.svp64_rm)
 342                     # calculate the address of the following instruction
 343                     insn_size = Mux(svp64.is_svp64_mode, 8, 4)
 344                     sync += nia.eq(cur_state.pc + insn_size)
 345                     with m.If(~svp64.is_svp64_mode):
 346                         # with no prefix, store the instruction
 347                         # and hand it directly to the next FSM
 348                         sync += fetch_insn_o.eq(insn)
 349                         m.next = "INSN_READY"
 350                     with m.Else():
 351                         # fetch the rest of the instruction from memory
 352                         comb += self.imem.a_pc_i.eq(cur_state.pc + 4)
 353                         comb += self.imem.a_valid_i.eq(1)
 354                         comb += self.imem.f_valid_i.eq(1)
 355                         m.next = "INSN_READ2"
 356
 357             with m.State("INSN_READ2"):
 358                 with m.If(self.imem.f_busy_o):  # zzz...
 359                     # busy: stay in wait-read
 360                     comb += self.imem.a_valid_i.eq(1)
 361                     comb += self.imem.f_valid_i.eq(1)
 362                 with m.Else():
 363                     # not busy: instruction fetched
 364                     insn = get_insn(self.imem.f_instr_o, cur_state.pc+4)
 365                     sync += fetch_insn_o.eq(insn)
 366                     m.next = "INSN_READY"
 367
 368             with m.State("INSN_READY"):
 369                 # hand over the instruction, to be decoded
 370                 comb += fetch_insn_valid_o.eq(1)
 371                 with m.If(fetch_insn_ready_i):
 372                     m.next = "IDLE"
 373
 374         # decode / issue / execute FSM.  this interacts with the "fetch" FSM
 375         # through fetch_pc_ready/valid (incoming) and fetch_insn_ready/valid
 376         # (outgoing).  SVP64 RM prefixes have already been set up by the
 377         # "fetch" phase, so execute is fairly straightforward.
 378
 379         with m.FSM():
 380
 381             # go fetch the instruction at the current PC
 382             # at this point, there is no instruction running, that
 383             # could inadvertently update the PC.
 384             with m.State("INSN_FETCH"):
 385                 comb += fetch_pc_valid_i.eq(1)
 386                 with m.If(fetch_pc_ready_o):
 387                     m.next = "INSN_WAIT"
 388
 389             # decode the instruction when it arrives
 390             with m.State("INSN_WAIT"):
 391                 comb += fetch_insn_ready_i.eq(1)
 392                 with m.If(fetch_insn_valid_o):
 393                     # decode the instruction
 394                     comb += dec_opcode_i.eq(fetch_insn_o)  # actual opcode
 395                     sync += core.e.eq(pdecode2.e)
 396                     sync += core.state.eq(cur_state)
 397                     sync += core.raw_insn_i.eq(dec_opcode_i)
 398                     sync += core.bigendian_i.eq(self.core_bigendian_i)
 399                     sync += ilatch.eq(insn) # latch current insn
 400                     # also drop PC and MSR into decode "state"
 401                     m.next = "INSN_START" # move to "start"
 402
 403             # waiting for instruction bus (stays there until not busy)
 404             with m.State("INSN_START"):
 405                 comb += core_ivalid_i.eq(1) # instruction is valid
 406                 comb += core_issue_i.eq(1)  # and issued
 407                 sync += pc_changed.eq(0)
 408
 409                 m.next = "INSN_ACTIVE" # move to "wait completion"
 410
 411             # instruction started: must wait till it finishes
 412             with m.State("INSN_ACTIVE"):
 413                 with m.If(insn_type != MicrOp.OP_NOP):
 414                     comb += core_ivalid_i.eq(1) # instruction is valid
 415                 with m.If(self.state_nia.wen & (1<<StateRegs.PC)):
 416                     sync += pc_changed.eq(1)
 417                 with m.If(~core_busy_o): # instruction done!
 418                     # ok here we are not reading the branch unit.  TODO
 419                     # this just blithely overwrites whatever pipeline
 420                     # updated the PC
 421                     with m.If(~pc_changed):
 422                         comb += self.state_w_pc.wen.eq(1<<StateRegs.PC)
 423                         comb += self.state_w_pc.data_i.eq(nia)
 424                     sync += core.e.eq(0)
 425                     sync += core.raw_insn_i.eq(0)
 426                     sync += core.bigendian_i.eq(0)
 427                     m.next = "INSN_FETCH"  # back to fetch
 428
 429         # for updating svstate (things like srcstep etc.)
 430         update_svstate = Signal() # TODO: move this somewhere above
 431         new_svstate = SVSTATERec("new_svstate") # and move this as well
 432         # check if svstate needs updating: if so, write it to State Regfile
 433         with m.If(update_svstate):
 434             comb += self.state_w_sv.wen.eq(1<<StateRegs.SVSTATE)
 435             comb += self.state_w_sv.data_i.eq(new_svstate)
 436
 437         # this bit doesn't have to be in the FSM: connect up to read
 438         # regfiles on demand from DMI
 439         with m.If(d_reg.req): # request for regfile access being made
 440             # TODO: error-check this
 441             # XXX should this be combinatorial?  sync better?
 442             if intrf.unary:
 443                 comb += self.int_r.ren.eq(1<<d_reg.addr)
 444             else:
 445                 comb += self.int_r.addr.eq(d_reg.addr)
 446                 comb += self.int_r.ren.eq(1)
 447         d_reg_delay  = Signal()
 448         sync += d_reg_delay.eq(d_reg.req)
 449         with m.If(d_reg_delay):
 450             # data arrives one clock later
 451             comb += d_reg.data.eq(self.int_r.data_o)
 452             comb += d_reg.ack.eq(1)
 453
 454         # sigh same thing for CR debug
 455         with m.If(d_cr.req): # request for regfile access being made
 456             comb += self.cr_r.ren.eq(0b11111111) # enable all
 457         d_cr_delay  = Signal()
 458         sync += d_cr_delay.eq(d_cr.req)
 459         with m.If(d_cr_delay):
 460             # data arrives one clock later
 461             comb += d_cr.data.eq(self.cr_r.data_o)
 462             comb += d_cr.ack.eq(1)
 463
 464         # aaand XER...
 465         with m.If(d_xer.req): # request for regfile access being made
 466             comb += self.xer_r.ren.eq(0b111111) # enable all
 467         d_xer_delay  = Signal()
 468         sync += d_xer_delay.eq(d_xer.req)
 469         with m.If(d_xer_delay):
 470             # data arrives one clock later
 471             comb += d_xer.data.eq(self.xer_r.data_o)
 472             comb += d_xer.ack.eq(1)
 473
 474         # DEC and TB inc/dec FSM.  copy of DEC is put into CoreState,
 475         # (which uses that in PowerDecoder2 to raise 0x900 exception)
 476         self.tb_dec_fsm(m, cur_state.dec)
 477
 478         return m
 479
 480     def tb_dec_fsm(self, m, spr_dec):
 481         """tb_dec_fsm
 482
 483         this is a FSM for updating either dec or tb.  it runs alternately
 484         DEC, TB, DEC, TB.  note that SPR pipeline could have written a new
 485         value to DEC, however the regfile has "passthrough" on it so this
 486         *should* be ok.
 487
 488         see v3.0B p1097-1099 for Timeer Resource and p1065 and p1076
 489         """
 490
 491         comb, sync = m.d.comb, m.d.sync
 492         fast_rf = self.core.regs.rf['fast']
 493         fast_r_dectb = fast_rf.r_ports['issue'] # DEC/TB
 494         fast_w_dectb = fast_rf.w_ports['issue'] # DEC/TB
 495
 496         with m.FSM() as fsm:
 497
 498             # initiates read of current DEC
 499             with m.State("DEC_READ"):
 500                 comb += fast_r_dectb.addr.eq(FastRegs.DEC)
 501                 comb += fast_r_dectb.ren.eq(1)
 502                 m.next = "DEC_WRITE"
 503
 504             # waits for DEC read to arrive (1 cycle), updates with new value
 505             with m.State("DEC_WRITE"):
 506                 new_dec = Signal(64)
 507                 # TODO: MSR.LPCR 32-bit decrement mode
 508                 comb += new_dec.eq(fast_r_dectb.data_o - 1)
 509                 comb += fast_w_dectb.addr.eq(FastRegs.DEC)
 510                 comb += fast_w_dectb.wen.eq(1)
 511                 comb += fast_w_dectb.data_i.eq(new_dec)
 512                 sync += spr_dec.eq(new_dec) # copy into cur_state for decoder
 513                 m.next = "TB_READ"
 514
 515             # initiates read of current TB
 516             with m.State("TB_READ"):
 517                 comb += fast_r_dectb.addr.eq(FastRegs.TB)
 518                 comb += fast_r_dectb.ren.eq(1)
 519                 m.next = "TB_WRITE"
 520
 521             # waits for read TB to arrive, initiates write of current TB
 522             with m.State("TB_WRITE"):
 523                 new_tb = Signal(64)
 524                 comb += new_tb.eq(fast_r_dectb.data_o + 1)
 525                 comb += fast_w_dectb.addr.eq(FastRegs.TB)
 526                 comb += fast_w_dectb.wen.eq(1)
 527                 comb += fast_w_dectb.data_i.eq(new_tb)
 528                 m.next = "DEC_READ"
 529
 530         return m
 531
 532     def __iter__(self):
 533         yield from self.pc_i.ports()
 534         yield self.pc_o
 535         yield self.memerr_o
 536         yield from self.core.ports()
 537         yield from self.imem.ports()
 538         yield self.core_bigendian_i
 539         yield self.busy_o
 540
 541     def ports(self):
 542         return list(self)
 543
 544     def external_ports(self):
 545         ports = self.pc_i.ports()
 546         ports += [self.pc_o, self.memerr_o, self.core_bigendian_i, self.busy_o,
 547                 ]
 548
 549         if self.jtag_en:
 550             ports += list(self.jtag.external_ports())
 551         else:
 552             # don't add DMI if JTAG is enabled
 553             ports += list(self.dbg.dmi.ports())
 554
 555         ports += list(self.imem.ibus.fields.values())
 556         ports += list(self.core.l0.cmpi.lsmem.lsi.slavebus.fields.values())
 557
 558         if self.sram4x4k:
 559             for sram in self.sram4k:
 560                 ports += list(sram.bus.fields.values())
 561
 562         if self.xics:
 563             ports += list(self.xics_icp.bus.fields.values())
 564             ports += list(self.xics_ics.bus.fields.values())
 565             ports.append(self.int_level_i)
 566
 567         if self.gpio:
 568             ports += list(self.simple_gpio.bus.fields.values())
 569             ports.append(self.gpio_o)
 570
 571         return ports
 572
 573     def ports(self):
 574         return list(self)
 575
 576
 577 class TestIssuer(Elaboratable):
 578     def __init__(self, pspec):
 579         self.ti = TestIssuerInternal(pspec)
 580
 581         self.pll = DummyPLL()
 582
 583         # PLL direct clock or not
 584         self.pll_en = hasattr(pspec, "use_pll") and pspec.use_pll
 585         if self.pll_en:
 586             self.pll_18_o = Signal(reset_less=True)
 587
 588     def elaborate(self, platform):
 589         m = Module()
 590         comb = m.d.comb
 591
 592         # TestIssuer runs at direct clock
 593         m.submodules.ti = ti = self.ti
 594         cd_int = ClockDomain("coresync")
 595
 596         if self.pll_en:
 597             # ClockSelect runs at PLL output internal clock rate
 598             m.submodules.pll = pll = self.pll
 599
 600             # add clock domains from PLL
 601             cd_pll = ClockDomain("pllclk")
 602             m.domains += cd_pll
 603
 604             # PLL clock established.  has the side-effect of running clklsel
 605             # at the PLL's speed (see DomainRenamer("pllclk") above)
 606             pllclk = ClockSignal("pllclk")
 607             comb += pllclk.eq(pll.clk_pll_o)
 608
 609             # wire up external 24mhz to PLL
 610             comb += pll.clk_24_i.eq(ClockSignal())
 611
 612             # output 18 mhz PLL test signal
 613             comb += self.pll_18_o.eq(pll.pll_18_o)
 614
 615             # now wire up ResetSignals.  don't mind them being in this domain
 616             pll_rst = ResetSignal("pllclk")
 617             comb += pll_rst.eq(ResetSignal())
 618
 619         # internal clock is set to selector clock-out.  has the side-effect of
 620         # running TestIssuer at this speed (see DomainRenamer("intclk") above)
 621         intclk = ClockSignal("coresync")
 622         if self.pll_en:
 623             comb += intclk.eq(pll.clk_pll_o)
 624         else:
 625             comb += intclk.eq(ClockSignal())
 626
 627         return m
 628
 629     def ports(self):
 630         return list(self.ti.ports()) + list(self.pll.ports()) + \
 631                [ClockSignal(), ResetSignal()]
 632
 633     def external_ports(self):
 634         ports = self.ti.external_ports()
 635         ports.append(ClockSignal())
 636         ports.append(ResetSignal())
 637         if self.pll_en:
 638             ports.append(self.pll.clk_sel_i)
 639             ports.append(self.pll_18_o)
 640             ports.append(self.pll.pll_lck_o)
 641         return ports
 642
 643
 644 if __name__ == '__main__':
 645     units = {'alu': 1, 'cr': 1, 'branch': 1, 'trap': 1, 'logical': 1,
 646              'spr': 1,
 647              'div': 1,
 648              'mul': 1,
 649              'shiftrot': 1
 650             }
 651     pspec = TestMemPspec(ldst_ifacetype='bare_wb',
 652                          imem_ifacetype='bare_wb',
 653                          addr_wid=48,
 654                          mask_wid=8,
 655                          reg_wid=64,
 656                          units=units)
 657     dut = TestIssuer(pspec)
 658     vl = main(dut, ports=dut.ports(), name="test_issuer")
 659
 660     if len(sys.argv) == 1:
 661         vl = rtlil.convert(dut, ports=dut.external_ports(), name="test_issuer")
 662         with open("test_issuer.il", "w") as f:
 663             f.write(vl)