src/soc/simple/issuer.py

   1 """simple core issuer
   2
   3 not in any way intended for production use.  this runs a FSM that:
   4
   5 * reads the Program Counter from StateRegs
   6 * reads an instruction from a fixed-size Test Memory
   7 * issues it to the Simple Core
   8 * waits for it to complete
   9 * increments the PC
  10 * does it all over again
  11
  12 the purpose of this module is to verify the functional correctness
  13 of the Function Units in the absolute simplest and clearest possible
  14 way, and to at provide something that can be further incrementally
  15 improved.
  16 """
  17
  18 from nmigen import (Elaboratable, Module, Signal, ClockSignal, ResetSignal,
  19                     ClockDomain, DomainRenamer, Mux, Const)
  20 from nmigen.cli import rtlil
  21 from nmigen.cli import main
  22 import sys
  23
  24 from soc.decoder.power_decoder import create_pdecode
  25 from soc.decoder.power_decoder2 import PowerDecode2, SVP64PrefixDecoder
  26 from soc.decoder.decode2execute1 import IssuerDecode2ToOperand
  27 from soc.decoder.decode2execute1 import Data
  28 from soc.experiment.testmem import TestMemory # test only for instructions
  29 from soc.regfile.regfiles import StateRegs, FastRegs
  30 from soc.simple.core import NonProductionCore
  31 from soc.config.test.test_loadstore import TestMemPspec
  32 from soc.config.ifetch import ConfigFetchUnit
  33 from soc.decoder.power_enums import MicrOp
  34 from soc.debug.dmi import CoreDebug, DMIInterface
  35 from soc.debug.jtag import JTAG
  36 from soc.config.pinouts import get_pinspecs
  37 from soc.config.state import CoreState
  38 from soc.interrupts.xics import XICS_ICP, XICS_ICS
  39 from soc.bus.simple_gpio import SimpleGPIO
  40 from soc.bus.SPBlock512W64B8W import SPBlock512W64B8W
  41 from soc.clock.select import ClockSelect
  42 from soc.clock.dummypll import DummyPLL
  43 from soc.sv.svstate import SVSTATERec
  44
  45
  46 from nmutil.util import rising_edge
  47
  48 def get_insn(f_instr_o, pc):
  49     if f_instr_o.width == 32:
  50         return f_instr_o
  51     else:
  52         # 64-bit: bit 2 of pc decides which word to select
  53         return f_instr_o.word_select(pc[2], 32)
  54
  55
  56 class TestIssuerInternal(Elaboratable):
  57     """TestIssuer - reads instructions from TestMemory and issues them
  58
  59     efficiency and speed is not the main goal here: functional correctness is.
  60     """
  61     def __init__(self, pspec):
  62
  63         # JTAG interface.  add this right at the start because if it's
  64         # added it *modifies* the pspec, by adding enable/disable signals
  65         # for parts of the rest of the core
  66         self.jtag_en = hasattr(pspec, "debug") and pspec.debug == 'jtag'
  67         if self.jtag_en:
  68             subset = {'uart', 'mtwi', 'eint', 'gpio', 'mspi0', 'mspi1',
  69                       'pwm', 'sd0', 'sdr'}
  70             self.jtag = JTAG(get_pinspecs(subset=subset))
  71             # add signals to pspec to enable/disable icache and dcache
  72             # (or data and intstruction wishbone if icache/dcache not included)
  73             # https://bugs.libre-soc.org/show_bug.cgi?id=520
  74             # TODO: do we actually care if these are not domain-synchronised?
  75             # honestly probably not.
  76             pspec.wb_icache_en = self.jtag.wb_icache_en
  77             pspec.wb_dcache_en = self.jtag.wb_dcache_en
  78             self.wb_sram_en = self.jtag.wb_sram_en
  79         else:
  80             self.wb_sram_en = Const(1)
  81
  82         # add 4k sram blocks?
  83         self.sram4x4k = (hasattr(pspec, "sram4x4kblock") and
  84                          pspec.sram4x4kblock == True)
  85         if self.sram4x4k:
  86             self.sram4k = []
  87             for i in range(4):
  88                 self.sram4k.append(SPBlock512W64B8W(name="sram4k_%d" % i))
  89
  90         # add interrupt controller?
  91         self.xics = hasattr(pspec, "xics") and pspec.xics == True
  92         if self.xics:
  93             self.xics_icp = XICS_ICP()
  94             self.xics_ics = XICS_ICS()
  95             self.int_level_i = self.xics_ics.int_level_i
  96
  97         # add GPIO peripheral?
  98         self.gpio = hasattr(pspec, "gpio") and pspec.gpio == True
  99         if self.gpio:
 100             self.simple_gpio = SimpleGPIO()
 101             self.gpio_o = self.simple_gpio.gpio_o
 102
 103         # main instruction core25
 104         self.core = core = NonProductionCore(pspec)
 105
 106         # instruction decoder.  goes into Trap Record
 107         pdecode = create_pdecode()
 108         self.cur_state = CoreState("cur") # current state (MSR/PC/EINT/SVSTATE)
 109         self.pdecode2 = PowerDecode2(pdecode, state=self.cur_state,
 110                                      opkls=IssuerDecode2ToOperand)
 111         self.svp64 = SVP64PrefixDecoder() # for decoding SVP64 prefix
 112
 113         # Test Instruction memory
 114         self.imem = ConfigFetchUnit(pspec).fu
 115         # one-row cache of instruction read
 116         self.iline = Signal(64) # one instruction line
 117         self.iprev_adr = Signal(64) # previous address: if different, do read
 118
 119         # DMI interface
 120         self.dbg = CoreDebug()
 121
 122         # instruction go/monitor
 123         self.pc_o = Signal(64, reset_less=True)
 124         self.pc_i = Data(64, "pc_i") # set "ok" to indicate "please change me"
 125         self.core_bigendian_i = Signal()
 126         self.busy_o = Signal(reset_less=True)
 127         self.memerr_o = Signal(reset_less=True)
 128
 129         # STATE regfile read /write ports for PC, MSR, SVSTATE
 130         staterf = self.core.regs.rf['state']
 131         self.state_r_pc = staterf.r_ports['cia'] # PC rd
 132         self.state_w_pc = staterf.w_ports['d_wr1'] # PC wr
 133         self.state_r_msr = staterf.r_ports['msr'] # MSR rd
 134         self.state_r_sv = staterf.r_ports['sv'] # SVSTATE rd
 135         self.state_w_sv = staterf.w_ports['sv'] # SVSTATE wr
 136
 137         # DMI interface access
 138         intrf = self.core.regs.rf['int']
 139         crrf = self.core.regs.rf['cr']
 140         xerrf = self.core.regs.rf['xer']
 141         self.int_r = intrf.r_ports['dmi'] # INT read
 142         self.cr_r = crrf.r_ports['full_cr_dbg'] # CR read
 143         self.xer_r = xerrf.r_ports['full_xer'] # XER read
 144
 145         # hack method of keeping an eye on whether branch/trap set the PC
 146         self.state_nia = self.core.regs.rf['state'].w_ports['nia']
 147         self.state_nia.wen.name = 'state_nia_wen'
 148
 149     def fetch_fsm(self, m, core, dbg, pc, nia,
 150                         core_rst, cur_state,
 151                         fetch_pc_ready_o, fetch_pc_valid_i,
 152                         fetch_insn_valid_o, fetch_insn_ready_i,
 153                         msr_read, sv_read,
 154                         fetch_insn_o):
 155         """fetch FSM
 156         this FSM performs fetch of raw instruction data, partial-decodes
 157         it 32-bit at a time to detect SVP64 prefixes, and will optionally
 158         read a 2nd 32-bit quantity if that occurs.
 159         """
 160         comb = m.d.comb
 161         sync = m.d.sync
 162         pdecode2 = self.pdecode2
 163         svp64 = self.svp64
 164
 165         with m.FSM(name='fetch_fsm'):
 166
 167             # waiting (zzz)
 168             with m.State("IDLE"):
 169                 with m.If(~dbg.core_stop_o & ~core_rst):
 170                     comb += fetch_pc_ready_o.eq(1)
 171                     with m.If(fetch_pc_valid_i):
 172                         # instruction allowed to go: start by reading the PC
 173                         # capture the PC and also drop it into Insn Memory
 174                         # we have joined a pair of combinatorial memory
 175                         # lookups together.  this is Generally Bad.
 176                         comb += self.imem.a_pc_i.eq(pc)
 177                         comb += self.imem.a_valid_i.eq(1)
 178                         comb += self.imem.f_valid_i.eq(1)
 179                         sync += cur_state.pc.eq(pc)
 180
 181                         # initiate read of MSR/SVSTATE. arrives one clock later
 182                         comb += self.state_r_msr.ren.eq(1 << StateRegs.MSR)
 183                         comb += self.state_r_sv.ren.eq(1 << StateRegs.SVSTATE)
 184                         sync += msr_read.eq(0)
 185                         sync += sv_read.eq(0)
 186
 187                         m.next = "INSN_READ"  # move to "wait for bus" phase
 188                 with m.Else():
 189                     comb += core.core_stopped_i.eq(1)
 190                     comb += dbg.core_stopped_i.eq(1)
 191
 192             # dummy pause to find out why simulation is not keeping up
 193             with m.State("INSN_READ"):
 194                 # one cycle later, msr/sv read arrives.  valid only once.
 195                 with m.If(~msr_read):
 196                     sync += msr_read.eq(1) # yeah don't read it again
 197                     sync += cur_state.msr.eq(self.state_r_msr.data_o)
 198                 with m.If(~sv_read):
 199                     sync += sv_read.eq(1) # yeah don't read it again
 200                     sync += cur_state.svstate.eq(self.state_r_sv.data_o)
 201                 with m.If(self.imem.f_busy_o): # zzz...
 202                     # busy: stay in wait-read
 203                     comb += self.imem.a_valid_i.eq(1)
 204                     comb += self.imem.f_valid_i.eq(1)
 205                 with m.Else():
 206                     # not busy: instruction fetched
 207                     insn = get_insn(self.imem.f_instr_o, cur_state.pc)
 208                     # decode the SVP64 prefix, if any
 209                     comb += svp64.raw_opcode_in.eq(insn)
 210                     comb += svp64.bigendian.eq(self.core_bigendian_i)
 211                     # pass the decoded prefix (if any) to PowerDecoder2
 212                     sync += pdecode2.sv_rm.eq(svp64.svp64_rm)
 213                     # calculate the address of the following instruction
 214                     insn_size = Mux(svp64.is_svp64_mode, 8, 4)
 215                     sync += nia.eq(cur_state.pc + insn_size)
 216                     with m.If(~svp64.is_svp64_mode):
 217                         # with no prefix, store the instruction
 218                         # and hand it directly to the next FSM
 219                         sync += fetch_insn_o.eq(insn)
 220                         m.next = "INSN_READY"
 221                     with m.Else():
 222                         # fetch the rest of the instruction from memory
 223                         comb += self.imem.a_pc_i.eq(cur_state.pc + 4)
 224                         comb += self.imem.a_valid_i.eq(1)
 225                         comb += self.imem.f_valid_i.eq(1)
 226                         m.next = "INSN_READ2"
 227
 228             with m.State("INSN_READ2"):
 229                 with m.If(self.imem.f_busy_o):  # zzz...
 230                     # busy: stay in wait-read
 231                     comb += self.imem.a_valid_i.eq(1)
 232                     comb += self.imem.f_valid_i.eq(1)
 233                 with m.Else():
 234                     # not busy: instruction fetched
 235                     insn = get_insn(self.imem.f_instr_o, cur_state.pc+4)
 236                     sync += fetch_insn_o.eq(insn)
 237                     m.next = "INSN_READY"
 238
 239             with m.State("INSN_READY"):
 240                 # hand over the instruction, to be decoded
 241                 comb += fetch_insn_valid_o.eq(1)
 242                 with m.If(fetch_insn_ready_i):
 243                     m.next = "IDLE"
 244
 245     def elaborate(self, platform):
 246         m = Module()
 247         comb, sync = m.d.comb, m.d.sync
 248
 249         m.submodules.core = core = DomainRenamer("coresync")(self.core)
 250         m.submodules.imem = imem = self.imem
 251         m.submodules.dbg = dbg = self.dbg
 252         if self.jtag_en:
 253             m.submodules.jtag = jtag = self.jtag
 254             # TODO: UART2GDB mux, here, from external pin
 255             # see https://bugs.libre-soc.org/show_bug.cgi?id=499
 256             sync += dbg.dmi.connect_to(jtag.dmi)
 257
 258         cur_state = self.cur_state
 259
 260         # 4x 4k SRAM blocks.  these simply "exist", they get routed in litex
 261         if self.sram4x4k:
 262             for i, sram in enumerate(self.sram4k):
 263                 m.submodules["sram4k_%d" % i] = sram
 264                 comb += sram.enable.eq(self.wb_sram_en)
 265
 266         # XICS interrupt handler
 267         if self.xics:
 268             m.submodules.xics_icp = icp = self.xics_icp
 269             m.submodules.xics_ics = ics = self.xics_ics
 270             comb += icp.ics_i.eq(ics.icp_o)           # connect ICS to ICP
 271             sync += cur_state.eint.eq(icp.core_irq_o) # connect ICP to core
 272
 273         # GPIO test peripheral
 274         if self.gpio:
 275             m.submodules.simple_gpio = simple_gpio = self.simple_gpio
 276
 277         # connect one GPIO output to ICS bit 15 (like in microwatt soc.vhdl)
 278         # XXX causes litex ECP5 test to get wrong idea about input and output
 279         # (but works with verilator sim *sigh*)
 280         #if self.gpio and self.xics:
 281         #   comb += self.int_level_i[15].eq(simple_gpio.gpio_o[0])
 282
 283         # instruction decoder
 284         pdecode = create_pdecode()
 285         m.submodules.dec2 = pdecode2 = self.pdecode2
 286         m.submodules.svp64 = svp64 = self.svp64
 287
 288         # convenience
 289         dmi, d_reg, d_cr, d_xer, = dbg.dmi, dbg.d_gpr, dbg.d_cr, dbg.d_xer
 290         intrf = self.core.regs.rf['int']
 291
 292         # clock delay power-on reset
 293         cd_por  = ClockDomain(reset_less=True)
 294         cd_sync = ClockDomain()
 295         core_sync = ClockDomain("coresync")
 296         m.domains += cd_por, cd_sync, core_sync
 297
 298         ti_rst = Signal(reset_less=True)
 299         delay = Signal(range(4), reset=3)
 300         with m.If(delay != 0):
 301             m.d.por += delay.eq(delay - 1)
 302         comb += cd_por.clk.eq(ClockSignal())
 303
 304         # power-on reset delay
 305         core_rst = ResetSignal("coresync")
 306         comb += ti_rst.eq(delay != 0 | dbg.core_rst_o | ResetSignal())
 307         comb += core_rst.eq(ti_rst)
 308
 309         # busy/halted signals from core
 310         comb += self.busy_o.eq(core.busy_o)
 311         comb += pdecode2.dec.bigendian.eq(self.core_bigendian_i)
 312
 313         # temporary hack: says "go" immediately for both address gen and ST
 314         l0 = core.l0
 315         ldst = core.fus.fus['ldst0']
 316         st_go_edge = rising_edge(m, ldst.st.rel_o)
 317         m.d.comb += ldst.ad.go_i.eq(ldst.ad.rel_o) # link addr-go direct to rel
 318         m.d.comb += ldst.st.go_i.eq(st_go_edge) # link store-go to rising rel
 319
 320         # PC and instruction from I-Memory
 321         pc_changed = Signal() # note write to PC
 322         comb += self.pc_o.eq(cur_state.pc)
 323
 324         # address of the next instruction, in the absence of a branch
 325         # depends on the instruction size
 326         nia = Signal(64, reset_less=True)
 327
 328         # read the PC
 329         pc = Signal(64, reset_less=True)
 330         pc_ok_delay = Signal()
 331         sync += pc_ok_delay.eq(~self.pc_i.ok)
 332         with m.If(self.pc_i.ok):
 333             # incoming override (start from pc_i)
 334             comb += pc.eq(self.pc_i.data)
 335         with m.Else():
 336             # otherwise read StateRegs regfile for PC...
 337             comb += self.state_r_pc.ren.eq(1<<StateRegs.PC)
 338         # ... but on a 1-clock delay
 339         with m.If(pc_ok_delay):
 340             comb += pc.eq(self.state_r_pc.data_o)
 341
 342         # don't write pc every cycle
 343         comb += self.state_w_pc.wen.eq(0)
 344         comb += self.state_w_pc.data_i.eq(0)
 345
 346         # don't read msr or svstate every cycle
 347         comb += self.state_r_sv.ren.eq(0)
 348         comb += self.state_r_msr.ren.eq(0)
 349         msr_read = Signal(reset=1)
 350         sv_read = Signal(reset=1)
 351
 352         # connect up debug signals
 353         # TODO comb += core.icache_rst_i.eq(dbg.icache_rst_o)
 354         comb += dbg.terminate_i.eq(core.core_terminate_o)
 355         comb += dbg.state.pc.eq(pc)
 356         #comb += dbg.state.pc.eq(cur_state.pc)
 357         comb += dbg.state.msr.eq(cur_state.msr)
 358
 359         # temporaries
 360         core_busy_o = core.busy_o                 # core is busy
 361         core_ivalid_i = core.ivalid_i             # instruction is valid
 362         core_issue_i = core.issue_i               # instruction is issued
 363         dec_opcode_i = pdecode2.dec.raw_opcode_in # raw opcode
 364         insn_type = core.e.do.insn_type           # instruction MicroOp type
 365
 366         # there are *TWO* FSMs, one fetch (32/64-bit) one decode/execute.
 367         # these are the handshake signals between fetch and decode/execute
 368
 369         # fetch FSM can run as soon as the PC is valid
 370         fetch_pc_valid_i = Signal()
 371         fetch_pc_ready_o = Signal()
 372         # when done, deliver the instruction to the next FSM
 373         fetch_insn_valid_o = Signal()
 374         fetch_insn_ready_i = Signal()
 375
 376         # latches copy of raw fetched instruction
 377         fetch_insn_o = Signal(32, reset_less=True)
 378
 379         # actually use a nmigen FSM for the first time (w00t)
 380         # this FSM is perhaps unusual in that it detects conditions
 381         # then "holds" information, combinatorially, for the core
 382         # (as opposed to using sync - which would be on a clock's delay)
 383         # this includes the actual opcode, valid flags and so on.
 384
 385         self.fetch_fsm(m, core, dbg, pc, nia,
 386                        core_rst, cur_state,
 387                        fetch_pc_ready_o, fetch_pc_valid_i,
 388                        fetch_insn_valid_o, fetch_insn_ready_i,
 389                        msr_read, sv_read,
 390                        fetch_insn_o)
 391
 392         # decode / issue / execute FSM.  this interacts with the "fetch" FSM
 393         # through fetch_pc_ready/valid (incoming) and fetch_insn_ready/valid
 394         # (outgoing).  SVP64 RM prefixes have already been set up by the
 395         # "fetch" phase, so execute is fairly straightforward.
 396
 397         with m.FSM():
 398
 399             # go fetch the instruction at the current PC
 400             # at this point, there is no instruction running, that
 401             # could inadvertently update the PC.
 402             with m.State("INSN_FETCH"):
 403                 comb += fetch_pc_valid_i.eq(1)
 404                 with m.If(fetch_pc_ready_o):
 405                     m.next = "INSN_WAIT"
 406
 407             # decode the instruction when it arrives
 408             with m.State("INSN_WAIT"):
 409                 comb += fetch_insn_ready_i.eq(1)
 410                 with m.If(fetch_insn_valid_o):
 411                     # decode the instruction
 412                     comb += dec_opcode_i.eq(fetch_insn_o)  # actual opcode
 413                     sync += core.e.eq(pdecode2.e)
 414                     sync += core.state.eq(cur_state)
 415                     sync += core.raw_insn_i.eq(dec_opcode_i)
 416                     sync += core.bigendian_i.eq(self.core_bigendian_i)
 417                     # also drop PC and MSR into decode "state"
 418                     m.next = "INSN_START" # move to "start"
 419
 420             # waiting for instruction bus (stays there until not busy)
 421             with m.State("INSN_START"):
 422                 comb += core_ivalid_i.eq(1) # instruction is valid
 423                 comb += core_issue_i.eq(1)  # and issued
 424                 sync += pc_changed.eq(0)
 425
 426                 m.next = "INSN_ACTIVE" # move to "wait completion"
 427
 428             # instruction started: must wait till it finishes
 429             with m.State("INSN_ACTIVE"):
 430                 with m.If(insn_type != MicrOp.OP_NOP):
 431                     comb += core_ivalid_i.eq(1) # instruction is valid
 432                 with m.If(self.state_nia.wen & (1<<StateRegs.PC)):
 433                     sync += pc_changed.eq(1)
 434                 with m.If(~core_busy_o): # instruction done!
 435                     # ok here we are not reading the branch unit.  TODO
 436                     # this just blithely overwrites whatever pipeline
 437                     # updated the PC
 438                     with m.If(~pc_changed):
 439                         comb += self.state_w_pc.wen.eq(1<<StateRegs.PC)
 440                         comb += self.state_w_pc.data_i.eq(nia)
 441                     sync += core.e.eq(0)
 442                     sync += core.raw_insn_i.eq(0)
 443                     sync += core.bigendian_i.eq(0)
 444                     m.next = "INSN_FETCH"  # back to fetch
 445
 446         # for updating svstate (things like srcstep etc.)
 447         update_svstate = Signal() # TODO: move this somewhere above
 448         new_svstate = SVSTATERec("new_svstate") # and move this as well
 449         # check if svstate needs updating: if so, write it to State Regfile
 450         with m.If(update_svstate):
 451             comb += self.state_w_sv.wen.eq(1<<StateRegs.SVSTATE)
 452             comb += self.state_w_sv.data_i.eq(new_svstate)
 453
 454         # this bit doesn't have to be in the FSM: connect up to read
 455         # regfiles on demand from DMI
 456         with m.If(d_reg.req): # request for regfile access being made
 457             # TODO: error-check this
 458             # XXX should this be combinatorial?  sync better?
 459             if intrf.unary:
 460                 comb += self.int_r.ren.eq(1<<d_reg.addr)
 461             else:
 462                 comb += self.int_r.addr.eq(d_reg.addr)
 463                 comb += self.int_r.ren.eq(1)
 464         d_reg_delay  = Signal()
 465         sync += d_reg_delay.eq(d_reg.req)
 466         with m.If(d_reg_delay):
 467             # data arrives one clock later
 468             comb += d_reg.data.eq(self.int_r.data_o)
 469             comb += d_reg.ack.eq(1)
 470
 471         # sigh same thing for CR debug
 472         with m.If(d_cr.req): # request for regfile access being made
 473             comb += self.cr_r.ren.eq(0b11111111) # enable all
 474         d_cr_delay  = Signal()
 475         sync += d_cr_delay.eq(d_cr.req)
 476         with m.If(d_cr_delay):
 477             # data arrives one clock later
 478             comb += d_cr.data.eq(self.cr_r.data_o)
 479             comb += d_cr.ack.eq(1)
 480
 481         # aaand XER...
 482         with m.If(d_xer.req): # request for regfile access being made
 483             comb += self.xer_r.ren.eq(0b111111) # enable all
 484         d_xer_delay  = Signal()
 485         sync += d_xer_delay.eq(d_xer.req)
 486         with m.If(d_xer_delay):
 487             # data arrives one clock later
 488             comb += d_xer.data.eq(self.xer_r.data_o)
 489             comb += d_xer.ack.eq(1)
 490
 491         # DEC and TB inc/dec FSM.  copy of DEC is put into CoreState,
 492         # (which uses that in PowerDecoder2 to raise 0x900 exception)
 493         self.tb_dec_fsm(m, cur_state.dec)
 494
 495         return m
 496
 497     def tb_dec_fsm(self, m, spr_dec):
 498         """tb_dec_fsm
 499
 500         this is a FSM for updating either dec or tb.  it runs alternately
 501         DEC, TB, DEC, TB.  note that SPR pipeline could have written a new
 502         value to DEC, however the regfile has "passthrough" on it so this
 503         *should* be ok.
 504
 505         see v3.0B p1097-1099 for Timeer Resource and p1065 and p1076
 506         """
 507
 508         comb, sync = m.d.comb, m.d.sync
 509         fast_rf = self.core.regs.rf['fast']
 510         fast_r_dectb = fast_rf.r_ports['issue'] # DEC/TB
 511         fast_w_dectb = fast_rf.w_ports['issue'] # DEC/TB
 512
 513         with m.FSM() as fsm:
 514
 515             # initiates read of current DEC
 516             with m.State("DEC_READ"):
 517                 comb += fast_r_dectb.addr.eq(FastRegs.DEC)
 518                 comb += fast_r_dectb.ren.eq(1)
 519                 m.next = "DEC_WRITE"
 520
 521             # waits for DEC read to arrive (1 cycle), updates with new value
 522             with m.State("DEC_WRITE"):
 523                 new_dec = Signal(64)
 524                 # TODO: MSR.LPCR 32-bit decrement mode
 525                 comb += new_dec.eq(fast_r_dectb.data_o - 1)
 526                 comb += fast_w_dectb.addr.eq(FastRegs.DEC)
 527                 comb += fast_w_dectb.wen.eq(1)
 528                 comb += fast_w_dectb.data_i.eq(new_dec)
 529                 sync += spr_dec.eq(new_dec) # copy into cur_state for decoder
 530                 m.next = "TB_READ"
 531
 532             # initiates read of current TB
 533             with m.State("TB_READ"):
 534                 comb += fast_r_dectb.addr.eq(FastRegs.TB)
 535                 comb += fast_r_dectb.ren.eq(1)
 536                 m.next = "TB_WRITE"
 537
 538             # waits for read TB to arrive, initiates write of current TB
 539             with m.State("TB_WRITE"):
 540                 new_tb = Signal(64)
 541                 comb += new_tb.eq(fast_r_dectb.data_o + 1)
 542                 comb += fast_w_dectb.addr.eq(FastRegs.TB)
 543                 comb += fast_w_dectb.wen.eq(1)
 544                 comb += fast_w_dectb.data_i.eq(new_tb)
 545                 m.next = "DEC_READ"
 546
 547         return m
 548
 549     def __iter__(self):
 550         yield from self.pc_i.ports()
 551         yield self.pc_o
 552         yield self.memerr_o
 553         yield from self.core.ports()
 554         yield from self.imem.ports()
 555         yield self.core_bigendian_i
 556         yield self.busy_o
 557
 558     def ports(self):
 559         return list(self)
 560
 561     def external_ports(self):
 562         ports = self.pc_i.ports()
 563         ports += [self.pc_o, self.memerr_o, self.core_bigendian_i, self.busy_o,
 564                 ]
 565
 566         if self.jtag_en:
 567             ports += list(self.jtag.external_ports())
 568         else:
 569             # don't add DMI if JTAG is enabled
 570             ports += list(self.dbg.dmi.ports())
 571
 572         ports += list(self.imem.ibus.fields.values())
 573         ports += list(self.core.l0.cmpi.lsmem.lsi.slavebus.fields.values())
 574
 575         if self.sram4x4k:
 576             for sram in self.sram4k:
 577                 ports += list(sram.bus.fields.values())
 578
 579         if self.xics:
 580             ports += list(self.xics_icp.bus.fields.values())
 581             ports += list(self.xics_ics.bus.fields.values())
 582             ports.append(self.int_level_i)
 583
 584         if self.gpio:
 585             ports += list(self.simple_gpio.bus.fields.values())
 586             ports.append(self.gpio_o)
 587
 588         return ports
 589
 590     def ports(self):
 591         return list(self)
 592
 593
 594 class TestIssuer(Elaboratable):
 595     def __init__(self, pspec):
 596         self.ti = TestIssuerInternal(pspec)
 597
 598         self.pll = DummyPLL()
 599
 600         # PLL direct clock or not
 601         self.pll_en = hasattr(pspec, "use_pll") and pspec.use_pll
 602         if self.pll_en:
 603             self.pll_18_o = Signal(reset_less=True)
 604
 605     def elaborate(self, platform):
 606         m = Module()
 607         comb = m.d.comb
 608
 609         # TestIssuer runs at direct clock
 610         m.submodules.ti = ti = self.ti
 611         cd_int = ClockDomain("coresync")
 612
 613         if self.pll_en:
 614             # ClockSelect runs at PLL output internal clock rate
 615             m.submodules.pll = pll = self.pll
 616
 617             # add clock domains from PLL
 618             cd_pll = ClockDomain("pllclk")
 619             m.domains += cd_pll
 620
 621             # PLL clock established.  has the side-effect of running clklsel
 622             # at the PLL's speed (see DomainRenamer("pllclk") above)
 623             pllclk = ClockSignal("pllclk")
 624             comb += pllclk.eq(pll.clk_pll_o)
 625
 626             # wire up external 24mhz to PLL
 627             comb += pll.clk_24_i.eq(ClockSignal())
 628
 629             # output 18 mhz PLL test signal
 630             comb += self.pll_18_o.eq(pll.pll_18_o)
 631
 632             # now wire up ResetSignals.  don't mind them being in this domain
 633             pll_rst = ResetSignal("pllclk")
 634             comb += pll_rst.eq(ResetSignal())
 635
 636         # internal clock is set to selector clock-out.  has the side-effect of
 637         # running TestIssuer at this speed (see DomainRenamer("intclk") above)
 638         intclk = ClockSignal("coresync")
 639         if self.pll_en:
 640             comb += intclk.eq(pll.clk_pll_o)
 641         else:
 642             comb += intclk.eq(ClockSignal())
 643
 644         return m
 645
 646     def ports(self):
 647         return list(self.ti.ports()) + list(self.pll.ports()) + \
 648                [ClockSignal(), ResetSignal()]
 649
 650     def external_ports(self):
 651         ports = self.ti.external_ports()
 652         ports.append(ClockSignal())
 653         ports.append(ResetSignal())
 654         if self.pll_en:
 655             ports.append(self.pll.clk_sel_i)
 656             ports.append(self.pll_18_o)
 657             ports.append(self.pll.pll_lck_o)
 658         return ports
 659
 660
 661 if __name__ == '__main__':
 662     units = {'alu': 1, 'cr': 1, 'branch': 1, 'trap': 1, 'logical': 1,
 663              'spr': 1,
 664              'div': 1,
 665              'mul': 1,
 666              'shiftrot': 1
 667             }
 668     pspec = TestMemPspec(ldst_ifacetype='bare_wb',
 669                          imem_ifacetype='bare_wb',
 670                          addr_wid=48,
 671                          mask_wid=8,
 672                          reg_wid=64,
 673                          units=units)
 674     dut = TestIssuer(pspec)
 675     vl = main(dut, ports=dut.ports(), name="test_issuer")
 676
 677     if len(sys.argv) == 1:
 678         vl = rtlil.convert(dut, ports=dut.external_ports(), name="test_issuer")
 679         with open("test_issuer.il", "w") as f:
 680             f.write(vl)