src/soc/simple/issuer.py

   1 """simple core issuer
   2
   3 not in any way intended for production use.  this runs a FSM that:
   4
   5 * reads the Program Counter from FastRegs
   6 * reads an instruction from a fixed-size Test Memory
   7 * issues it to the Simple Core
   8 * waits for it to complete
   9 * increments the PC
  10 * does it all over again
  11
  12 the purpose of this module is to verify the functional correctness
  13 of the Function Units in the absolute simplest and clearest possible
  14 way, and to at provide something that can be further incrementally
  15 improved.
  16 """
  17
  18 from nmigen import Elaboratable, Module, Signal
  19 from nmigen.cli import rtlil
  20
  21 from soc.decoder.decode2execute1 import Data
  22 from soc.experiment.testmem import TestMemory # test only for instructions
  23 from soc.regfile.regfiles import FastRegs
  24 from soc.simple.core import NonProductionCore
  25 from soc.config.test.test_loadstore import TestMemPspec
  26 from soc.config.ifetch import ConfigFetchUnit
  27
  28
  29 class TestIssuer(Elaboratable):
  30     """TestIssuer - reads instructions from TestMemory and issues them
  31
  32     efficiency and speed is not the main goal here: functional correctness is.
  33     """
  34     def __init__(self, pspec):
  35         # main instruction core
  36         self.core = core = NonProductionCore(pspec)
  37
  38         # Test Instruction memory
  39         self.imem = ConfigFetchUnit(pspec).fu
  40         # one-row cache of instruction read
  41         self.iline = Signal(64) # one instruction line
  42         self.iprev_adr = Signal(64) # previous address: if different, do read
  43
  44         # instruction go/monitor
  45         self.go_insn_i = Signal(reset_less=True)
  46         self.pc_o = Signal(64, reset_less=True)
  47         self.pc_i = Data(64, "pc") # set "ok" to indicate "please change me"
  48         self.busy_o = core.busy_o
  49         self.memerr_o = Signal(reset_less=True)
  50
  51         # FAST regfile read /write ports
  52         self.fast_rd1 = self.core.regs.rf['fast'].r_ports['d_rd1']
  53         self.fast_wr1 = self.core.regs.rf['fast'].w_ports['d_wr1']
  54         # hack method of keeping an eye on whether branch/trap set the PC
  55         self.fast_nia = self.core.regs.rf['fast'].w_ports['nia']
  56         self.fast_nia.wen.name = 'fast_nia_wen'
  57
  58     def elaborate(self, platform):
  59         m = Module()
  60         comb, sync = m.d.comb, m.d.sync
  61
  62         m.submodules.core = core = self.core
  63         m.submodules.imem = imem = self.imem
  64
  65         # temporary hack: says "go" immediately for both address gen and ST
  66         l0 = core.l0
  67         ldst = core.fus.fus['ldst0']
  68         m.d.comb += ldst.ad.go.eq(ldst.ad.rel) # link addr-go direct to rel
  69         m.d.comb += ldst.st.go.eq(ldst.st.rel) # link store-go direct to rel
  70
  71         # PC and instruction from I-Memory
  72         current_insn = Signal(32) # current fetched instruction (note sync)
  73         cur_pc = Signal(64) # current PC (note it is reset/sync)
  74         pc_changed = Signal() # note write to PC
  75         comb += self.pc_o.eq(cur_pc)
  76         ilatch = Signal(32)
  77
  78         # allow debug access to current instruction and pc
  79         self._current_insn = current_insn
  80         self._cur_pc = cur_pc
  81
  82         # next instruction (+4 on current)
  83         nia = Signal(64, reset_less=True)
  84         comb += nia.eq(cur_pc + 4)
  85
  86         # temporaries
  87         core_busy_o = core.busy_o         # core is busy
  88         core_ivalid_i = core.ivalid_i     # instruction is valid
  89         core_issue_i = core.issue_i       # instruction is issued
  90         core_be_i = core.bigendian_i      # bigendian mode
  91         core_opcode_i = core.raw_opcode_i # raw opcode
  92
  93         # only run if not in halted state
  94         with m.If(~core.core_terminated_o):
  95
  96             # actually use a nmigen FSM for the first time (w00t)
  97             with m.FSM() as fsm:
  98
  99                 # waiting (zzz)
 100                 with m.State("IDLE"):
 101                     sync += pc_changed.eq(0)
 102                     with m.If(self.go_insn_i):
 103                         # instruction allowed to go: start by reading the PC
 104                         pc = Signal(64, reset_less=True)
 105                         with m.If(self.pc_i.ok):
 106                             # incoming override (start from pc_i)
 107                             comb += pc.eq(self.pc_i.data)
 108                         with m.Else():
 109                             # otherwise read FastRegs regfile for PC
 110                             comb += self.fast_rd1.ren.eq(1<<FastRegs.PC)
 111                             comb += pc.eq(self.fast_rd1.data_o)
 112                         # capture the PC and also drop it into Insn Memory
 113                         # we have joined a pair of combinatorial memory
 114                         # lookups together.  this is Generally Bad.
 115                         comb += self.imem.a_pc_i.eq(pc)
 116                         comb += self.imem.a_valid_i.eq(1)
 117                         comb += self.imem.f_valid_i.eq(1)
 118                         sync += cur_pc.eq(pc)
 119                         m.next = "INSN_READ" # move to "wait for bus" phase
 120
 121                 # waiting for instruction bus (stays there until not busy)
 122                 with m.State("INSN_READ"):
 123                     with m.If(self.imem.f_busy_o): # zzz...
 124                         # busy: stay in wait-read
 125                         comb += self.imem.a_valid_i.eq(1)
 126                         comb += self.imem.f_valid_i.eq(1)
 127                     with m.Else():
 128                         # not busy: instruction fetched
 129                         insn = self.imem.f_instr_o.word_select(cur_pc[2], 32)
 130                         comb += current_insn.eq(insn)
 131                         comb += core_ivalid_i.eq(1) # say instruction is valid
 132                         comb += core_issue_i.eq(1)  # and issued
 133                         comb += core_be_i.eq(0)     # little-endian mode
 134                         comb += core_opcode_i.eq(current_insn) # actual opcode
 135                         sync += ilatch.eq(current_insn)
 136                         m.next = "INSN_ACTIVE" # move to "wait completion"
 137
 138                 # instruction started: must wait till it finishes
 139                 with m.State("INSN_ACTIVE"):
 140                     comb += core_ivalid_i.eq(1) # say instruction is valid
 141                     comb += core_opcode_i.eq(ilatch) # actual opcode
 142                     with m.If(self.fast_nia.wen):
 143                         sync += pc_changed.eq(1)
 144                     with m.If(~core_busy_o): # instruction done!
 145                         # ok here we are not reading the branch unit.  TODO
 146                         # this just blithely overwrites whatever pipeline
 147                         # updated the PC
 148                         with m.If(~pc_changed):
 149                             comb += self.fast_wr1.wen.eq(1<<FastRegs.PC)
 150                             comb += self.fast_wr1.data_i.eq(nia)
 151                         m.next = "IDLE" # back to idle
 152
 153         return m
 154
 155     def __iter__(self):
 156         yield from self.pc_i.ports()
 157         yield self.pc_o
 158         yield self.go_insn_i
 159         yield self.memerr_o
 160         yield from self.core.ports()
 161         yield from self.imem.ports()
 162
 163     def ports(self):
 164         return list(self)
 165
 166
 167 if __name__ == '__main__':
 168     units = {'alu': 1, 'cr': 1, 'branch': 1, 'trap': 1, 'logical': 1,
 169              'spr': 1,
 170              'mul': 1,
 171              'shiftrot': 1}
 172     pspec = TestMemPspec(ldst_ifacetype='bare_wb',
 173                          imem_ifacetype='bare_wb',
 174                          addr_wid=48,
 175                          mask_wid=8,
 176                          reg_wid=64,
 177                          units=units)
 178     dut = TestIssuer(pspec)
 179     vl = rtlil.convert(dut, ports=dut.ports(), name="test_issuer")
 180     with open("test_issuer.il", "w") as f:
 181         f.write(vl)
 182