3 not in any way intended for production use. this runs a FSM that:
5 * reads the Program Counter from StateRegs
6 * reads an instruction from a fixed-size Test Memory
7 * issues it to the Simple Core
8 * waits for it to complete
10 * does it all over again
12 the purpose of this module is to verify the functional correctness
13 of the Function Units in the absolute simplest and clearest possible
14 way, and to at provide something that can be further incrementally
18 from nmigen
import (Elaboratable
, Module
, Signal
, ClockSignal
, ResetSignal
,
19 ClockDomain
, DomainRenamer
, Mux
, Const
, Repl
, Cat
)
20 from nmigen
.cli
import rtlil
21 from nmigen
.cli
import main
24 from nmutil
.singlepipe
import ControlBase
25 from soc
.simple
.core_data
import FetchOutput
, FetchInput
27 from nmigen
.lib
.coding
import PriorityEncoder
29 from openpower
.decoder
.power_decoder
import create_pdecode
30 from openpower
.decoder
.power_decoder2
import PowerDecode2
, SVP64PrefixDecoder
31 from openpower
.decoder
.decode2execute1
import IssuerDecode2ToOperand
32 from openpower
.decoder
.decode2execute1
import Data
33 from openpower
.decoder
.power_enums
import (MicrOp
, SVP64PredInt
, SVP64PredCR
,
35 from openpower
.state
import CoreState
36 from openpower
.consts
import (CR
, SVP64CROffs
)
37 from soc
.experiment
.testmem
import TestMemory
# test only for instructions
38 from soc
.regfile
.regfiles
import StateRegs
, FastRegs
39 from soc
.simple
.core
import NonProductionCore
40 from soc
.config
.test
.test_loadstore
import TestMemPspec
41 from soc
.config
.ifetch
import ConfigFetchUnit
42 from soc
.debug
.dmi
import CoreDebug
, DMIInterface
43 from soc
.debug
.jtag
import JTAG
44 from soc
.config
.pinouts
import get_pinspecs
45 from soc
.interrupts
.xics
import XICS_ICP
, XICS_ICS
46 from soc
.bus
.simple_gpio
import SimpleGPIO
47 from soc
.bus
.SPBlock512W64B8W
import SPBlock512W64B8W
48 from soc
.clock
.select
import ClockSelect
49 from soc
.clock
.dummypll
import DummyPLL
50 from openpower
.sv
.svstate
import SVSTATERec
51 from soc
.experiment
.icache
import ICache
53 from nmutil
.util
import rising_edge
56 def get_insn(f_instr_o
, pc
):
57 if f_instr_o
.width
== 32:
60 # 64-bit: bit 2 of pc decides which word to select
61 return f_instr_o
.word_select(pc
[2], 32)
63 # gets state input or reads from state regfile
66 def state_get(m
, core_rst
, state_i
, name
, regfile
, regnum
):
70 res
= Signal(64, reset_less
=True, name
=name
)
71 res_ok_delay
= Signal(name
="%s_ok_delay" % name
)
73 sync
+= res_ok_delay
.eq(~state_i
.ok
)
74 with m
.If(state_i
.ok
):
75 # incoming override (start from pc_i)
76 comb
+= res
.eq(state_i
.data
)
78 # otherwise read StateRegs regfile for PC...
79 comb
+= regfile
.ren
.eq(1 << regnum
)
80 # ... but on a 1-clock delay
81 with m
.If(res_ok_delay
):
82 comb
+= res
.eq(regfile
.o_data
)
86 def get_predint(m
, mask
, name
):
87 """decode SVP64 predicate integer mask field to reg number and invert
88 this is identical to the equivalent function in ISACaller except that
89 it doesn't read the INT directly, it just decodes "what needs to be done"
90 i.e. which INT reg, whether it is shifted and whether it is bit-inverted.
92 * all1s is set to indicate that no mask is to be applied.
93 * regread indicates the GPR register number to be read
94 * invert is set to indicate that the register value is to be inverted
95 * unary indicates that the contents of the register is to be shifted 1<<r3
98 regread
= Signal(5, name
=name
+"regread")
99 invert
= Signal(name
=name
+"invert")
100 unary
= Signal(name
=name
+"unary")
101 all1s
= Signal(name
=name
+"all1s")
103 with m
.Case(SVP64PredInt
.ALWAYS
.value
):
104 comb
+= all1s
.eq(1) # use 0b1111 (all ones)
105 with m
.Case(SVP64PredInt
.R3_UNARY
.value
):
106 comb
+= regread
.eq(3)
107 comb
+= unary
.eq(1) # 1<<r3 - shift r3 (single bit)
108 with m
.Case(SVP64PredInt
.R3
.value
):
109 comb
+= regread
.eq(3)
110 with m
.Case(SVP64PredInt
.R3_N
.value
):
111 comb
+= regread
.eq(3)
113 with m
.Case(SVP64PredInt
.R10
.value
):
114 comb
+= regread
.eq(10)
115 with m
.Case(SVP64PredInt
.R10_N
.value
):
116 comb
+= regread
.eq(10)
118 with m
.Case(SVP64PredInt
.R30
.value
):
119 comb
+= regread
.eq(30)
120 with m
.Case(SVP64PredInt
.R30_N
.value
):
121 comb
+= regread
.eq(30)
123 return regread
, invert
, unary
, all1s
126 def get_predcr(m
, mask
, name
):
127 """decode SVP64 predicate CR to reg number field and invert status
128 this is identical to _get_predcr in ISACaller
131 idx
= Signal(2, name
=name
+"idx")
132 invert
= Signal(name
=name
+"crinvert")
134 with m
.Case(SVP64PredCR
.LT
.value
):
135 comb
+= idx
.eq(CR
.LT
)
137 with m
.Case(SVP64PredCR
.GE
.value
):
138 comb
+= idx
.eq(CR
.LT
)
140 with m
.Case(SVP64PredCR
.GT
.value
):
141 comb
+= idx
.eq(CR
.GT
)
143 with m
.Case(SVP64PredCR
.LE
.value
):
144 comb
+= idx
.eq(CR
.GT
)
146 with m
.Case(SVP64PredCR
.EQ
.value
):
147 comb
+= idx
.eq(CR
.EQ
)
149 with m
.Case(SVP64PredCR
.NE
.value
):
150 comb
+= idx
.eq(CR
.EQ
)
152 with m
.Case(SVP64PredCR
.SO
.value
):
153 comb
+= idx
.eq(CR
.SO
)
155 with m
.Case(SVP64PredCR
.NS
.value
):
156 comb
+= idx
.eq(CR
.SO
)
161 # Fetch Finite State Machine.
162 # WARNING: there are currently DriverConflicts but it's actually working.
163 # TODO, here: everything that is global in nature, information from the
164 # main TestIssuerInternal, needs to move to either ispec() or ospec().
165 # not only that: TestIssuerInternal.imem can entirely move into here
166 # because imem is only ever accessed inside the FetchFSM.
167 class FetchFSM(ControlBase
):
168 def __init__(self
, allow_overlap
, svp64_en
, imem
, core_rst
,
170 dbg
, core
, svstate
, nia
, is_svp64_mode
):
171 self
.allow_overlap
= allow_overlap
172 self
.svp64_en
= svp64_en
174 self
.core_rst
= core_rst
175 self
.pdecode2
= pdecode2
176 self
.cur_state
= cur_state
179 self
.svstate
= svstate
181 self
.is_svp64_mode
= is_svp64_mode
183 # set up pipeline ControlBase and allocate i/o specs
184 # (unusual: normally done by the Pipeline API)
185 super().__init
__(stage
=self
)
186 self
.p
.i_data
, self
.n
.o_data
= self
.new_specs(None)
187 self
.i
, self
.o
= self
.p
.i_data
, self
.n
.o_data
189 # next 3 functions are Stage API Compliance
190 def setup(self
, m
, i
):
199 def elaborate(self
, platform
):
202 this FSM performs fetch of raw instruction data, partial-decodes
203 it 32-bit at a time to detect SVP64 prefixes, and will optionally
204 read a 2nd 32-bit quantity if that occurs.
206 m
= super().elaborate(platform
)
211 svstate
= self
.svstate
213 is_svp64_mode
= self
.is_svp64_mode
214 fetch_pc_o_ready
= self
.p
.o_ready
215 fetch_pc_i_valid
= self
.p
.i_valid
216 fetch_insn_o_valid
= self
.n
.o_valid
217 fetch_insn_i_ready
= self
.n
.i_ready
221 pdecode2
= self
.pdecode2
222 cur_state
= self
.cur_state
223 dec_opcode_o
= pdecode2
.dec
.raw_opcode_in
# raw opcode
225 msr_read
= Signal(reset
=1)
227 # don't read msr every cycle
228 staterf
= self
.core
.regs
.rf
['state']
229 state_r_msr
= staterf
.r_ports
['msr'] # MSR rd
231 comb
+= state_r_msr
.ren
.eq(0)
233 with m
.FSM(name
='fetch_fsm'):
236 with m
.State("IDLE"):
237 with m
.If(~dbg
.stopping_o
):
238 comb
+= fetch_pc_o_ready
.eq(1)
239 with m
.If(fetch_pc_i_valid
):
240 # instruction allowed to go: start by reading the PC
241 # capture the PC and also drop it into Insn Memory
242 # we have joined a pair of combinatorial memory
243 # lookups together. this is Generally Bad.
244 comb
+= self
.imem
.a_pc_i
.eq(pc
)
245 comb
+= self
.imem
.a_i_valid
.eq(1)
246 comb
+= self
.imem
.f_i_valid
.eq(1)
247 sync
+= cur_state
.pc
.eq(pc
)
248 sync
+= cur_state
.svstate
.eq(svstate
) # and svstate
250 # initiate read of MSR. arrives one clock later
251 comb
+= state_r_msr
.ren
.eq(1 << StateRegs
.MSR
)
252 sync
+= msr_read
.eq(0)
254 m
.next
= "INSN_READ" # move to "wait for bus" phase
256 # dummy pause to find out why simulation is not keeping up
257 with m
.State("INSN_READ"):
258 if self
.allow_overlap
:
259 stopping
= dbg
.stopping_o
263 # stopping: jump back to idle
266 # one cycle later, msr/sv read arrives. valid only once.
267 with m
.If(~msr_read
):
268 sync
+= msr_read
.eq(1) # yeah don't read it again
269 sync
+= cur_state
.msr
.eq(state_r_msr
.o_data
)
270 with m
.If(self
.imem
.f_busy_o
): # zzz...
271 # busy: stay in wait-read
272 comb
+= self
.imem
.a_i_valid
.eq(1)
273 comb
+= self
.imem
.f_i_valid
.eq(1)
275 # not busy: instruction fetched
276 insn
= get_insn(self
.imem
.f_instr_o
, cur_state
.pc
)
279 # decode the SVP64 prefix, if any
280 comb
+= svp64
.raw_opcode_in
.eq(insn
)
281 comb
+= svp64
.bigendian
.eq(self
.core_bigendian_i
)
282 # pass the decoded prefix (if any) to PowerDecoder2
283 sync
+= pdecode2
.sv_rm
.eq(svp64
.svp64_rm
)
284 sync
+= pdecode2
.is_svp64_mode
.eq(is_svp64_mode
)
285 # remember whether this is a prefixed instruction,
286 # so the FSM can readily loop when VL==0
287 sync
+= is_svp64_mode
.eq(svp64
.is_svp64_mode
)
288 # calculate the address of the following instruction
289 insn_size
= Mux(svp64
.is_svp64_mode
, 8, 4)
290 sync
+= nia
.eq(cur_state
.pc
+ insn_size
)
291 with m
.If(~svp64
.is_svp64_mode
):
292 # with no prefix, store the instruction
293 # and hand it directly to the next FSM
294 sync
+= dec_opcode_o
.eq(insn
)
295 m
.next
= "INSN_READY"
297 # fetch the rest of the instruction from memory
298 comb
+= self
.imem
.a_pc_i
.eq(cur_state
.pc
+ 4)
299 comb
+= self
.imem
.a_i_valid
.eq(1)
300 comb
+= self
.imem
.f_i_valid
.eq(1)
301 m
.next
= "INSN_READ2"
303 # not SVP64 - 32-bit only
304 sync
+= nia
.eq(cur_state
.pc
+ 4)
305 sync
+= dec_opcode_o
.eq(insn
)
306 m
.next
= "INSN_READY"
308 with m
.State("INSN_READ2"):
309 with m
.If(self
.imem
.f_busy_o
): # zzz...
310 # busy: stay in wait-read
311 comb
+= self
.imem
.a_i_valid
.eq(1)
312 comb
+= self
.imem
.f_i_valid
.eq(1)
314 # not busy: instruction fetched
315 insn
= get_insn(self
.imem
.f_instr_o
, cur_state
.pc
+4)
316 sync
+= dec_opcode_o
.eq(insn
)
317 m
.next
= "INSN_READY"
318 # TODO: probably can start looking at pdecode2.rm_dec
319 # here or maybe even in INSN_READ state, if svp64_mode
320 # detected, in order to trigger - and wait for - the
323 pmode
= pdecode2
.rm_dec
.predmode
325 if pmode != SVP64PredMode.ALWAYS.value:
326 fire predicate loading FSM and wait before
329 sync += self.srcmask.eq(-1) # set to all 1s
330 sync += self.dstmask.eq(-1) # set to all 1s
331 m.next = "INSN_READY"
334 with m
.State("INSN_READY"):
335 # hand over the instruction, to be decoded
336 comb
+= fetch_insn_o_valid
.eq(1)
337 with m
.If(fetch_insn_i_ready
):
340 # whatever was done above, over-ride it if core reset is held
341 with m
.If(self
.core_rst
):
347 class TestIssuerInternal(Elaboratable
):
348 """TestIssuer - reads instructions from TestMemory and issues them
350 efficiency and speed is not the main goal here: functional correctness
351 and code clarity is. optimisations (which almost 100% interfere with
352 easy understanding) come later.
355 def __init__(self
, pspec
):
357 # test is SVP64 is to be enabled
358 self
.svp64_en
= hasattr(pspec
, "svp64") and (pspec
.svp64
== True)
360 # and if regfiles are reduced
361 self
.regreduce_en
= (hasattr(pspec
, "regreduce") and
362 (pspec
.regreduce
== True))
364 # and if overlap requested
365 self
.allow_overlap
= (hasattr(pspec
, "allow_overlap") and
366 (pspec
.allow_overlap
== True))
368 # JTAG interface. add this right at the start because if it's
369 # added it *modifies* the pspec, by adding enable/disable signals
370 # for parts of the rest of the core
371 self
.jtag_en
= hasattr(pspec
, "debug") and pspec
.debug
== 'jtag'
372 self
.dbg_domain
= "sync" # sigh "dbgsunc" too problematic
373 # self.dbg_domain = "dbgsync" # domain for DMI/JTAG clock
375 # XXX MUST keep this up-to-date with litex, and
376 # soc-cocotb-sim, and err.. all needs sorting out, argh
379 'eint', 'gpio', 'mspi0',
380 # 'mspi1', - disabled for now
381 # 'pwm', 'sd0', - disabled for now
383 self
.jtag
= JTAG(get_pinspecs(subset
=subset
),
384 domain
=self
.dbg_domain
)
385 # add signals to pspec to enable/disable icache and dcache
386 # (or data and intstruction wishbone if icache/dcache not included)
387 # https://bugs.libre-soc.org/show_bug.cgi?id=520
388 # TODO: do we actually care if these are not domain-synchronised?
389 # honestly probably not.
390 pspec
.wb_icache_en
= self
.jtag
.wb_icache_en
391 pspec
.wb_dcache_en
= self
.jtag
.wb_dcache_en
392 self
.wb_sram_en
= self
.jtag
.wb_sram_en
394 self
.wb_sram_en
= Const(1)
396 # add 4k sram blocks?
397 self
.sram4x4k
= (hasattr(pspec
, "sram4x4kblock") and
398 pspec
.sram4x4kblock
== True)
402 self
.sram4k
.append(SPBlock512W64B8W(name
="sram4k_%d" % i
,
406 # add interrupt controller?
407 self
.xics
= hasattr(pspec
, "xics") and pspec
.xics
== True
409 self
.xics_icp
= XICS_ICP()
410 self
.xics_ics
= XICS_ICS()
411 self
.int_level_i
= self
.xics_ics
.int_level_i
413 # add GPIO peripheral?
414 self
.gpio
= hasattr(pspec
, "gpio") and pspec
.gpio
== True
416 self
.simple_gpio
= SimpleGPIO()
417 self
.gpio_o
= self
.simple_gpio
.gpio_o
419 # main instruction core. suitable for prototyping / demo only
420 self
.core
= core
= NonProductionCore(pspec
)
421 self
.core_rst
= ResetSignal("coresync")
423 # instruction decoder. goes into Trap Record
424 #pdecode = create_pdecode()
425 self
.cur_state
= CoreState("cur") # current state (MSR/PC/SVSTATE)
426 self
.pdecode2
= PowerDecode2(None, state
=self
.cur_state
,
427 opkls
=IssuerDecode2ToOperand
,
428 svp64_en
=self
.svp64_en
,
429 regreduce_en
=self
.regreduce_en
)
430 pdecode
= self
.pdecode2
.dec
433 self
.svp64
= SVP64PrefixDecoder() # for decoding SVP64 prefix
435 # Test Instruction memory
436 if hasattr(core
, "icache"):
437 # XXX BLECH! use pspec to transfer the I-Cache to ConfigFetchUnit
438 # truly dreadful. needs a huge reorg.
439 pspec
.icache
= core
.icache
440 self
.imem
= ConfigFetchUnit(pspec
).fu
443 self
.dbg
= CoreDebug()
445 # instruction go/monitor
446 self
.pc_o
= Signal(64, reset_less
=True)
447 self
.pc_i
= Data(64, "pc_i") # set "ok" to indicate "please change me"
448 self
.svstate_i
= Data(64, "svstate_i") # ditto
449 self
.core_bigendian_i
= Signal() # TODO: set based on MSR.LE
450 self
.busy_o
= Signal(reset_less
=True)
451 self
.memerr_o
= Signal(reset_less
=True)
453 # STATE regfile read /write ports for PC, MSR, SVSTATE
454 staterf
= self
.core
.regs
.rf
['state']
455 self
.state_r_pc
= staterf
.r_ports
['cia'] # PC rd
456 self
.state_w_pc
= staterf
.w_ports
['d_wr1'] # PC wr
457 self
.state_r_sv
= staterf
.r_ports
['sv'] # SVSTATE rd
458 self
.state_w_sv
= staterf
.w_ports
['sv'] # SVSTATE wr
460 # DMI interface access
461 intrf
= self
.core
.regs
.rf
['int']
462 crrf
= self
.core
.regs
.rf
['cr']
463 xerrf
= self
.core
.regs
.rf
['xer']
464 self
.int_r
= intrf
.r_ports
['dmi'] # INT read
465 self
.cr_r
= crrf
.r_ports
['full_cr_dbg'] # CR read
466 self
.xer_r
= xerrf
.r_ports
['full_xer'] # XER read
470 self
.int_pred
= intrf
.r_ports
['pred'] # INT predicate read
471 self
.cr_pred
= crrf
.r_ports
['cr_pred'] # CR predicate read
473 # hack method of keeping an eye on whether branch/trap set the PC
474 self
.state_nia
= self
.core
.regs
.rf
['state'].w_ports
['nia']
475 self
.state_nia
.wen
.name
= 'state_nia_wen'
477 # pulse to synchronize the simulator at instruction end
478 self
.insn_done
= Signal()
480 # indicate any instruction still outstanding, in execution
481 self
.any_busy
= Signal()
484 # store copies of predicate masks
485 self
.srcmask
= Signal(64)
486 self
.dstmask
= Signal(64)
488 def fetch_predicate_fsm(self
, m
,
489 pred_insn_i_valid
, pred_insn_o_ready
,
490 pred_mask_o_valid
, pred_mask_i_ready
):
491 """fetch_predicate_fsm - obtains (constructs in the case of CR)
492 src/dest predicate masks
494 https://bugs.libre-soc.org/show_bug.cgi?id=617
495 the predicates can be read here, by using IntRegs r_ports['pred']
496 or CRRegs r_ports['pred']. in the case of CRs it will have to
497 be done through multiple reads, extracting one relevant at a time.
498 later, a faster way would be to use the 32-bit-wide CR port but
499 this is more complex decoding, here. equivalent code used in
500 ISACaller is "from openpower.decoder.isa.caller import get_predcr"
502 note: this ENTIRE FSM is not to be called when svp64 is disabled
506 pdecode2
= self
.pdecode2
507 rm_dec
= pdecode2
.rm_dec
# SVP64RMModeDecode
508 predmode
= rm_dec
.predmode
509 srcpred
, dstpred
= rm_dec
.srcpred
, rm_dec
.dstpred
510 cr_pred
, int_pred
= self
.cr_pred
, self
.int_pred
# read regfiles
511 # get src/dst step, so we can skip already used mask bits
512 cur_state
= self
.cur_state
513 srcstep
= cur_state
.svstate
.srcstep
514 dststep
= cur_state
.svstate
.dststep
515 cur_vl
= cur_state
.svstate
.vl
518 sregread
, sinvert
, sunary
, sall1s
= get_predint(m
, srcpred
, 's')
519 dregread
, dinvert
, dunary
, dall1s
= get_predint(m
, dstpred
, 'd')
520 sidx
, scrinvert
= get_predcr(m
, srcpred
, 's')
521 didx
, dcrinvert
= get_predcr(m
, dstpred
, 'd')
523 # store fetched masks, for either intpred or crpred
524 # when src/dst step is not zero, the skipped mask bits need to be
525 # shifted-out, before actually storing them in src/dest mask
526 new_srcmask
= Signal(64, reset_less
=True)
527 new_dstmask
= Signal(64, reset_less
=True)
529 with m
.FSM(name
="fetch_predicate"):
531 with m
.State("FETCH_PRED_IDLE"):
532 comb
+= pred_insn_o_ready
.eq(1)
533 with m
.If(pred_insn_i_valid
):
534 with m
.If(predmode
== SVP64PredMode
.INT
):
535 # skip fetching destination mask register, when zero
537 sync
+= new_dstmask
.eq(-1)
538 # directly go to fetch source mask register
539 # guaranteed not to be zero (otherwise predmode
540 # would be SVP64PredMode.ALWAYS, not INT)
541 comb
+= int_pred
.addr
.eq(sregread
)
542 comb
+= int_pred
.ren
.eq(1)
543 m
.next
= "INT_SRC_READ"
544 # fetch destination predicate register
546 comb
+= int_pred
.addr
.eq(dregread
)
547 comb
+= int_pred
.ren
.eq(1)
548 m
.next
= "INT_DST_READ"
549 with m
.Elif(predmode
== SVP64PredMode
.CR
):
550 # go fetch masks from the CR register file
551 sync
+= new_srcmask
.eq(0)
552 sync
+= new_dstmask
.eq(0)
555 sync
+= self
.srcmask
.eq(-1)
556 sync
+= self
.dstmask
.eq(-1)
557 m
.next
= "FETCH_PRED_DONE"
559 with m
.State("INT_DST_READ"):
560 # store destination mask
561 inv
= Repl(dinvert
, 64)
563 # set selected mask bit for 1<<r3 mode
564 dst_shift
= Signal(range(64))
565 comb
+= dst_shift
.eq(self
.int_pred
.o_data
& 0b111111)
566 sync
+= new_dstmask
.eq(1 << dst_shift
)
568 # invert mask if requested
569 sync
+= new_dstmask
.eq(self
.int_pred
.o_data ^ inv
)
570 # skip fetching source mask register, when zero
572 sync
+= new_srcmask
.eq(-1)
573 m
.next
= "FETCH_PRED_SHIFT_MASK"
574 # fetch source predicate register
576 comb
+= int_pred
.addr
.eq(sregread
)
577 comb
+= int_pred
.ren
.eq(1)
578 m
.next
= "INT_SRC_READ"
580 with m
.State("INT_SRC_READ"):
582 inv
= Repl(sinvert
, 64)
584 # set selected mask bit for 1<<r3 mode
585 src_shift
= Signal(range(64))
586 comb
+= src_shift
.eq(self
.int_pred
.o_data
& 0b111111)
587 sync
+= new_srcmask
.eq(1 << src_shift
)
589 # invert mask if requested
590 sync
+= new_srcmask
.eq(self
.int_pred
.o_data ^ inv
)
591 m
.next
= "FETCH_PRED_SHIFT_MASK"
593 # fetch masks from the CR register file
594 # implements the following loop:
595 # idx, inv = get_predcr(mask)
597 # for cr_idx in range(vl):
598 # cr = crl[cr_idx + SVP64CROffs.CRPred] # takes one cycle
600 # mask |= 1 << cr_idx
602 with m
.State("CR_READ"):
603 # CR index to be read, which will be ready by the next cycle
604 cr_idx
= Signal
.like(cur_vl
, reset_less
=True)
605 # submit the read operation to the regfile
606 with m
.If(cr_idx
!= cur_vl
):
607 # the CR read port is unary ...
609 # ... in MSB0 convention ...
610 # ren = 1 << (7 - cr_idx)
611 # ... and with an offset:
612 # ren = 1 << (7 - off - cr_idx)
613 idx
= SVP64CROffs
.CRPred
+ cr_idx
614 comb
+= cr_pred
.ren
.eq(1 << (7 - idx
))
615 # signal data valid in the next cycle
616 cr_read
= Signal(reset_less
=True)
617 sync
+= cr_read
.eq(1)
618 # load the next index
619 sync
+= cr_idx
.eq(cr_idx
+ 1)
622 sync
+= cr_read
.eq(0)
624 m
.next
= "FETCH_PRED_SHIFT_MASK"
626 # compensate for the one cycle delay on the regfile
627 cur_cr_idx
= Signal
.like(cur_vl
)
628 comb
+= cur_cr_idx
.eq(cr_idx
- 1)
629 # read the CR field, select the appropriate bit
633 comb
+= cr_field
.eq(cr_pred
.o_data
)
634 comb
+= scr_bit
.eq(cr_field
.bit_select(sidx
, 1)
636 comb
+= dcr_bit
.eq(cr_field
.bit_select(didx
, 1)
638 # set the corresponding mask bit
639 bit_to_set
= Signal
.like(self
.srcmask
)
640 comb
+= bit_to_set
.eq(1 << cur_cr_idx
)
642 sync
+= new_srcmask
.eq(new_srcmask | bit_to_set
)
644 sync
+= new_dstmask
.eq(new_dstmask | bit_to_set
)
646 with m
.State("FETCH_PRED_SHIFT_MASK"):
647 # shift-out skipped mask bits
648 sync
+= self
.srcmask
.eq(new_srcmask
>> srcstep
)
649 sync
+= self
.dstmask
.eq(new_dstmask
>> dststep
)
650 m
.next
= "FETCH_PRED_DONE"
652 with m
.State("FETCH_PRED_DONE"):
653 comb
+= pred_mask_o_valid
.eq(1)
654 with m
.If(pred_mask_i_ready
):
655 m
.next
= "FETCH_PRED_IDLE"
657 def issue_fsm(self
, m
, core
, pc_changed
, sv_changed
, nia
,
658 dbg
, core_rst
, is_svp64_mode
,
659 fetch_pc_o_ready
, fetch_pc_i_valid
,
660 fetch_insn_o_valid
, fetch_insn_i_ready
,
661 pred_insn_i_valid
, pred_insn_o_ready
,
662 pred_mask_o_valid
, pred_mask_i_ready
,
663 exec_insn_i_valid
, exec_insn_o_ready
,
664 exec_pc_o_valid
, exec_pc_i_ready
):
667 decode / issue FSM. this interacts with the "fetch" FSM
668 through fetch_insn_ready/valid (incoming) and fetch_pc_ready/valid
669 (outgoing). also interacts with the "execute" FSM
670 through exec_insn_ready/valid (outgoing) and exec_pc_ready/valid
672 SVP64 RM prefixes have already been set up by the
673 "fetch" phase, so execute is fairly straightforward.
678 pdecode2
= self
.pdecode2
679 cur_state
= self
.cur_state
682 dec_opcode_i
= pdecode2
.dec
.raw_opcode_in
# raw opcode
684 # for updating svstate (things like srcstep etc.)
685 update_svstate
= Signal() # set this (below) if updating
686 new_svstate
= SVSTATERec("new_svstate")
687 comb
+= new_svstate
.eq(cur_state
.svstate
)
689 # precalculate srcstep+1 and dststep+1
690 cur_srcstep
= cur_state
.svstate
.srcstep
691 cur_dststep
= cur_state
.svstate
.dststep
692 next_srcstep
= Signal
.like(cur_srcstep
)
693 next_dststep
= Signal
.like(cur_dststep
)
694 comb
+= next_srcstep
.eq(cur_state
.svstate
.srcstep
+1)
695 comb
+= next_dststep
.eq(cur_state
.svstate
.dststep
+1)
697 # note if an exception happened. in a pipelined or OoO design
698 # this needs to be accompanied by "shadowing" (or stalling)
699 exc_happened
= self
.core
.o
.exc_happened
700 # also note instruction fetch failed
701 if hasattr(core
, "icache"):
702 fetch_failed
= core
.icache
.i_out
.fetch_failed
704 fetch_failed
= Const(0, 1)
705 # set to fault in decoder
706 # update (highest priority) instruction fault
707 comb
+= pdecode2
.instr_fault
.eq(fetch_failed
)
709 with m
.FSM(name
="issue_fsm"):
711 # sync with the "fetch" phase which is reading the instruction
712 # at this point, there is no instruction running, that
713 # could inadvertently update the PC.
714 with m
.State("ISSUE_START"):
715 # wait on "core stop" release, before next fetch
716 # need to do this here, in case we are in a VL==0 loop
717 with m
.If(~dbg
.core_stop_o
& ~core_rst
):
718 comb
+= fetch_pc_i_valid
.eq(1) # tell fetch to start
719 with m
.If(fetch_pc_o_ready
): # fetch acknowledged us
722 # tell core it's stopped, and acknowledge debug handshake
723 comb
+= dbg
.core_stopped_i
.eq(1)
724 # while stopped, allow updating the PC and SVSTATE
725 with m
.If(self
.pc_i
.ok
):
726 comb
+= self
.state_w_pc
.wen
.eq(1 << StateRegs
.PC
)
727 comb
+= self
.state_w_pc
.i_data
.eq(self
.pc_i
.data
)
728 sync
+= pc_changed
.eq(1)
729 with m
.If(self
.svstate_i
.ok
):
730 comb
+= new_svstate
.eq(self
.svstate_i
.data
)
731 comb
+= update_svstate
.eq(1)
732 sync
+= sv_changed
.eq(1)
734 # wait for an instruction to arrive from Fetch
735 with m
.State("INSN_WAIT"):
736 if self
.allow_overlap
:
737 stopping
= dbg
.stopping_o
741 # stopping: jump back to idle
742 m
.next
= "ISSUE_START"
744 comb
+= fetch_insn_i_ready
.eq(1)
745 with m
.If(fetch_insn_o_valid
):
746 # loop into ISSUE_START if it's a SVP64 instruction
747 # and VL == 0. this because VL==0 is a for-loop
748 # from 0 to 0 i.e. always, always a NOP.
749 cur_vl
= cur_state
.svstate
.vl
750 with m
.If(is_svp64_mode
& (cur_vl
== 0)):
751 # update the PC before fetching the next instruction
752 # since we are in a VL==0 loop, no instruction was
753 # executed that we could be overwriting
754 comb
+= self
.state_w_pc
.wen
.eq(1 << StateRegs
.PC
)
755 comb
+= self
.state_w_pc
.i_data
.eq(nia
)
756 comb
+= self
.insn_done
.eq(1)
757 m
.next
= "ISSUE_START"
760 m
.next
= "PRED_START" # fetching predicate
762 m
.next
= "DECODE_SV" # skip predication
764 with m
.State("PRED_START"):
765 comb
+= pred_insn_i_valid
.eq(1) # tell fetch_pred to start
766 with m
.If(pred_insn_o_ready
): # fetch_pred acknowledged us
769 with m
.State("MASK_WAIT"):
770 comb
+= pred_mask_i_ready
.eq(1) # ready to receive the masks
771 with m
.If(pred_mask_o_valid
): # predication masks are ready
774 # skip zeros in predicate
775 with m
.State("PRED_SKIP"):
776 with m
.If(~is_svp64_mode
):
777 m
.next
= "DECODE_SV" # nothing to do
780 pred_src_zero
= pdecode2
.rm_dec
.pred_sz
781 pred_dst_zero
= pdecode2
.rm_dec
.pred_dz
783 # new srcstep, after skipping zeros
784 skip_srcstep
= Signal
.like(cur_srcstep
)
785 # value to be added to the current srcstep
786 src_delta
= Signal
.like(cur_srcstep
)
787 # add leading zeros to srcstep, if not in zero mode
788 with m
.If(~pred_src_zero
):
789 # priority encoder (count leading zeros)
790 # append guard bit, in case the mask is all zeros
791 pri_enc_src
= PriorityEncoder(65)
792 m
.submodules
.pri_enc_src
= pri_enc_src
793 comb
+= pri_enc_src
.i
.eq(Cat(self
.srcmask
,
795 comb
+= src_delta
.eq(pri_enc_src
.o
)
796 # apply delta to srcstep
797 comb
+= skip_srcstep
.eq(cur_srcstep
+ src_delta
)
798 # shift-out all leading zeros from the mask
799 # plus the leading "one" bit
800 # TODO count leading zeros and shift-out the zero
801 # bits, in the same step, in hardware
802 sync
+= self
.srcmask
.eq(self
.srcmask
>> (src_delta
+1))
804 # same as above, but for dststep
805 skip_dststep
= Signal
.like(cur_dststep
)
806 dst_delta
= Signal
.like(cur_dststep
)
807 with m
.If(~pred_dst_zero
):
808 pri_enc_dst
= PriorityEncoder(65)
809 m
.submodules
.pri_enc_dst
= pri_enc_dst
810 comb
+= pri_enc_dst
.i
.eq(Cat(self
.dstmask
,
812 comb
+= dst_delta
.eq(pri_enc_dst
.o
)
813 comb
+= skip_dststep
.eq(cur_dststep
+ dst_delta
)
814 sync
+= self
.dstmask
.eq(self
.dstmask
>> (dst_delta
+1))
816 # TODO: initialize mask[VL]=1 to avoid passing past VL
817 with m
.If((skip_srcstep
>= cur_vl
) |
818 (skip_dststep
>= cur_vl
)):
819 # end of VL loop. Update PC and reset src/dst step
820 comb
+= self
.state_w_pc
.wen
.eq(1 << StateRegs
.PC
)
821 comb
+= self
.state_w_pc
.i_data
.eq(nia
)
822 comb
+= new_svstate
.srcstep
.eq(0)
823 comb
+= new_svstate
.dststep
.eq(0)
824 comb
+= update_svstate
.eq(1)
825 # synchronize with the simulator
826 comb
+= self
.insn_done
.eq(1)
828 m
.next
= "ISSUE_START"
830 # update new src/dst step
831 comb
+= new_svstate
.srcstep
.eq(skip_srcstep
)
832 comb
+= new_svstate
.dststep
.eq(skip_dststep
)
833 comb
+= update_svstate
.eq(1)
837 # pass predicate mask bits through to satellite decoders
838 # TODO: for SIMD this will be *multiple* bits
839 sync
+= core
.i
.sv_pred_sm
.eq(self
.srcmask
[0])
840 sync
+= core
.i
.sv_pred_dm
.eq(self
.dstmask
[0])
842 # after src/dst step have been updated, we are ready
843 # to decode the instruction
844 with m
.State("DECODE_SV"):
845 # decode the instruction
846 sync
+= core
.i
.e
.eq(pdecode2
.e
)
847 sync
+= core
.i
.state
.eq(cur_state
)
848 sync
+= core
.i
.raw_insn_i
.eq(dec_opcode_i
)
849 sync
+= core
.i
.bigendian_i
.eq(self
.core_bigendian_i
)
851 sync
+= core
.i
.sv_rm
.eq(pdecode2
.sv_rm
)
852 # set RA_OR_ZERO detection in satellite decoders
853 sync
+= core
.i
.sv_a_nz
.eq(pdecode2
.sv_a_nz
)
854 # and svp64 detection
855 sync
+= core
.i
.is_svp64_mode
.eq(is_svp64_mode
)
856 # and svp64 bit-rev'd ldst mode
857 ldst_dec
= pdecode2
.use_svp64_ldst_dec
858 sync
+= core
.i
.use_svp64_ldst_dec
.eq(ldst_dec
)
859 # after decoding, reset any previous exception condition,
860 # allowing it to be set again during the next execution
861 sync
+= pdecode2
.ldst_exc
.eq(0)
863 m
.next
= "INSN_EXECUTE" # move to "execute"
865 # handshake with execution FSM, move to "wait" once acknowledged
866 with m
.State("INSN_EXECUTE"):
867 comb
+= exec_insn_i_valid
.eq(1) # trigger execute
868 with m
.If(exec_insn_o_ready
): # execute acknowledged us
869 m
.next
= "EXECUTE_WAIT"
871 with m
.State("EXECUTE_WAIT"):
872 # wait on "core stop" release, at instruction end
873 # need to do this here, in case we are in a VL>1 loop
874 with m
.If(~dbg
.core_stop_o
& ~core_rst
):
875 comb
+= exec_pc_i_ready
.eq(1)
876 # see https://bugs.libre-soc.org/show_bug.cgi?id=636
877 # the exception info needs to be blatted into
878 # pdecode.ldst_exc, and the instruction "re-run".
879 # when ldst_exc.happened is set, the PowerDecoder2
880 # reacts very differently: it re-writes the instruction
881 # with a "trap" (calls PowerDecoder2.trap()) which
882 # will *overwrite* whatever was requested and jump the
883 # PC to the exception address, as well as alter MSR.
884 # nothing else needs to be done other than to note
885 # the change of PC and MSR (and, later, SVSTATE)
886 with m
.If(exc_happened
):
887 sync
+= pdecode2
.ldst_exc
.eq(core
.fus
.get_exc("ldst0"))
889 with m
.If(exec_pc_o_valid
):
891 # was this the last loop iteration?
893 cur_vl
= cur_state
.svstate
.vl
894 comb
+= is_last
.eq(next_srcstep
== cur_vl
)
896 # return directly to Decode if Execute generated an
898 with m
.If(pdecode2
.ldst_exc
.happened
):
901 # if either PC or SVSTATE were changed by the previous
902 # instruction, go directly back to Fetch, without
903 # updating either PC or SVSTATE
904 with m
.Elif(pc_changed | sv_changed
):
905 m
.next
= "ISSUE_START"
907 # also return to Fetch, when no output was a vector
908 # (regardless of SRCSTEP and VL), or when the last
909 # instruction was really the last one of the VL loop
910 with m
.Elif((~pdecode2
.loop_continue
) | is_last
):
911 # before going back to fetch, update the PC state
912 # register with the NIA.
913 # ok here we are not reading the branch unit.
914 # TODO: this just blithely overwrites whatever
915 # pipeline updated the PC
916 comb
+= self
.state_w_pc
.wen
.eq(1 << StateRegs
.PC
)
917 comb
+= self
.state_w_pc
.i_data
.eq(nia
)
918 # reset SRCSTEP before returning to Fetch
920 with m
.If(pdecode2
.loop_continue
):
921 comb
+= new_svstate
.srcstep
.eq(0)
922 comb
+= new_svstate
.dststep
.eq(0)
923 comb
+= update_svstate
.eq(1)
925 comb
+= new_svstate
.srcstep
.eq(0)
926 comb
+= new_svstate
.dststep
.eq(0)
927 comb
+= update_svstate
.eq(1)
928 m
.next
= "ISSUE_START"
930 # returning to Execute? then, first update SRCSTEP
932 comb
+= new_svstate
.srcstep
.eq(next_srcstep
)
933 comb
+= new_svstate
.dststep
.eq(next_dststep
)
934 comb
+= update_svstate
.eq(1)
935 # return to mask skip loop
939 comb
+= dbg
.core_stopped_i
.eq(1)
940 # while stopped, allow updating the PC and SVSTATE
941 with m
.If(self
.pc_i
.ok
):
942 comb
+= self
.state_w_pc
.wen
.eq(1 << StateRegs
.PC
)
943 comb
+= self
.state_w_pc
.i_data
.eq(self
.pc_i
.data
)
944 sync
+= pc_changed
.eq(1)
945 with m
.If(self
.svstate_i
.ok
):
946 comb
+= new_svstate
.eq(self
.svstate_i
.data
)
947 comb
+= update_svstate
.eq(1)
948 sync
+= sv_changed
.eq(1)
950 # check if svstate needs updating: if so, write it to State Regfile
951 with m
.If(update_svstate
):
952 comb
+= self
.state_w_sv
.wen
.eq(1 << StateRegs
.SVSTATE
)
953 comb
+= self
.state_w_sv
.i_data
.eq(new_svstate
)
954 sync
+= cur_state
.svstate
.eq(new_svstate
) # for next clock
956 def execute_fsm(self
, m
, core
, pc_changed
, sv_changed
,
957 exec_insn_i_valid
, exec_insn_o_ready
,
958 exec_pc_o_valid
, exec_pc_i_ready
):
961 execute FSM. this interacts with the "issue" FSM
962 through exec_insn_ready/valid (incoming) and exec_pc_ready/valid
963 (outgoing). SVP64 RM prefixes have already been set up by the
964 "issue" phase, so execute is fairly straightforward.
969 pdecode2
= self
.pdecode2
972 core_busy_o
= core
.n
.o_data
.busy_o
# core is busy
973 core_ivalid_i
= core
.p
.i_valid
# instruction is valid
975 with m
.FSM(name
="exec_fsm"):
977 # waiting for instruction bus (stays there until not busy)
978 with m
.State("INSN_START"):
979 comb
+= exec_insn_o_ready
.eq(1)
980 with m
.If(exec_insn_i_valid
):
981 comb
+= core_ivalid_i
.eq(1) # instruction is valid/issued
982 sync
+= sv_changed
.eq(0)
983 sync
+= pc_changed
.eq(0)
984 with m
.If(core
.p
.o_ready
): # only move if accepted
985 m
.next
= "INSN_ACTIVE" # move to "wait completion"
987 # instruction started: must wait till it finishes
988 with m
.State("INSN_ACTIVE"):
989 # note changes to PC and SVSTATE
990 with m
.If(self
.state_nia
.wen
& (1 << StateRegs
.SVSTATE
)):
991 sync
+= sv_changed
.eq(1)
992 with m
.If(self
.state_nia
.wen
& (1 << StateRegs
.PC
)):
993 sync
+= pc_changed
.eq(1)
994 with m
.If(~core_busy_o
): # instruction done!
995 comb
+= exec_pc_o_valid
.eq(1)
996 with m
.If(exec_pc_i_ready
):
997 # when finished, indicate "done".
998 # however, if there was an exception, the instruction
999 # is *not* yet done. this is an implementation
1000 # detail: we choose to implement exceptions by
1001 # taking the exception information from the LDST
1002 # unit, putting that *back* into the PowerDecoder2,
1003 # and *re-running the entire instruction*.
1004 # if we erroneously indicate "done" here, it is as if
1005 # there were *TWO* instructions:
1006 # 1) the failed LDST 2) a TRAP.
1007 with m
.If(~pdecode2
.ldst_exc
.happened
):
1008 comb
+= self
.insn_done
.eq(1)
1009 m
.next
= "INSN_START" # back to fetch
1011 def setup_peripherals(self
, m
):
1012 comb
, sync
= m
.d
.comb
, m
.d
.sync
1014 # okaaaay so the debug module must be in coresync clock domain
1015 # but NOT its reset signal. to cope with this, set every single
1016 # submodule explicitly in coresync domain, debug and JTAG
1017 # in their own one but using *external* reset.
1018 csd
= DomainRenamer("coresync")
1019 dbd
= DomainRenamer(self
.dbg_domain
)
1021 m
.submodules
.core
= core
= csd(self
.core
)
1022 # this _so_ needs sorting out. ICache is added down inside
1023 # LoadStore1 and is already a submodule of LoadStore1
1024 if not isinstance(self
.imem
, ICache
):
1025 m
.submodules
.imem
= imem
= csd(self
.imem
)
1026 m
.submodules
.dbg
= dbg
= dbd(self
.dbg
)
1028 m
.submodules
.jtag
= jtag
= dbd(self
.jtag
)
1029 # TODO: UART2GDB mux, here, from external pin
1030 # see https://bugs.libre-soc.org/show_bug.cgi?id=499
1031 sync
+= dbg
.dmi
.connect_to(jtag
.dmi
)
1033 cur_state
= self
.cur_state
1035 # 4x 4k SRAM blocks. these simply "exist", they get routed in litex
1037 for i
, sram
in enumerate(self
.sram4k
):
1038 m
.submodules
["sram4k_%d" % i
] = csd(sram
)
1039 comb
+= sram
.enable
.eq(self
.wb_sram_en
)
1041 # XICS interrupt handler
1043 m
.submodules
.xics_icp
= icp
= csd(self
.xics_icp
)
1044 m
.submodules
.xics_ics
= ics
= csd(self
.xics_ics
)
1045 comb
+= icp
.ics_i
.eq(ics
.icp_o
) # connect ICS to ICP
1046 sync
+= cur_state
.eint
.eq(icp
.core_irq_o
) # connect ICP to core
1048 # GPIO test peripheral
1050 m
.submodules
.simple_gpio
= simple_gpio
= csd(self
.simple_gpio
)
1052 # connect one GPIO output to ICS bit 15 (like in microwatt soc.vhdl)
1053 # XXX causes litex ECP5 test to get wrong idea about input and output
1054 # (but works with verilator sim *sigh*)
1055 # if self.gpio and self.xics:
1056 # comb += self.int_level_i[15].eq(simple_gpio.gpio_o[0])
1058 # instruction decoder
1059 pdecode
= create_pdecode()
1060 m
.submodules
.dec2
= pdecode2
= csd(self
.pdecode2
)
1062 m
.submodules
.svp64
= svp64
= csd(self
.svp64
)
1065 dmi
, d_reg
, d_cr
, d_xer
, = dbg
.dmi
, dbg
.d_gpr
, dbg
.d_cr
, dbg
.d_xer
1066 intrf
= self
.core
.regs
.rf
['int']
1068 # clock delay power-on reset
1069 cd_por
= ClockDomain(reset_less
=True)
1070 cd_sync
= ClockDomain()
1071 core_sync
= ClockDomain("coresync")
1072 m
.domains
+= cd_por
, cd_sync
, core_sync
1073 if self
.dbg_domain
!= "sync":
1074 dbg_sync
= ClockDomain(self
.dbg_domain
)
1075 m
.domains
+= dbg_sync
1077 ti_rst
= Signal(reset_less
=True)
1078 delay
= Signal(range(4), reset
=3)
1079 with m
.If(delay
!= 0):
1080 m
.d
.por
+= delay
.eq(delay
- 1)
1081 comb
+= cd_por
.clk
.eq(ClockSignal())
1083 # power-on reset delay
1084 core_rst
= ResetSignal("coresync")
1085 comb
+= ti_rst
.eq(delay
!= 0 | dbg
.core_rst_o |
ResetSignal())
1086 comb
+= core_rst
.eq(ti_rst
)
1088 # debug clock is same as coresync, but reset is *main external*
1089 if self
.dbg_domain
!= "sync":
1090 dbg_rst
= ResetSignal(self
.dbg_domain
)
1091 comb
+= dbg_rst
.eq(ResetSignal())
1093 # busy/halted signals from core
1094 core_busy_o
= ~core
.p
.o_ready | core
.n
.o_data
.busy_o
# core is busy
1095 comb
+= self
.busy_o
.eq(core_busy_o
)
1096 comb
+= pdecode2
.dec
.bigendian
.eq(self
.core_bigendian_i
)
1098 # temporary hack: says "go" immediately for both address gen and ST
1100 ldst
= core
.fus
.fus
['ldst0']
1101 st_go_edge
= rising_edge(m
, ldst
.st
.rel_o
)
1102 # link addr-go direct to rel
1103 m
.d
.comb
+= ldst
.ad
.go_i
.eq(ldst
.ad
.rel_o
)
1104 m
.d
.comb
+= ldst
.st
.go_i
.eq(st_go_edge
) # link store-go to rising rel
1106 def elaborate(self
, platform
):
1109 comb
, sync
= m
.d
.comb
, m
.d
.sync
1110 cur_state
= self
.cur_state
1111 pdecode2
= self
.pdecode2
1115 # set up peripherals and core
1116 core_rst
= self
.core_rst
1117 self
.setup_peripherals(m
)
1119 # reset current state if core reset requested
1120 with m
.If(core_rst
):
1121 m
.d
.sync
+= self
.cur_state
.eq(0)
1123 # PC and instruction from I-Memory
1124 comb
+= self
.pc_o
.eq(cur_state
.pc
)
1125 pc_changed
= Signal() # note write to PC
1126 sv_changed
= Signal() # note write to SVSTATE
1128 # indicate to outside world if any FU is still executing
1129 comb
+= self
.any_busy
.eq(core
.n
.o_data
.any_busy_o
) # any FU executing
1131 # read state either from incoming override or from regfile
1132 # TODO: really should be doing MSR in the same way
1133 pc
= state_get(m
, core_rst
, self
.pc_i
,
1135 self
.state_r_pc
, StateRegs
.PC
)
1136 svstate
= state_get(m
, core_rst
, self
.svstate_i
,
1137 "svstate", # read SVSTATE
1138 self
.state_r_sv
, StateRegs
.SVSTATE
)
1140 # don't write pc every cycle
1141 comb
+= self
.state_w_pc
.wen
.eq(0)
1142 comb
+= self
.state_w_pc
.i_data
.eq(0)
1144 # address of the next instruction, in the absence of a branch
1145 # depends on the instruction size
1148 # connect up debug signals
1149 # TODO comb += core.icache_rst_i.eq(dbg.icache_rst_o)
1150 comb
+= dbg
.terminate_i
.eq(core
.o
.core_terminate_o
)
1151 comb
+= dbg
.state
.pc
.eq(pc
)
1152 comb
+= dbg
.state
.svstate
.eq(svstate
)
1153 comb
+= dbg
.state
.msr
.eq(cur_state
.msr
)
1155 # pass the prefix mode from Fetch to Issue, so the latter can loop
1157 is_svp64_mode
= Signal()
1159 # there are *THREE^WFOUR-if-SVP64-enabled* FSMs, fetch (32/64-bit)
1160 # issue, decode/execute, now joined by "Predicate fetch/calculate".
1161 # these are the handshake signals between each
1163 # fetch FSM can run as soon as the PC is valid
1164 fetch_pc_i_valid
= Signal() # Execute tells Fetch "start next read"
1165 fetch_pc_o_ready
= Signal() # Fetch Tells SVSTATE "proceed"
1167 # fetch FSM hands over the instruction to be decoded / issued
1168 fetch_insn_o_valid
= Signal()
1169 fetch_insn_i_ready
= Signal()
1171 # predicate fetch FSM decodes and fetches the predicate
1172 pred_insn_i_valid
= Signal()
1173 pred_insn_o_ready
= Signal()
1175 # predicate fetch FSM delivers the masks
1176 pred_mask_o_valid
= Signal()
1177 pred_mask_i_ready
= Signal()
1179 # issue FSM delivers the instruction to the be executed
1180 exec_insn_i_valid
= Signal()
1181 exec_insn_o_ready
= Signal()
1183 # execute FSM, hands over the PC/SVSTATE back to the issue FSM
1184 exec_pc_o_valid
= Signal()
1185 exec_pc_i_ready
= Signal()
1187 # the FSMs here are perhaps unusual in that they detect conditions
1188 # then "hold" information, combinatorially, for the core
1189 # (as opposed to using sync - which would be on a clock's delay)
1190 # this includes the actual opcode, valid flags and so on.
1192 # Fetch, then predicate fetch, then Issue, then Execute.
1193 # Issue is where the VL for-loop # lives. the ready/valid
1194 # signalling is used to communicate between the four.
1197 fetch
= FetchFSM(self
.allow_overlap
, self
.svp64_en
,
1198 self
.imem
, core_rst
, pdecode2
, cur_state
,
1199 dbg
, core
, svstate
, nia
, is_svp64_mode
)
1200 m
.submodules
.fetch
= fetch
1201 # connect up in/out data to existing Signals
1202 comb
+= fetch
.p
.i_data
.pc
.eq(pc
)
1203 # and the ready/valid signalling
1204 comb
+= fetch_pc_o_ready
.eq(fetch
.p
.o_ready
)
1205 comb
+= fetch
.p
.i_valid
.eq(fetch_pc_i_valid
)
1206 comb
+= fetch_insn_o_valid
.eq(fetch
.n
.o_valid
)
1207 comb
+= fetch
.n
.i_ready
.eq(fetch_insn_i_ready
)
1209 self
.issue_fsm(m
, core
, pc_changed
, sv_changed
, nia
,
1210 dbg
, core_rst
, is_svp64_mode
,
1211 fetch_pc_o_ready
, fetch_pc_i_valid
,
1212 fetch_insn_o_valid
, fetch_insn_i_ready
,
1213 pred_insn_i_valid
, pred_insn_o_ready
,
1214 pred_mask_o_valid
, pred_mask_i_ready
,
1215 exec_insn_i_valid
, exec_insn_o_ready
,
1216 exec_pc_o_valid
, exec_pc_i_ready
)
1219 self
.fetch_predicate_fsm(m
,
1220 pred_insn_i_valid
, pred_insn_o_ready
,
1221 pred_mask_o_valid
, pred_mask_i_ready
)
1223 self
.execute_fsm(m
, core
, pc_changed
, sv_changed
,
1224 exec_insn_i_valid
, exec_insn_o_ready
,
1225 exec_pc_o_valid
, exec_pc_i_ready
)
1227 # this bit doesn't have to be in the FSM: connect up to read
1228 # regfiles on demand from DMI
1231 # DEC and TB inc/dec FSM. copy of DEC is put into CoreState,
1232 # (which uses that in PowerDecoder2 to raise 0x900 exception)
1233 self
.tb_dec_fsm(m
, cur_state
.dec
)
1237 def do_dmi(self
, m
, dbg
):
1238 """deals with DMI debug requests
1240 currently only provides read requests for the INT regfile, CR and XER
1241 it will later also deal with *writing* to these regfiles.
1245 dmi
, d_reg
, d_cr
, d_xer
, = dbg
.dmi
, dbg
.d_gpr
, dbg
.d_cr
, dbg
.d_xer
1246 intrf
= self
.core
.regs
.rf
['int']
1248 with m
.If(d_reg
.req
): # request for regfile access being made
1249 # TODO: error-check this
1250 # XXX should this be combinatorial? sync better?
1252 comb
+= self
.int_r
.ren
.eq(1 << d_reg
.addr
)
1254 comb
+= self
.int_r
.addr
.eq(d_reg
.addr
)
1255 comb
+= self
.int_r
.ren
.eq(1)
1256 d_reg_delay
= Signal()
1257 sync
+= d_reg_delay
.eq(d_reg
.req
)
1258 with m
.If(d_reg_delay
):
1259 # data arrives one clock later
1260 comb
+= d_reg
.data
.eq(self
.int_r
.o_data
)
1261 comb
+= d_reg
.ack
.eq(1)
1263 # sigh same thing for CR debug
1264 with m
.If(d_cr
.req
): # request for regfile access being made
1265 comb
+= self
.cr_r
.ren
.eq(0b11111111) # enable all
1266 d_cr_delay
= Signal()
1267 sync
+= d_cr_delay
.eq(d_cr
.req
)
1268 with m
.If(d_cr_delay
):
1269 # data arrives one clock later
1270 comb
+= d_cr
.data
.eq(self
.cr_r
.o_data
)
1271 comb
+= d_cr
.ack
.eq(1)
1274 with m
.If(d_xer
.req
): # request for regfile access being made
1275 comb
+= self
.xer_r
.ren
.eq(0b111111) # enable all
1276 d_xer_delay
= Signal()
1277 sync
+= d_xer_delay
.eq(d_xer
.req
)
1278 with m
.If(d_xer_delay
):
1279 # data arrives one clock later
1280 comb
+= d_xer
.data
.eq(self
.xer_r
.o_data
)
1281 comb
+= d_xer
.ack
.eq(1)
1283 def tb_dec_fsm(self
, m
, spr_dec
):
1286 this is a FSM for updating either dec or tb. it runs alternately
1287 DEC, TB, DEC, TB. note that SPR pipeline could have written a new
1288 value to DEC, however the regfile has "passthrough" on it so this
1291 see v3.0B p1097-1099 for Timeer Resource and p1065 and p1076
1294 comb
, sync
= m
.d
.comb
, m
.d
.sync
1295 fast_rf
= self
.core
.regs
.rf
['fast']
1296 fast_r_dectb
= fast_rf
.r_ports
['issue'] # DEC/TB
1297 fast_w_dectb
= fast_rf
.w_ports
['issue'] # DEC/TB
1299 with m
.FSM() as fsm
:
1301 # initiates read of current DEC
1302 with m
.State("DEC_READ"):
1303 comb
+= fast_r_dectb
.addr
.eq(FastRegs
.DEC
)
1304 comb
+= fast_r_dectb
.ren
.eq(1)
1305 m
.next
= "DEC_WRITE"
1307 # waits for DEC read to arrive (1 cycle), updates with new value
1308 with m
.State("DEC_WRITE"):
1309 new_dec
= Signal(64)
1310 # TODO: MSR.LPCR 32-bit decrement mode
1311 comb
+= new_dec
.eq(fast_r_dectb
.o_data
- 1)
1312 comb
+= fast_w_dectb
.addr
.eq(FastRegs
.DEC
)
1313 comb
+= fast_w_dectb
.wen
.eq(1)
1314 comb
+= fast_w_dectb
.i_data
.eq(new_dec
)
1315 sync
+= spr_dec
.eq(new_dec
) # copy into cur_state for decoder
1318 # initiates read of current TB
1319 with m
.State("TB_READ"):
1320 comb
+= fast_r_dectb
.addr
.eq(FastRegs
.TB
)
1321 comb
+= fast_r_dectb
.ren
.eq(1)
1324 # waits for read TB to arrive, initiates write of current TB
1325 with m
.State("TB_WRITE"):
1327 comb
+= new_tb
.eq(fast_r_dectb
.o_data
+ 1)
1328 comb
+= fast_w_dectb
.addr
.eq(FastRegs
.TB
)
1329 comb
+= fast_w_dectb
.wen
.eq(1)
1330 comb
+= fast_w_dectb
.i_data
.eq(new_tb
)
1336 yield from self
.pc_i
.ports()
1339 yield from self
.core
.ports()
1340 yield from self
.imem
.ports()
1341 yield self
.core_bigendian_i
1347 def external_ports(self
):
1348 ports
= self
.pc_i
.ports()
1349 ports
+= [self
.pc_o
, self
.memerr_o
, self
.core_bigendian_i
, self
.busy_o
,
1353 ports
+= list(self
.jtag
.external_ports())
1355 # don't add DMI if JTAG is enabled
1356 ports
+= list(self
.dbg
.dmi
.ports())
1358 ports
+= list(self
.imem
.ibus
.fields
.values())
1359 ports
+= list(self
.core
.l0
.cmpi
.wb_bus().fields
.values())
1362 for sram
in self
.sram4k
:
1363 ports
+= list(sram
.bus
.fields
.values())
1366 ports
+= list(self
.xics_icp
.bus
.fields
.values())
1367 ports
+= list(self
.xics_ics
.bus
.fields
.values())
1368 ports
.append(self
.int_level_i
)
1371 ports
+= list(self
.simple_gpio
.bus
.fields
.values())
1372 ports
.append(self
.gpio_o
)
1380 class TestIssuer(Elaboratable
):
1381 def __init__(self
, pspec
):
1382 self
.ti
= TestIssuerInternal(pspec
)
1383 self
.pll
= DummyPLL(instance
=True)
1385 # PLL direct clock or not
1386 self
.pll_en
= hasattr(pspec
, "use_pll") and pspec
.use_pll
1388 self
.pll_test_o
= Signal(reset_less
=True)
1389 self
.pll_vco_o
= Signal(reset_less
=True)
1390 self
.clk_sel_i
= Signal(2, reset_less
=True)
1391 self
.ref_clk
= ClockSignal() # can't rename it but that's ok
1392 self
.pllclk_clk
= ClockSignal("pllclk")
1394 def elaborate(self
, platform
):
1398 # TestIssuer nominally runs at main clock, actually it is
1399 # all combinatorial internally except for coresync'd components
1400 m
.submodules
.ti
= ti
= self
.ti
1403 # ClockSelect runs at PLL output internal clock rate
1404 m
.submodules
.wrappll
= pll
= self
.pll
1406 # add clock domains from PLL
1407 cd_pll
= ClockDomain("pllclk")
1410 # PLL clock established. has the side-effect of running clklsel
1411 # at the PLL's speed (see DomainRenamer("pllclk") above)
1412 pllclk
= self
.pllclk_clk
1413 comb
+= pllclk
.eq(pll
.clk_pll_o
)
1415 # wire up external 24mhz to PLL
1416 #comb += pll.clk_24_i.eq(self.ref_clk)
1417 # output 18 mhz PLL test signal, and analog oscillator out
1418 comb
+= self
.pll_test_o
.eq(pll
.pll_test_o
)
1419 comb
+= self
.pll_vco_o
.eq(pll
.pll_vco_o
)
1421 # input to pll clock selection
1422 comb
+= pll
.clk_sel_i
.eq(self
.clk_sel_i
)
1424 # now wire up ResetSignals. don't mind them being in this domain
1425 pll_rst
= ResetSignal("pllclk")
1426 comb
+= pll_rst
.eq(ResetSignal())
1428 # internal clock is set to selector clock-out. has the side-effect of
1429 # running TestIssuer at this speed (see DomainRenamer("intclk") above)
1430 # debug clock runs at coresync internal clock
1431 cd_coresync
= ClockDomain("coresync")
1432 #m.domains += cd_coresync
1433 if self
.ti
.dbg_domain
!= 'sync':
1434 cd_dbgsync
= ClockDomain("dbgsync")
1435 #m.domains += cd_dbgsync
1436 intclk
= ClockSignal("coresync")
1437 dbgclk
= ClockSignal(self
.ti
.dbg_domain
)
1438 # XXX BYPASS PLL XXX
1439 # XXX BYPASS PLL XXX
1440 # XXX BYPASS PLL XXX
1442 comb
+= intclk
.eq(self
.ref_clk
)
1444 comb
+= intclk
.eq(ClockSignal())
1445 if self
.ti
.dbg_domain
!= 'sync':
1446 dbgclk
= ClockSignal(self
.ti
.dbg_domain
)
1447 comb
+= dbgclk
.eq(intclk
)
1452 return list(self
.ti
.ports()) + list(self
.pll
.ports()) + \
1453 [ClockSignal(), ResetSignal()]
1455 def external_ports(self
):
1456 ports
= self
.ti
.external_ports()
1457 ports
.append(ClockSignal())
1458 ports
.append(ResetSignal())
1460 ports
.append(self
.clk_sel_i
)
1461 ports
.append(self
.pll
.clk_24_i
)
1462 ports
.append(self
.pll_test_o
)
1463 ports
.append(self
.pll_vco_o
)
1464 ports
.append(self
.pllclk_clk
)
1465 ports
.append(self
.ref_clk
)
1469 if __name__
== '__main__':
1470 units
= {'alu': 1, 'cr': 1, 'branch': 1, 'trap': 1, 'logical': 1,
1476 pspec
= TestMemPspec(ldst_ifacetype
='bare_wb',
1477 imem_ifacetype
='bare_wb',
1482 dut
= TestIssuer(pspec
)
1483 vl
= main(dut
, ports
=dut
.ports(), name
="test_issuer")
1485 if len(sys
.argv
) == 1:
1486 vl
= rtlil
.convert(dut
, ports
=dut
.external_ports(), name
="test_issuer")
1487 with
open("test_issuer.il", "w") as f
: