3 not in any way intended for production use. this runs a FSM that:
5 * reads the Program Counter from StateRegs
6 * reads an instruction from a fixed-size Test Memory
7 * issues it to the Simple Core
8 * waits for it to complete
10 * does it all over again
12 the purpose of this module is to verify the functional correctness
13 of the Function Units in the absolute simplest and clearest possible
14 way, and to at provide something that can be further incrementally
18 from nmigen
import (Elaboratable
, Module
, Signal
, ClockSignal
, ResetSignal
,
19 ClockDomain
, DomainRenamer
, Mux
, Const
, Repl
, Cat
)
20 from nmigen
.cli
import rtlil
21 from nmigen
.cli
import main
24 from nmutil
.singlepipe
import ControlBase
25 from soc
.simple
.core_data
import FetchOutput
, FetchInput
27 from nmigen
.lib
.coding
import PriorityEncoder
29 from openpower
.decoder
.power_decoder
import create_pdecode
30 from openpower
.decoder
.power_decoder2
import PowerDecode2
, SVP64PrefixDecoder
31 from openpower
.decoder
.decode2execute1
import IssuerDecode2ToOperand
32 from openpower
.decoder
.decode2execute1
import Data
33 from openpower
.decoder
.power_enums
import (MicrOp
, SVP64PredInt
, SVP64PredCR
,
35 from openpower
.state
import CoreState
36 from openpower
.consts
import (CR
, SVP64CROffs
, MSR
)
37 from soc
.experiment
.testmem
import TestMemory
# test only for instructions
38 from soc
.regfile
.regfiles
import StateRegs
, FastRegs
39 from soc
.simple
.core
import NonProductionCore
40 from soc
.config
.test
.test_loadstore
import TestMemPspec
41 from soc
.config
.ifetch
import ConfigFetchUnit
42 from soc
.debug
.dmi
import CoreDebug
, DMIInterface
43 from soc
.debug
.jtag
import JTAG
44 from soc
.config
.pinouts
import get_pinspecs
45 from soc
.interrupts
.xics
import XICS_ICP
, XICS_ICS
46 from soc
.bus
.simple_gpio
import SimpleGPIO
47 from soc
.bus
.SPBlock512W64B8W
import SPBlock512W64B8W
48 from soc
.clock
.select
import ClockSelect
49 from soc
.clock
.dummypll
import DummyPLL
50 from openpower
.sv
.svstate
import SVSTATERec
51 from soc
.experiment
.icache
import ICache
53 from nmutil
.util
import rising_edge
56 def get_insn(f_instr_o
, pc
):
57 if f_instr_o
.width
== 32:
60 # 64-bit: bit 2 of pc decides which word to select
61 return f_instr_o
.word_select(pc
[2], 32)
63 # gets state input or reads from state regfile
66 def state_get(m
, res
, core_rst
, state_i
, name
, regfile
, regnum
):
69 # read the {insert state variable here}
70 res_ok_delay
= Signal(name
="%s_ok_delay" % name
)
72 sync
+= res_ok_delay
.eq(~state_i
.ok
)
73 with m
.If(state_i
.ok
):
74 # incoming override (start from pc_i)
75 comb
+= res
.eq(state_i
.data
)
77 # otherwise read StateRegs regfile for {insert state here}...
78 comb
+= regfile
.ren
.eq(1 << regnum
)
79 # ... but on a 1-clock delay
80 with m
.If(res_ok_delay
):
81 comb
+= res
.eq(regfile
.o_data
)
84 def get_predint(m
, mask
, name
):
85 """decode SVP64 predicate integer mask field to reg number and invert
86 this is identical to the equivalent function in ISACaller except that
87 it doesn't read the INT directly, it just decodes "what needs to be done"
88 i.e. which INT reg, whether it is shifted and whether it is bit-inverted.
90 * all1s is set to indicate that no mask is to be applied.
91 * regread indicates the GPR register number to be read
92 * invert is set to indicate that the register value is to be inverted
93 * unary indicates that the contents of the register is to be shifted 1<<r3
96 regread
= Signal(5, name
=name
+"regread")
97 invert
= Signal(name
=name
+"invert")
98 unary
= Signal(name
=name
+"unary")
99 all1s
= Signal(name
=name
+"all1s")
101 with m
.Case(SVP64PredInt
.ALWAYS
.value
):
102 comb
+= all1s
.eq(1) # use 0b1111 (all ones)
103 with m
.Case(SVP64PredInt
.R3_UNARY
.value
):
104 comb
+= regread
.eq(3)
105 comb
+= unary
.eq(1) # 1<<r3 - shift r3 (single bit)
106 with m
.Case(SVP64PredInt
.R3
.value
):
107 comb
+= regread
.eq(3)
108 with m
.Case(SVP64PredInt
.R3_N
.value
):
109 comb
+= regread
.eq(3)
111 with m
.Case(SVP64PredInt
.R10
.value
):
112 comb
+= regread
.eq(10)
113 with m
.Case(SVP64PredInt
.R10_N
.value
):
114 comb
+= regread
.eq(10)
116 with m
.Case(SVP64PredInt
.R30
.value
):
117 comb
+= regread
.eq(30)
118 with m
.Case(SVP64PredInt
.R30_N
.value
):
119 comb
+= regread
.eq(30)
121 return regread
, invert
, unary
, all1s
124 def get_predcr(m
, mask
, name
):
125 """decode SVP64 predicate CR to reg number field and invert status
126 this is identical to _get_predcr in ISACaller
129 idx
= Signal(2, name
=name
+"idx")
130 invert
= Signal(name
=name
+"crinvert")
132 with m
.Case(SVP64PredCR
.LT
.value
):
133 comb
+= idx
.eq(CR
.LT
)
135 with m
.Case(SVP64PredCR
.GE
.value
):
136 comb
+= idx
.eq(CR
.LT
)
138 with m
.Case(SVP64PredCR
.GT
.value
):
139 comb
+= idx
.eq(CR
.GT
)
141 with m
.Case(SVP64PredCR
.LE
.value
):
142 comb
+= idx
.eq(CR
.GT
)
144 with m
.Case(SVP64PredCR
.EQ
.value
):
145 comb
+= idx
.eq(CR
.EQ
)
147 with m
.Case(SVP64PredCR
.NE
.value
):
148 comb
+= idx
.eq(CR
.EQ
)
150 with m
.Case(SVP64PredCR
.SO
.value
):
151 comb
+= idx
.eq(CR
.SO
)
153 with m
.Case(SVP64PredCR
.NS
.value
):
154 comb
+= idx
.eq(CR
.SO
)
159 class TestIssuerBase(Elaboratable
):
160 """TestIssuerBase - common base class for Issuers
162 takes care of power-on reset, peripherals, debug, DEC/TB,
163 and gets PC/MSR/SVSTATE from the State Regfile etc.
166 def __init__(self
, pspec
):
168 # test if microwatt compatibility is to be enabled
169 self
.microwatt_compat
= (hasattr(pspec
, "microwatt_compat") and
170 (pspec
.microwatt_compat
== True))
171 self
.alt_reset
= Signal(reset_less
=True) # not connected yet (microwatt)
173 if self
.microwatt_compat
:
175 if hasattr(pspec
, "microwatt_old"):
176 self
.microwatt_old
= pspec
.microwatt_old
178 self
.microwatt_old
= True # PLEASE DO NOT ALTER THIS
180 if hasattr(pspec
, "microwatt_debug"):
181 self
.microwatt_debug
= pspec
.microwatt_debug
183 self
.microwatt_debug
= True # set to False when using an FPGA
185 # test is SVP64 is to be enabled
186 self
.svp64_en
= hasattr(pspec
, "svp64") and (pspec
.svp64
== True)
188 # and if regfiles are reduced
189 self
.regreduce_en
= (hasattr(pspec
, "regreduce") and
190 (pspec
.regreduce
== True))
192 # and if overlap requested
193 self
.allow_overlap
= (hasattr(pspec
, "allow_overlap") and
194 (pspec
.allow_overlap
== True))
196 # and get the core domain
197 self
.core_domain
= "coresync"
198 if (hasattr(pspec
, "core_domain") and
199 isinstance(pspec
.core_domain
, str)):
200 self
.core_domain
= pspec
.core_domain
202 # JTAG interface. add this right at the start because if it's
203 # added it *modifies* the pspec, by adding enable/disable signals
204 # for parts of the rest of the core
205 self
.jtag_en
= hasattr(pspec
, "debug") and pspec
.debug
== 'jtag'
206 #self.dbg_domain = "sync" # sigh "dbgsunc" too problematic
207 self
.dbg_domain
= "dbgsync" # domain for DMI/JTAG clock
209 # XXX MUST keep this up-to-date with litex, and
210 # soc-cocotb-sim, and err.. all needs sorting out, argh
213 'eint', 'gpio', 'mspi0',
214 # 'mspi1', - disabled for now
215 # 'pwm', 'sd0', - disabled for now
217 self
.jtag
= JTAG(get_pinspecs(subset
=subset
),
218 domain
=self
.dbg_domain
)
219 # add signals to pspec to enable/disable icache and dcache
220 # (or data and intstruction wishbone if icache/dcache not included)
221 # https://bugs.libre-soc.org/show_bug.cgi?id=520
222 # TODO: do we actually care if these are not domain-synchronised?
223 # honestly probably not.
224 pspec
.wb_icache_en
= self
.jtag
.wb_icache_en
225 pspec
.wb_dcache_en
= self
.jtag
.wb_dcache_en
226 self
.wb_sram_en
= self
.jtag
.wb_sram_en
228 self
.wb_sram_en
= Const(1)
230 # add 4k sram blocks?
231 self
.sram4x4k
= (hasattr(pspec
, "sram4x4kblock") and
232 pspec
.sram4x4kblock
== True)
236 self
.sram4k
.append(SPBlock512W64B8W(name
="sram4k_%d" % i
,
240 # add interrupt controller?
241 self
.xics
= hasattr(pspec
, "xics") and pspec
.xics
== True
243 self
.xics_icp
= XICS_ICP()
244 self
.xics_ics
= XICS_ICS()
245 self
.int_level_i
= self
.xics_ics
.int_level_i
247 self
.ext_irq
= Signal()
249 # add GPIO peripheral?
250 self
.gpio
= hasattr(pspec
, "gpio") and pspec
.gpio
== True
252 self
.simple_gpio
= SimpleGPIO()
253 self
.gpio_o
= self
.simple_gpio
.gpio_o
255 # main instruction core. suitable for prototyping / demo only
256 self
.core
= core
= NonProductionCore(pspec
)
257 self
.core_rst
= ResetSignal(self
.core_domain
)
259 # instruction decoder. goes into Trap Record
260 #pdecode = create_pdecode()
261 self
.cur_state
= CoreState("cur") # current state (MSR/PC/SVSTATE)
262 self
.pdecode2
= PowerDecode2(None, state
=self
.cur_state
,
263 opkls
=IssuerDecode2ToOperand
,
264 svp64_en
=self
.svp64_en
,
265 regreduce_en
=self
.regreduce_en
)
266 pdecode
= self
.pdecode2
.dec
269 self
.svp64
= SVP64PrefixDecoder() # for decoding SVP64 prefix
271 self
.update_svstate
= Signal() # set this if updating svstate
272 self
.new_svstate
= new_svstate
= SVSTATERec("new_svstate")
274 # Test Instruction memory
275 if hasattr(core
, "icache"):
276 # XXX BLECH! use pspec to transfer the I-Cache to ConfigFetchUnit
277 # truly dreadful. needs a huge reorg.
278 pspec
.icache
= core
.icache
279 self
.imem
= ConfigFetchUnit(pspec
).fu
282 self
.dbg
= CoreDebug()
283 self
.dbg_rst_i
= Signal(reset_less
=True)
285 # instruction go/monitor
286 self
.pc_o
= Signal(64, reset_less
=True)
287 self
.pc_i
= Data(64, "pc_i") # set "ok" to indicate "please change me"
288 self
.msr_i
= Data(64, "msr_i") # set "ok" to indicate "please change me"
289 self
.svstate_i
= Data(64, "svstate_i") # ditto
290 self
.core_bigendian_i
= Signal() # TODO: set based on MSR.LE
291 self
.busy_o
= Signal(reset_less
=True)
292 self
.memerr_o
= Signal(reset_less
=True)
294 # STATE regfile read /write ports for PC, MSR, SVSTATE
295 staterf
= self
.core
.regs
.rf
['state']
296 self
.state_r_msr
= staterf
.r_ports
['msr'] # MSR rd
297 self
.state_r_pc
= staterf
.r_ports
['cia'] # PC rd
298 self
.state_r_sv
= staterf
.r_ports
['sv'] # SVSTATE rd
300 self
.state_w_msr
= staterf
.w_ports
['d_wr2'] # MSR wr
301 self
.state_w_pc
= staterf
.w_ports
['d_wr1'] # PC wr
302 self
.state_w_sv
= staterf
.w_ports
['sv'] # SVSTATE wr
304 # DMI interface access
305 intrf
= self
.core
.regs
.rf
['int']
306 fastrf
= self
.core
.regs
.rf
['fast']
307 crrf
= self
.core
.regs
.rf
['cr']
308 xerrf
= self
.core
.regs
.rf
['xer']
309 self
.int_r
= intrf
.r_ports
['dmi'] # INT DMI read
310 self
.cr_r
= crrf
.r_ports
['full_cr_dbg'] # CR DMI read
311 self
.xer_r
= xerrf
.r_ports
['full_xer'] # XER DMI read
312 self
.fast_r
= fastrf
.r_ports
['dmi'] # FAST DMI read
316 self
.int_pred
= intrf
.r_ports
['pred'] # INT predicate read
317 self
.cr_pred
= crrf
.r_ports
['cr_pred'] # CR predicate read
319 # hack method of keeping an eye on whether branch/trap set the PC
320 self
.state_nia
= self
.core
.regs
.rf
['state'].w_ports
['nia']
321 self
.state_nia
.wen
.name
= 'state_nia_wen'
322 # and whether SPR pipeline sets DEC or TB (fu/spr/main_stage.py)
323 self
.state_spr
= self
.core
.regs
.rf
['state'].w_ports
['state1']
325 # pulse to synchronize the simulator at instruction end
326 self
.insn_done
= Signal()
328 # indicate any instruction still outstanding, in execution
329 self
.any_busy
= Signal()
332 # store copies of predicate masks
333 self
.srcmask
= Signal(64)
334 self
.dstmask
= Signal(64)
336 # sigh, the wishbone addresses are not wishbone-compliant
337 # in old versions of microwatt, tplaten_3d_game is a new one
338 if self
.microwatt_compat
:
339 self
.ibus_adr
= Signal(32, name
='wishbone_insn_out.adr')
340 self
.dbus_adr
= Signal(32, name
='wishbone_data_out.adr')
342 # add an output of the PC and instruction, and whether it was requested
343 # this is for verilator debug purposes
344 if self
.microwatt_compat
:
345 self
.nia
= Signal(64)
346 self
.msr_o
= Signal(64)
347 self
.nia_req
= Signal(1)
348 self
.insn
= Signal(32)
349 self
.ldst_req
= Signal(1)
350 self
.ldst_addr
= Signal(1)
352 # for pausing dec/tb during an SPR pipeline event, this
353 # ensures that an SPR write (mtspr) to TB or DEC does not
354 # get overwritten by the DEC/TB FSM
355 self
.pause_dec_tb
= Signal()
357 def setup_peripherals(self
, m
):
358 comb
, sync
= m
.d
.comb
, m
.d
.sync
360 # okaaaay so the debug module must be in coresync clock domain
361 # but NOT its reset signal. to cope with this, set every single
362 # submodule explicitly in coresync domain, debug and JTAG
363 # in their own one but using *external* reset.
364 csd
= DomainRenamer(self
.core_domain
)
365 dbd
= DomainRenamer(self
.dbg_domain
)
367 if self
.microwatt_compat
:
368 m
.submodules
.core
= core
= self
.core
370 m
.submodules
.core
= core
= csd(self
.core
)
372 # this _so_ needs sorting out. ICache is added down inside
373 # LoadStore1 and is already a submodule of LoadStore1
374 if not isinstance(self
.imem
, ICache
):
375 m
.submodules
.imem
= imem
= csd(self
.imem
)
377 # set up JTAG Debug Module (in correct domain)
378 m
.submodules
.dbg
= dbg
= dbd(self
.dbg
)
380 m
.submodules
.jtag
= jtag
= dbd(self
.jtag
)
381 # TODO: UART2GDB mux, here, from external pin
382 # see https://bugs.libre-soc.org/show_bug.cgi?id=499
383 sync
+= dbg
.dmi
.connect_to(jtag
.dmi
)
385 # fixup the clocks in microwatt-compat mode (but leave resets alone
386 # so that microwatt soc.vhdl can pull a reset on the core or DMI
387 # can do it, just like in TestIssuer)
388 if self
.microwatt_compat
:
389 intclk
= ClockSignal(self
.core_domain
)
390 dbgclk
= ClockSignal(self
.dbg_domain
)
391 if self
.core_domain
!= 'sync':
392 comb
+= intclk
.eq(ClockSignal())
393 if self
.dbg_domain
!= 'sync':
394 comb
+= dbgclk
.eq(ClockSignal())
396 # if using old version of microwatt
397 # drop the first 3 bits of the incoming wishbone addresses
398 if self
.microwatt_compat
:
399 ibus
= self
.imem
.ibus
400 dbus
= self
.core
.l0
.cmpi
.wb_bus()
401 if self
.microwatt_old
:
402 comb
+= self
.ibus_adr
.eq(Cat(Const(0, 3), ibus
.adr
))
403 comb
+= self
.dbus_adr
.eq(Cat(Const(0, 3), dbus
.adr
))
405 comb
+= self
.ibus_adr
.eq(ibus
.adr
)
406 comb
+= self
.dbus_adr
.eq(dbus
.adr
)
407 if self
.microwatt_debug
:
408 # microwatt verilator debug purposes
409 pi
= self
.core
.l0
.cmpi
.pi
.pi
410 comb
+= self
.ldst_req
.eq(pi
.addr_ok_o
)
411 comb
+= self
.ldst_addr
.eq(pi
.addr
)
413 cur_state
= self
.cur_state
415 # 4x 4k SRAM blocks. these simply "exist", they get routed in litex
417 for i
, sram
in enumerate(self
.sram4k
):
418 m
.submodules
["sram4k_%d" % i
] = csd(sram
)
419 comb
+= sram
.enable
.eq(self
.wb_sram_en
)
421 # XICS interrupt handler
423 m
.submodules
.xics_icp
= icp
= csd(self
.xics_icp
)
424 m
.submodules
.xics_ics
= ics
= csd(self
.xics_ics
)
425 comb
+= icp
.ics_i
.eq(ics
.icp_o
) # connect ICS to ICP
426 sync
+= cur_state
.eint
.eq(icp
.core_irq_o
) # connect ICP to core
428 sync
+= cur_state
.eint
.eq(self
.ext_irq
) # connect externally
430 # GPIO test peripheral
432 m
.submodules
.simple_gpio
= simple_gpio
= csd(self
.simple_gpio
)
434 # connect one GPIO output to ICS bit 15 (like in microwatt soc.vhdl)
435 # XXX causes litex ECP5 test to get wrong idea about input and output
436 # (but works with verilator sim *sigh*)
437 # if self.gpio and self.xics:
438 # comb += self.int_level_i[15].eq(simple_gpio.gpio_o[0])
440 # instruction decoder
441 pdecode
= create_pdecode()
442 m
.submodules
.dec2
= pdecode2
= csd(self
.pdecode2
)
444 m
.submodules
.svp64
= svp64
= csd(self
.svp64
)
446 # clock delay power-on reset
447 cd_por
= ClockDomain(reset_less
=True)
448 cd_sync
= ClockDomain()
449 m
.domains
+= cd_por
, cd_sync
450 core_sync
= ClockDomain(self
.core_domain
)
451 if self
.core_domain
!= "sync":
452 m
.domains
+= core_sync
453 if self
.dbg_domain
!= "sync":
454 dbg_sync
= ClockDomain(self
.dbg_domain
)
455 m
.domains
+= dbg_sync
457 # create a delay, but remember it is in the power-on-reset clock domain!
458 ti_rst
= Signal(reset_less
=True)
459 delay
= Signal(range(4), reset
=3)
460 stop_delay
= Signal(range(16), reset
=5)
461 with m
.If(delay
!= 0):
462 m
.d
.por
+= delay
.eq(delay
- 1) # decrement... in POR domain!
463 with m
.If(stop_delay
!= 0):
464 m
.d
.por
+= stop_delay
.eq(stop_delay
- 1) # likewise
465 comb
+= cd_por
.clk
.eq(ClockSignal())
467 # power-on reset delay
468 core_rst
= ResetSignal(self
.core_domain
)
469 if self
.core_domain
!= "sync":
470 comb
+= ti_rst
.eq(delay
!= 0 | dbg
.core_rst_o |
ResetSignal())
471 comb
+= core_rst
.eq(ti_rst
)
473 with m
.If(delay
!= 0 | dbg
.core_rst_o
):
474 comb
+= core_rst
.eq(1)
475 with m
.If(stop_delay
!= 0):
476 # run DMI core-stop as well but on an extra couple of cycles
477 comb
+= dbg
.core_stopped_i
.eq(1)
479 # connect external reset signal to DMI Reset
480 if self
.dbg_domain
!= "sync":
481 dbg_rst
= ResetSignal(self
.dbg_domain
)
482 comb
+= dbg_rst
.eq(self
.dbg_rst_i
)
484 # busy/halted signals from core
485 core_busy_o
= ~core
.p
.o_ready | core
.n
.o_data
.busy_o
# core is busy
486 comb
+= self
.busy_o
.eq(core_busy_o
)
487 comb
+= pdecode2
.dec
.bigendian
.eq(self
.core_bigendian_i
)
489 # temporary hack: says "go" immediately for both address gen and ST
490 # XXX: st.go_i is set to 1 cycle delay to reduce combinatorial chains
492 ldst
= core
.fus
.fus
['ldst0']
493 st_go_edge
= rising_edge(m
, ldst
.st
.rel_o
)
494 # link addr-go direct to rel
495 m
.d
.comb
+= ldst
.ad
.go_i
.eq(ldst
.ad
.rel_o
)
496 m
.d
.sync
+= ldst
.st
.go_i
.eq(st_go_edge
) # link store-go to rising rel
498 def do_dmi(self
, m
, dbg
):
499 """deals with DMI debug requests
501 currently only provides read requests for the INT regfile, CR and XER
502 it will later also deal with *writing* to these regfiles.
506 dmi
, d_reg
, d_cr
, d_xer
, = dbg
.dmi
, dbg
.d_gpr
, dbg
.d_cr
, dbg
.d_xer
508 intrf
= self
.core
.regs
.rf
['int']
509 fastrf
= self
.core
.regs
.rf
['fast']
511 with m
.If(d_reg
.req
): # request for regfile access being made
512 # TODO: error-check this
513 # XXX should this be combinatorial? sync better?
515 comb
+= self
.int_r
.ren
.eq(1 << d_reg
.addr
)
517 comb
+= self
.int_r
.addr
.eq(d_reg
.addr
)
518 comb
+= self
.int_r
.ren
.eq(1)
519 d_reg_delay
= Signal()
520 sync
+= d_reg_delay
.eq(d_reg
.req
)
521 with m
.If(d_reg_delay
):
522 # data arrives one clock later
523 comb
+= d_reg
.data
.eq(self
.int_r
.o_data
)
524 comb
+= d_reg
.ack
.eq(1)
527 with m
.If(d_fast
.req
): # request for regfile access being made
529 comb
+= self
.fast_r
.ren
.eq(1 << d_fast
.addr
)
531 comb
+= self
.fast_r
.addr
.eq(d_fast
.addr
)
532 comb
+= self
.fast_r
.ren
.eq(1)
533 d_fast_delay
= Signal()
534 sync
+= d_fast_delay
.eq(d_fast
.req
)
535 with m
.If(d_fast_delay
):
536 # data arrives one clock later
537 comb
+= d_fast
.data
.eq(self
.fast_r
.o_data
)
538 comb
+= d_fast
.ack
.eq(1)
540 # sigh same thing for CR debug
541 with m
.If(d_cr
.req
): # request for regfile access being made
542 comb
+= self
.cr_r
.ren
.eq(0b11111111) # enable all
543 d_cr_delay
= Signal()
544 sync
+= d_cr_delay
.eq(d_cr
.req
)
545 with m
.If(d_cr_delay
):
546 # data arrives one clock later
547 comb
+= d_cr
.data
.eq(self
.cr_r
.o_data
)
548 comb
+= d_cr
.ack
.eq(1)
551 with m
.If(d_xer
.req
): # request for regfile access being made
552 comb
+= self
.xer_r
.ren
.eq(0b111111) # enable all
553 d_xer_delay
= Signal()
554 sync
+= d_xer_delay
.eq(d_xer
.req
)
555 with m
.If(d_xer_delay
):
556 # data arrives one clock later
557 comb
+= d_xer
.data
.eq(self
.xer_r
.o_data
)
558 comb
+= d_xer
.ack
.eq(1)
560 def tb_dec_fsm(self
, m
, spr_dec
):
563 this is a FSM for updating either dec or tb. it runs alternately
564 DEC, TB, DEC, TB. note that SPR pipeline could have written a new
565 value to DEC, however the regfile has "passthrough" on it so this
568 see v3.0B p1097-1099 for Timer Resource and p1065 and p1076
571 comb
, sync
= m
.d
.comb
, m
.d
.sync
572 state_rf
= self
.core
.regs
.rf
['state']
573 state_r_dectb
= state_rf
.r_ports
['issue'] # DEC/TB
574 state_w_dectb
= state_rf
.w_ports
['issue'] # DEC/TB
579 # initiates read of current DEC
580 with m
.State("DEC_READ"):
581 comb
+= state_r_dectb
.ren
.eq(1<<StateRegs
.DEC
)
582 with m
.If(~self
.pause_dec_tb
):
585 # waits for DEC read to arrive (1 cycle), updates with new value
586 # respects if dec/tb writing has been paused
587 with m
.State("DEC_WRITE"):
588 with m
.If(self
.pause_dec_tb
):
589 # if paused, return to reading
593 # TODO: MSR.LPCR 32-bit decrement mode
594 comb
+= new_dec
.eq(state_r_dectb
.o_data
- 1)
595 comb
+= state_w_dectb
.wen
.eq(1<<StateRegs
.DEC
)
596 comb
+= state_w_dectb
.i_data
.eq(new_dec
)
597 # copy to cur_state for decoder, for an interrupt
598 sync
+= spr_dec
.eq(new_dec
)
601 # initiates read of current TB
602 with m
.State("TB_READ"):
603 comb
+= state_r_dectb
.ren
.eq(1<<StateRegs
.TB
)
604 with m
.If(~self
.pause_dec_tb
):
607 # waits for read TB to arrive, initiates write of current TB
608 # respects if dec/tb writing has been paused
609 with m
.State("TB_WRITE"):
610 with m
.If(self
.pause_dec_tb
):
611 # if paused, return to reading
615 comb
+= new_tb
.eq(state_r_dectb
.o_data
+ 1)
616 comb
+= state_w_dectb
.wen
.eq(1<<StateRegs
.TB
)
617 comb
+= state_w_dectb
.i_data
.eq(new_tb
)
622 def elaborate(self
, platform
):
625 comb
, sync
= m
.d
.comb
, m
.d
.sync
626 cur_state
= self
.cur_state
627 pdecode2
= self
.pdecode2
630 # set up peripherals and core
631 core_rst
= self
.core_rst
632 self
.setup_peripherals(m
)
634 # reset current state if core reset requested
636 m
.d
.sync
+= self
.cur_state
.eq(0)
637 # and, sigh, set configured values, which are also done in regfile
638 # XXX ??? what the hell is the shift for??
639 m
.d
.sync
+= self
.cur_state
.pc
.eq(self
.core
.pc_at_reset
)
640 m
.d
.sync
+= self
.cur_state
.msr
.eq(self
.core
.msr_at_reset
)
642 # check halted condition: requested PC to execute matches DMI stop addr
643 # and immediately stop. address of 0xffff_ffff_ffff_ffff can never
646 comb
+= halted
.eq(dbg
.stop_addr_o
== dbg
.state
.pc
)
648 comb
+= dbg
.core_stopped_i
.eq(1)
649 comb
+= dbg
.terminate_i
.eq(1)
651 # PC and instruction from I-Memory
652 comb
+= self
.pc_o
.eq(cur_state
.pc
)
653 self
.pc_changed
= Signal() # note write to PC
654 self
.msr_changed
= Signal() # note write to MSR
655 self
.sv_changed
= Signal() # note write to SVSTATE
657 # read state either from incoming override or from regfile
658 state
= CoreState("get") # current state (MSR/PC/SVSTATE)
659 state_get(m
, state
.msr
, core_rst
, self
.msr_i
,
661 self
.state_r_msr
, StateRegs
.MSR
)
662 state_get(m
, state
.pc
, core_rst
, self
.pc_i
,
664 self
.state_r_pc
, StateRegs
.PC
)
665 state_get(m
, state
.svstate
, core_rst
, self
.svstate_i
,
666 "svstate", # read SVSTATE
667 self
.state_r_sv
, StateRegs
.SVSTATE
)
669 # don't write pc every cycle
670 comb
+= self
.state_w_pc
.wen
.eq(0)
671 comb
+= self
.state_w_pc
.i_data
.eq(0)
673 # connect up debug state. note "combinatorially same" below,
674 # this is a bit naff, passing state over in the dbg class, but
675 # because it is combinatorial it achieves the desired goal
676 comb
+= dbg
.state
.eq(state
)
678 # this bit doesn't have to be in the FSM: connect up to read
679 # regfiles on demand from DMI
682 # DEC and TB inc/dec FSM. copy of DEC is put into CoreState,
683 # (which uses that in PowerDecoder2 to raise 0x900 exception)
684 self
.tb_dec_fsm(m
, cur_state
.dec
)
686 # while stopped, allow updating the MSR, PC and SVSTATE.
687 # these are mainly for debugging purposes (including DMI/JTAG)
688 with m
.If(dbg
.core_stopped_i
):
689 with m
.If(self
.pc_i
.ok
):
690 comb
+= self
.state_w_pc
.wen
.eq(1 << StateRegs
.PC
)
691 comb
+= self
.state_w_pc
.i_data
.eq(self
.pc_i
.data
)
692 sync
+= self
.pc_changed
.eq(1)
693 with m
.If(self
.msr_i
.ok
):
694 comb
+= self
.state_w_msr
.wen
.eq(1 << StateRegs
.MSR
)
695 comb
+= self
.state_w_msr
.i_data
.eq(self
.msr_i
.data
)
696 sync
+= self
.msr_changed
.eq(1)
697 with m
.If(self
.svstate_i
.ok | self
.update_svstate
):
698 with m
.If(self
.svstate_i
.ok
): # over-ride from external source
699 comb
+= self
.new_svstate
.eq(self
.svstate_i
.data
)
700 comb
+= self
.state_w_sv
.wen
.eq(1 << StateRegs
.SVSTATE
)
701 comb
+= self
.state_w_sv
.i_data
.eq(self
.new_svstate
)
702 sync
+= self
.sv_changed
.eq(1)
704 # start renaming some of the ports to match microwatt
705 if self
.microwatt_compat
:
706 self
.core
.o
.core_terminate_o
.name
= "terminated_out"
707 # names of DMI interface
708 self
.dbg
.dmi
.addr_i
.name
= 'dmi_addr'
709 self
.dbg
.dmi
.din
.name
= 'dmi_din'
710 self
.dbg
.dmi
.dout
.name
= 'dmi_dout'
711 self
.dbg
.dmi
.req_i
.name
= 'dmi_req'
712 self
.dbg
.dmi
.we_i
.name
= 'dmi_wr'
713 self
.dbg
.dmi
.ack_o
.name
= 'dmi_ack'
714 # wishbone instruction bus
715 ibus
= self
.imem
.ibus
716 ibus
.adr
.name
= 'wishbone_insn_out.adr'
717 ibus
.dat_w
.name
= 'wishbone_insn_out.dat'
718 ibus
.sel
.name
= 'wishbone_insn_out.sel'
719 ibus
.cyc
.name
= 'wishbone_insn_out.cyc'
720 ibus
.stb
.name
= 'wishbone_insn_out.stb'
721 ibus
.we
.name
= 'wishbone_insn_out.we'
722 ibus
.dat_r
.name
= 'wishbone_insn_in.dat'
723 ibus
.ack
.name
= 'wishbone_insn_in.ack'
724 ibus
.stall
.name
= 'wishbone_insn_in.stall'
726 dbus
= self
.core
.l0
.cmpi
.wb_bus()
727 dbus
.adr
.name
= 'wishbone_data_out.adr'
728 dbus
.dat_w
.name
= 'wishbone_data_out.dat'
729 dbus
.sel
.name
= 'wishbone_data_out.sel'
730 dbus
.cyc
.name
= 'wishbone_data_out.cyc'
731 dbus
.stb
.name
= 'wishbone_data_out.stb'
732 dbus
.we
.name
= 'wishbone_data_out.we'
733 dbus
.dat_r
.name
= 'wishbone_data_in.dat'
734 dbus
.ack
.name
= 'wishbone_data_in.ack'
735 dbus
.stall
.name
= 'wishbone_data_in.stall'
740 yield from self
.pc_i
.ports()
741 yield from self
.msr_i
.ports()
744 yield from self
.core
.ports()
745 yield from self
.imem
.ports()
746 yield self
.core_bigendian_i
752 def external_ports(self
):
753 if self
.microwatt_compat
:
754 ports
= [self
.core
.o
.core_terminate_o
,
756 self
.alt_reset
, # not connected yet
757 self
.nia
, self
.insn
, self
.nia_req
, self
.msr_o
,
758 self
.ldst_req
, self
.ldst_addr
,
762 ports
+= list(self
.dbg
.dmi
.ports())
763 # for dbus/ibus microwatt, exclude err btw and cti
764 for name
, sig
in self
.imem
.ibus
.fields
.items():
765 if name
not in ['err', 'bte', 'cti', 'adr']:
767 for name
, sig
in self
.core
.l0
.cmpi
.wb_bus().fields
.items():
768 if name
not in ['err', 'bte', 'cti', 'adr']:
770 # microwatt non-compliant with wishbone
771 ports
.append(self
.ibus_adr
)
772 ports
.append(self
.dbus_adr
)
775 ports
= self
.pc_i
.ports()
776 ports
= self
.msr_i
.ports()
777 ports
+= [self
.pc_o
, self
.memerr_o
, self
.core_bigendian_i
, self
.busy_o
,
781 ports
+= list(self
.jtag
.external_ports())
783 # don't add DMI if JTAG is enabled
784 ports
+= list(self
.dbg
.dmi
.ports())
786 ports
+= list(self
.imem
.ibus
.fields
.values())
787 ports
+= list(self
.core
.l0
.cmpi
.wb_bus().fields
.values())
790 for sram
in self
.sram4k
:
791 ports
+= list(sram
.bus
.fields
.values())
794 ports
+= list(self
.xics_icp
.bus
.fields
.values())
795 ports
+= list(self
.xics_ics
.bus
.fields
.values())
796 ports
.append(self
.int_level_i
)
798 ports
.append(self
.ext_irq
)
801 ports
+= list(self
.simple_gpio
.bus
.fields
.values())
802 ports
.append(self
.gpio_o
)
810 class TestIssuerInternal(TestIssuerBase
):
811 """TestIssuer - reads instructions from TestMemory and issues them
813 efficiency and speed is not the main goal here: functional correctness
814 and code clarity is. optimisations (which almost 100% interfere with
815 easy understanding) come later.
818 def fetch_fsm(self
, m
, dbg
, core
, core_rst
, nia
, is_svp64_mode
,
819 fetch_pc_o_ready
, fetch_pc_i_valid
,
820 fetch_insn_o_valid
, fetch_insn_i_ready
):
823 this FSM performs fetch of raw instruction data, partial-decodes
824 it 32-bit at a time to detect SVP64 prefixes, and will optionally
825 read a 2nd 32-bit quantity if that occurs.
829 pdecode2
= self
.pdecode2
830 cur_state
= self
.cur_state
831 dec_opcode_i
= pdecode2
.dec
.raw_opcode_in
# raw opcode
832 pc
, msr
, svstate
= cur_state
.pc
, cur_state
.msr
, cur_state
.svstate
834 # also note instruction fetch failed
835 if hasattr(core
, "icache"):
836 fetch_failed
= core
.icache
.i_out
.fetch_failed
839 fetch_failed
= Const(0, 1)
842 # set priv / virt mode on I-Cache, sigh
843 if isinstance(self
.imem
, ICache
):
844 comb
+= self
.imem
.i_in
.priv_mode
.eq(~msr
[MSR
.PR
])
845 comb
+= self
.imem
.i_in
.virt_mode
.eq(msr
[MSR
.IR
]) # Instr. Redir (VM)
847 with m
.FSM(name
='fetch_fsm'):
849 # allow fetch to not run at startup due to I-Cache reset not
850 # having time to settle. power-on-reset holds dbg.core_stopped_i
851 with m
.State("PRE_IDLE"):
852 with m
.If(~dbg
.core_stopped_i
& ~dbg
.core_stop_o
& ~core_rst
):
856 with m
.State("IDLE"):
857 # fetch allowed if not failed and stopped but not stepping
858 # (see dmi.py for how core_stop_o is generated)
859 with m
.If(~fetch_failed
& ~dbg
.core_stop_o
):
860 comb
+= fetch_pc_o_ready
.eq(1)
861 with m
.If(fetch_pc_i_valid
& ~pdecode2
.instr_fault
863 # instruction allowed to go: start by reading the PC
864 # capture the PC and also drop it into Insn Memory
865 # we have joined a pair of combinatorial memory
866 # lookups together. this is Generally Bad.
867 comb
+= self
.imem
.a_pc_i
.eq(pc
)
868 comb
+= self
.imem
.a_i_valid
.eq(1)
869 comb
+= self
.imem
.f_i_valid
.eq(1)
870 m
.next
= "INSN_READ" # move to "wait for bus" phase
872 # dummy pause to find out why simulation is not keeping up
873 with m
.State("INSN_READ"):
874 # when using "single-step" mode, checking dbg.stopping_o
875 # prevents progress. allow fetch to proceed once started
877 #if self.allow_overlap:
878 # stopping = dbg.stopping_o
880 # stopping: jump back to idle
883 with m
.If(self
.imem
.f_busy_o
&
884 ~pdecode2
.instr_fault
): # zzz...
885 # busy but not fetch failed: stay in wait-read
886 comb
+= self
.imem
.a_pc_i
.eq(pc
)
887 comb
+= self
.imem
.a_i_valid
.eq(1)
888 comb
+= self
.imem
.f_i_valid
.eq(1)
890 # not busy (or fetch failed!): instruction fetched
891 # when fetch failed, the instruction gets ignored
893 if hasattr(core
, "icache"):
894 # blech, icache returns actual instruction
895 insn
= self
.imem
.f_instr_o
897 # but these return raw memory
898 insn
= get_insn(self
.imem
.f_instr_o
, cur_state
.pc
)
901 # decode the SVP64 prefix, if any
902 comb
+= svp64
.raw_opcode_in
.eq(insn
)
903 comb
+= svp64
.bigendian
.eq(self
.core_bigendian_i
)
904 # pass the decoded prefix (if any) to PowerDecoder2
905 sync
+= pdecode2
.sv_rm
.eq(svp64
.svp64_rm
)
906 sync
+= pdecode2
.is_svp64_mode
.eq(is_svp64_mode
)
907 # remember whether this is a prefixed instruction,
908 # so the FSM can readily loop when VL==0
909 sync
+= is_svp64_mode
.eq(svp64
.is_svp64_mode
)
910 # calculate the address of the following instruction
911 insn_size
= Mux(svp64
.is_svp64_mode
, 8, 4)
912 sync
+= nia
.eq(cur_state
.pc
+ insn_size
)
913 with m
.If(~svp64
.is_svp64_mode
):
914 # with no prefix, store the instruction
915 # and hand it directly to the next FSM
916 sync
+= dec_opcode_i
.eq(insn
)
917 m
.next
= "INSN_READY"
919 # fetch the rest of the instruction from memory
920 comb
+= self
.imem
.a_pc_i
.eq(cur_state
.pc
+ 4)
921 comb
+= self
.imem
.a_i_valid
.eq(1)
922 comb
+= self
.imem
.f_i_valid
.eq(1)
923 m
.next
= "INSN_READ2"
925 # not SVP64 - 32-bit only
926 sync
+= nia
.eq(cur_state
.pc
+ 4)
927 sync
+= dec_opcode_i
.eq(insn
)
928 if self
.microwatt_compat
:
929 # for verilator debug purposes
930 comb
+= self
.insn
.eq(insn
)
931 comb
+= self
.nia
.eq(cur_state
.pc
)
932 comb
+= self
.msr_o
.eq(cur_state
.msr
)
933 comb
+= self
.nia_req
.eq(1)
934 m
.next
= "INSN_READY"
936 with m
.State("INSN_READ2"):
937 with m
.If(self
.imem
.f_busy_o
): # zzz...
938 # busy: stay in wait-read
939 comb
+= self
.imem
.a_i_valid
.eq(1)
940 comb
+= self
.imem
.f_i_valid
.eq(1)
942 # not busy: instruction fetched
943 if hasattr(core
, "icache"):
944 # blech, icache returns actual instruction
945 insn
= self
.imem
.f_instr_o
947 insn
= get_insn(self
.imem
.f_instr_o
, cur_state
.pc
+4)
948 sync
+= dec_opcode_i
.eq(insn
)
949 m
.next
= "INSN_READY"
950 # TODO: probably can start looking at pdecode2.rm_dec
951 # here or maybe even in INSN_READ state, if svp64_mode
952 # detected, in order to trigger - and wait for - the
955 pmode
= pdecode2
.rm_dec
.predmode
957 if pmode != SVP64PredMode.ALWAYS.value:
958 fire predicate loading FSM and wait before
961 sync += self.srcmask.eq(-1) # set to all 1s
962 sync += self.dstmask.eq(-1) # set to all 1s
963 m.next = "INSN_READY"
966 with m
.State("INSN_READY"):
967 # hand over the instruction, to be decoded
968 comb
+= fetch_insn_o_valid
.eq(1)
969 with m
.If(fetch_insn_i_ready
):
973 def fetch_predicate_fsm(self
, m
,
974 pred_insn_i_valid
, pred_insn_o_ready
,
975 pred_mask_o_valid
, pred_mask_i_ready
):
976 """fetch_predicate_fsm - obtains (constructs in the case of CR)
977 src/dest predicate masks
979 https://bugs.libre-soc.org/show_bug.cgi?id=617
980 the predicates can be read here, by using IntRegs r_ports['pred']
981 or CRRegs r_ports['pred']. in the case of CRs it will have to
982 be done through multiple reads, extracting one relevant at a time.
983 later, a faster way would be to use the 32-bit-wide CR port but
984 this is more complex decoding, here. equivalent code used in
985 ISACaller is "from openpower.decoder.isa.caller import get_predcr"
987 note: this ENTIRE FSM is not to be called when svp64 is disabled
991 pdecode2
= self
.pdecode2
992 rm_dec
= pdecode2
.rm_dec
# SVP64RMModeDecode
993 predmode
= rm_dec
.predmode
994 srcpred
, dstpred
= rm_dec
.srcpred
, rm_dec
.dstpred
995 cr_pred
, int_pred
= self
.cr_pred
, self
.int_pred
# read regfiles
996 # get src/dst step, so we can skip already used mask bits
997 cur_state
= self
.cur_state
998 srcstep
= cur_state
.svstate
.srcstep
999 dststep
= cur_state
.svstate
.dststep
1000 cur_vl
= cur_state
.svstate
.vl
1003 sregread
, sinvert
, sunary
, sall1s
= get_predint(m
, srcpred
, 's')
1004 dregread
, dinvert
, dunary
, dall1s
= get_predint(m
, dstpred
, 'd')
1005 sidx
, scrinvert
= get_predcr(m
, srcpred
, 's')
1006 didx
, dcrinvert
= get_predcr(m
, dstpred
, 'd')
1008 # store fetched masks, for either intpred or crpred
1009 # when src/dst step is not zero, the skipped mask bits need to be
1010 # shifted-out, before actually storing them in src/dest mask
1011 new_srcmask
= Signal(64, reset_less
=True)
1012 new_dstmask
= Signal(64, reset_less
=True)
1014 with m
.FSM(name
="fetch_predicate"):
1016 with m
.State("FETCH_PRED_IDLE"):
1017 comb
+= pred_insn_o_ready
.eq(1)
1018 with m
.If(pred_insn_i_valid
):
1019 with m
.If(predmode
== SVP64PredMode
.INT
):
1020 # skip fetching destination mask register, when zero
1022 sync
+= new_dstmask
.eq(-1)
1023 # directly go to fetch source mask register
1024 # guaranteed not to be zero (otherwise predmode
1025 # would be SVP64PredMode.ALWAYS, not INT)
1026 comb
+= int_pred
.addr
.eq(sregread
)
1027 comb
+= int_pred
.ren
.eq(1)
1028 m
.next
= "INT_SRC_READ"
1029 # fetch destination predicate register
1031 comb
+= int_pred
.addr
.eq(dregread
)
1032 comb
+= int_pred
.ren
.eq(1)
1033 m
.next
= "INT_DST_READ"
1034 with m
.Elif(predmode
== SVP64PredMode
.CR
):
1035 # go fetch masks from the CR register file
1036 sync
+= new_srcmask
.eq(0)
1037 sync
+= new_dstmask
.eq(0)
1040 sync
+= self
.srcmask
.eq(-1)
1041 sync
+= self
.dstmask
.eq(-1)
1042 m
.next
= "FETCH_PRED_DONE"
1044 with m
.State("INT_DST_READ"):
1045 # store destination mask
1046 inv
= Repl(dinvert
, 64)
1048 # set selected mask bit for 1<<r3 mode
1049 dst_shift
= Signal(range(64))
1050 comb
+= dst_shift
.eq(self
.int_pred
.o_data
& 0b111111)
1051 sync
+= new_dstmask
.eq(1 << dst_shift
)
1053 # invert mask if requested
1054 sync
+= new_dstmask
.eq(self
.int_pred
.o_data ^ inv
)
1055 # skip fetching source mask register, when zero
1057 sync
+= new_srcmask
.eq(-1)
1058 m
.next
= "FETCH_PRED_SHIFT_MASK"
1059 # fetch source predicate register
1061 comb
+= int_pred
.addr
.eq(sregread
)
1062 comb
+= int_pred
.ren
.eq(1)
1063 m
.next
= "INT_SRC_READ"
1065 with m
.State("INT_SRC_READ"):
1067 inv
= Repl(sinvert
, 64)
1069 # set selected mask bit for 1<<r3 mode
1070 src_shift
= Signal(range(64))
1071 comb
+= src_shift
.eq(self
.int_pred
.o_data
& 0b111111)
1072 sync
+= new_srcmask
.eq(1 << src_shift
)
1074 # invert mask if requested
1075 sync
+= new_srcmask
.eq(self
.int_pred
.o_data ^ inv
)
1076 m
.next
= "FETCH_PRED_SHIFT_MASK"
1078 # fetch masks from the CR register file
1079 # implements the following loop:
1080 # idx, inv = get_predcr(mask)
1082 # for cr_idx in range(vl):
1083 # cr = crl[cr_idx + SVP64CROffs.CRPred] # takes one cycle
1085 # mask |= 1 << cr_idx
1087 with m
.State("CR_READ"):
1088 # CR index to be read, which will be ready by the next cycle
1089 cr_idx
= Signal
.like(cur_vl
, reset_less
=True)
1090 # submit the read operation to the regfile
1091 with m
.If(cr_idx
!= cur_vl
):
1092 # the CR read port is unary ...
1094 # ... in MSB0 convention ...
1095 # ren = 1 << (7 - cr_idx)
1096 # ... and with an offset:
1097 # ren = 1 << (7 - off - cr_idx)
1098 idx
= SVP64CROffs
.CRPred
+ cr_idx
1099 comb
+= cr_pred
.ren
.eq(1 << (7 - idx
))
1100 # signal data valid in the next cycle
1101 cr_read
= Signal(reset_less
=True)
1102 sync
+= cr_read
.eq(1)
1103 # load the next index
1104 sync
+= cr_idx
.eq(cr_idx
+ 1)
1107 sync
+= cr_read
.eq(0)
1108 sync
+= cr_idx
.eq(0)
1109 m
.next
= "FETCH_PRED_SHIFT_MASK"
1111 # compensate for the one cycle delay on the regfile
1112 cur_cr_idx
= Signal
.like(cur_vl
)
1113 comb
+= cur_cr_idx
.eq(cr_idx
- 1)
1114 # read the CR field, select the appropriate bit
1115 cr_field
= Signal(4)
1118 comb
+= cr_field
.eq(cr_pred
.o_data
)
1119 comb
+= scr_bit
.eq(cr_field
.bit_select(sidx
, 1)
1121 comb
+= dcr_bit
.eq(cr_field
.bit_select(didx
, 1)
1123 # set the corresponding mask bit
1124 bit_to_set
= Signal
.like(self
.srcmask
)
1125 comb
+= bit_to_set
.eq(1 << cur_cr_idx
)
1127 sync
+= new_srcmask
.eq(new_srcmask | bit_to_set
)
1129 sync
+= new_dstmask
.eq(new_dstmask | bit_to_set
)
1131 with m
.State("FETCH_PRED_SHIFT_MASK"):
1132 # shift-out skipped mask bits
1133 sync
+= self
.srcmask
.eq(new_srcmask
>> srcstep
)
1134 sync
+= self
.dstmask
.eq(new_dstmask
>> dststep
)
1135 m
.next
= "FETCH_PRED_DONE"
1137 with m
.State("FETCH_PRED_DONE"):
1138 comb
+= pred_mask_o_valid
.eq(1)
1139 with m
.If(pred_mask_i_ready
):
1140 m
.next
= "FETCH_PRED_IDLE"
1142 def issue_fsm(self
, m
, core
, nia
,
1143 dbg
, core_rst
, is_svp64_mode
,
1144 fetch_pc_o_ready
, fetch_pc_i_valid
,
1145 fetch_insn_o_valid
, fetch_insn_i_ready
,
1146 pred_insn_i_valid
, pred_insn_o_ready
,
1147 pred_mask_o_valid
, pred_mask_i_ready
,
1148 exec_insn_i_valid
, exec_insn_o_ready
,
1149 exec_pc_o_valid
, exec_pc_i_ready
):
1152 decode / issue FSM. this interacts with the "fetch" FSM
1153 through fetch_insn_ready/valid (incoming) and fetch_pc_ready/valid
1154 (outgoing). also interacts with the "execute" FSM
1155 through exec_insn_ready/valid (outgoing) and exec_pc_ready/valid
1157 SVP64 RM prefixes have already been set up by the
1158 "fetch" phase, so execute is fairly straightforward.
1163 pdecode2
= self
.pdecode2
1164 cur_state
= self
.cur_state
1165 new_svstate
= self
.new_svstate
1168 dec_opcode_i
= pdecode2
.dec
.raw_opcode_in
# raw opcode
1170 # for updating svstate (things like srcstep etc.)
1171 comb
+= new_svstate
.eq(cur_state
.svstate
)
1173 # precalculate srcstep+1 and dststep+1
1174 cur_srcstep
= cur_state
.svstate
.srcstep
1175 cur_dststep
= cur_state
.svstate
.dststep
1176 next_srcstep
= Signal
.like(cur_srcstep
)
1177 next_dststep
= Signal
.like(cur_dststep
)
1178 comb
+= next_srcstep
.eq(cur_state
.svstate
.srcstep
+1)
1179 comb
+= next_dststep
.eq(cur_state
.svstate
.dststep
+1)
1181 # note if an exception happened. in a pipelined or OoO design
1182 # this needs to be accompanied by "shadowing" (or stalling)
1183 exc_happened
= self
.core
.o
.exc_happened
1184 # also note instruction fetch failed
1185 if hasattr(core
, "icache"):
1186 fetch_failed
= core
.icache
.i_out
.fetch_failed
1188 # set to fault in decoder
1189 # update (highest priority) instruction fault
1190 rising_fetch_failed
= rising_edge(m
, fetch_failed
)
1191 with m
.If(rising_fetch_failed
):
1192 sync
+= pdecode2
.instr_fault
.eq(1)
1194 fetch_failed
= Const(0, 1)
1195 flush_needed
= False
1197 sync
+= fetch_pc_i_valid
.eq(0)
1199 with m
.FSM(name
="issue_fsm"):
1201 with m
.State("PRE_IDLE"):
1202 with m
.If(~dbg
.core_stop_o
& ~core_rst
):
1203 m
.next
= "ISSUE_START"
1205 # sync with the "fetch" phase which is reading the instruction
1206 # at this point, there is no instruction running, that
1207 # could inadvertently update the PC.
1208 with m
.State("ISSUE_START"):
1209 # reset instruction fault
1210 sync
+= pdecode2
.instr_fault
.eq(0)
1211 # wait on "core stop" release, before next fetch
1212 # need to do this here, in case we are in a VL==0 loop
1213 with m
.If(~dbg
.core_stop_o
& ~core_rst
):
1214 sync
+= fetch_pc_i_valid
.eq(1) # tell fetch to start
1215 sync
+= cur_state
.pc
.eq(dbg
.state
.pc
)
1216 sync
+= cur_state
.svstate
.eq(dbg
.state
.svstate
)
1217 sync
+= cur_state
.msr
.eq(dbg
.state
.msr
)
1218 with m
.If(fetch_pc_o_ready
): # fetch acknowledged us
1219 m
.next
= "INSN_WAIT"
1221 # tell core it's stopped, and acknowledge debug handshake
1222 comb
+= dbg
.core_stopped_i
.eq(1)
1223 # while stopped, allow updating SVSTATE
1224 with m
.If(self
.svstate_i
.ok
):
1225 comb
+= new_svstate
.eq(self
.svstate_i
.data
)
1226 comb
+= self
.update_svstate
.eq(1)
1227 sync
+= self
.sv_changed
.eq(1)
1229 # wait for an instruction to arrive from Fetch
1230 with m
.State("INSN_WAIT"):
1231 # when using "single-step" mode, checking dbg.stopping_o
1232 # prevents progress. allow issue to proceed once started
1234 #if self.allow_overlap:
1235 # stopping = dbg.stopping_o
1236 with m
.If(stopping
):
1237 # stopping: jump back to idle
1238 m
.next
= "ISSUE_START"
1240 # request the icache to stop asserting "failed"
1241 comb
+= core
.icache
.flush_in
.eq(1)
1242 # stop instruction fault
1243 sync
+= pdecode2
.instr_fault
.eq(0)
1245 comb
+= fetch_insn_i_ready
.eq(1)
1246 with m
.If(fetch_insn_o_valid
):
1247 # loop into ISSUE_START if it's a SVP64 instruction
1248 # and VL == 0. this because VL==0 is a for-loop
1249 # from 0 to 0 i.e. always, always a NOP.
1250 cur_vl
= cur_state
.svstate
.vl
1251 with m
.If(is_svp64_mode
& (cur_vl
== 0)):
1252 # update the PC before fetching the next instruction
1253 # since we are in a VL==0 loop, no instruction was
1254 # executed that we could be overwriting
1255 comb
+= self
.state_w_pc
.wen
.eq(1 << StateRegs
.PC
)
1256 comb
+= self
.state_w_pc
.i_data
.eq(nia
)
1257 comb
+= self
.insn_done
.eq(1)
1258 m
.next
= "ISSUE_START"
1261 m
.next
= "PRED_START" # fetching predicate
1263 m
.next
= "DECODE_SV" # skip predication
1265 with m
.State("PRED_START"):
1266 comb
+= pred_insn_i_valid
.eq(1) # tell fetch_pred to start
1267 with m
.If(pred_insn_o_ready
): # fetch_pred acknowledged us
1268 m
.next
= "MASK_WAIT"
1270 with m
.State("MASK_WAIT"):
1271 comb
+= pred_mask_i_ready
.eq(1) # ready to receive the masks
1272 with m
.If(pred_mask_o_valid
): # predication masks are ready
1273 m
.next
= "PRED_SKIP"
1275 # skip zeros in predicate
1276 with m
.State("PRED_SKIP"):
1277 with m
.If(~is_svp64_mode
):
1278 m
.next
= "DECODE_SV" # nothing to do
1281 pred_src_zero
= pdecode2
.rm_dec
.pred_sz
1282 pred_dst_zero
= pdecode2
.rm_dec
.pred_dz
1284 # new srcstep, after skipping zeros
1285 skip_srcstep
= Signal
.like(cur_srcstep
)
1286 # value to be added to the current srcstep
1287 src_delta
= Signal
.like(cur_srcstep
)
1288 # add leading zeros to srcstep, if not in zero mode
1289 with m
.If(~pred_src_zero
):
1290 # priority encoder (count leading zeros)
1291 # append guard bit, in case the mask is all zeros
1292 pri_enc_src
= PriorityEncoder(65)
1293 m
.submodules
.pri_enc_src
= pri_enc_src
1294 comb
+= pri_enc_src
.i
.eq(Cat(self
.srcmask
,
1296 comb
+= src_delta
.eq(pri_enc_src
.o
)
1297 # apply delta to srcstep
1298 comb
+= skip_srcstep
.eq(cur_srcstep
+ src_delta
)
1299 # shift-out all leading zeros from the mask
1300 # plus the leading "one" bit
1301 # TODO count leading zeros and shift-out the zero
1302 # bits, in the same step, in hardware
1303 sync
+= self
.srcmask
.eq(self
.srcmask
>> (src_delta
+1))
1305 # same as above, but for dststep
1306 skip_dststep
= Signal
.like(cur_dststep
)
1307 dst_delta
= Signal
.like(cur_dststep
)
1308 with m
.If(~pred_dst_zero
):
1309 pri_enc_dst
= PriorityEncoder(65)
1310 m
.submodules
.pri_enc_dst
= pri_enc_dst
1311 comb
+= pri_enc_dst
.i
.eq(Cat(self
.dstmask
,
1313 comb
+= dst_delta
.eq(pri_enc_dst
.o
)
1314 comb
+= skip_dststep
.eq(cur_dststep
+ dst_delta
)
1315 sync
+= self
.dstmask
.eq(self
.dstmask
>> (dst_delta
+1))
1317 # TODO: initialize mask[VL]=1 to avoid passing past VL
1318 with m
.If((skip_srcstep
>= cur_vl
) |
1319 (skip_dststep
>= cur_vl
)):
1320 # end of VL loop. Update PC and reset src/dst step
1321 comb
+= self
.state_w_pc
.wen
.eq(1 << StateRegs
.PC
)
1322 comb
+= self
.state_w_pc
.i_data
.eq(nia
)
1323 comb
+= new_svstate
.srcstep
.eq(0)
1324 comb
+= new_svstate
.dststep
.eq(0)
1325 comb
+= self
.update_svstate
.eq(1)
1326 # synchronize with the simulator
1327 comb
+= self
.insn_done
.eq(1)
1329 m
.next
= "ISSUE_START"
1331 # update new src/dst step
1332 comb
+= new_svstate
.srcstep
.eq(skip_srcstep
)
1333 comb
+= new_svstate
.dststep
.eq(skip_dststep
)
1334 comb
+= self
.update_svstate
.eq(1)
1336 m
.next
= "DECODE_SV"
1338 # pass predicate mask bits through to satellite decoders
1339 # TODO: for SIMD this will be *multiple* bits
1340 sync
+= core
.i
.sv_pred_sm
.eq(self
.srcmask
[0])
1341 sync
+= core
.i
.sv_pred_dm
.eq(self
.dstmask
[0])
1343 # after src/dst step have been updated, we are ready
1344 # to decode the instruction
1345 with m
.State("DECODE_SV"):
1346 # decode the instruction
1347 with m
.If(~fetch_failed
):
1348 sync
+= pdecode2
.instr_fault
.eq(0)
1349 sync
+= core
.i
.e
.eq(pdecode2
.e
)
1350 sync
+= core
.i
.state
.eq(cur_state
)
1351 sync
+= core
.i
.raw_insn_i
.eq(dec_opcode_i
)
1352 sync
+= core
.i
.bigendian_i
.eq(self
.core_bigendian_i
)
1354 sync
+= core
.i
.sv_rm
.eq(pdecode2
.sv_rm
)
1355 # set RA_OR_ZERO detection in satellite decoders
1356 sync
+= core
.i
.sv_a_nz
.eq(pdecode2
.sv_a_nz
)
1357 # and svp64 detection
1358 sync
+= core
.i
.is_svp64_mode
.eq(is_svp64_mode
)
1359 # and svp64 bit-rev'd ldst mode
1360 ldst_dec
= pdecode2
.use_svp64_ldst_dec
1361 sync
+= core
.i
.use_svp64_ldst_dec
.eq(ldst_dec
)
1362 # after decoding, reset any previous exception condition,
1363 # allowing it to be set again during the next execution
1364 sync
+= pdecode2
.ldst_exc
.eq(0)
1366 m
.next
= "INSN_EXECUTE" # move to "execute"
1368 # handshake with execution FSM, move to "wait" once acknowledged
1369 with m
.State("INSN_EXECUTE"):
1370 # when using "single-step" mode, checking dbg.stopping_o
1371 # prevents progress. allow execute to proceed once started
1373 #if self.allow_overlap:
1374 # stopping = dbg.stopping_o
1375 with m
.If(stopping
):
1376 # stopping: jump back to idle
1377 m
.next
= "ISSUE_START"
1379 # request the icache to stop asserting "failed"
1380 comb
+= core
.icache
.flush_in
.eq(1)
1381 # stop instruction fault
1382 sync
+= pdecode2
.instr_fault
.eq(0)
1384 comb
+= exec_insn_i_valid
.eq(1) # trigger execute
1385 with m
.If(exec_insn_o_ready
): # execute acknowledged us
1386 m
.next
= "EXECUTE_WAIT"
1388 with m
.State("EXECUTE_WAIT"):
1389 comb
+= exec_pc_i_ready
.eq(1)
1390 # see https://bugs.libre-soc.org/show_bug.cgi?id=636
1391 # the exception info needs to be blatted into
1392 # pdecode.ldst_exc, and the instruction "re-run".
1393 # when ldst_exc.happened is set, the PowerDecoder2
1394 # reacts very differently: it re-writes the instruction
1395 # with a "trap" (calls PowerDecoder2.trap()) which
1396 # will *overwrite* whatever was requested and jump the
1397 # PC to the exception address, as well as alter MSR.
1398 # nothing else needs to be done other than to note
1399 # the change of PC and MSR (and, later, SVSTATE)
1400 with m
.If(exc_happened
):
1401 mmu
= core
.fus
.get_exc("mmu0")
1402 ldst
= core
.fus
.get_exc("ldst0")
1404 with m
.If(fetch_failed
):
1405 # instruction fetch: exception is from MMU
1406 # reset instr_fault (highest priority)
1407 sync
+= pdecode2
.ldst_exc
.eq(mmu
)
1408 sync
+= pdecode2
.instr_fault
.eq(0)
1410 # request icache to stop asserting "failed"
1411 comb
+= core
.icache
.flush_in
.eq(1)
1412 with m
.If(~fetch_failed
):
1413 # otherwise assume it was a LDST exception
1414 sync
+= pdecode2
.ldst_exc
.eq(ldst
)
1416 with m
.If(exec_pc_o_valid
):
1418 # was this the last loop iteration?
1420 cur_vl
= cur_state
.svstate
.vl
1421 comb
+= is_last
.eq(next_srcstep
== cur_vl
)
1423 with m
.If(pdecode2
.instr_fault
):
1424 # reset instruction fault, try again
1425 sync
+= pdecode2
.instr_fault
.eq(0)
1426 m
.next
= "ISSUE_START"
1428 # return directly to Decode if Execute generated an
1430 with m
.Elif(pdecode2
.ldst_exc
.happened
):
1431 m
.next
= "DECODE_SV"
1433 # if MSR, PC or SVSTATE were changed by the previous
1434 # instruction, go directly back to Fetch, without
1435 # updating either MSR PC or SVSTATE
1436 with m
.Elif(self
.msr_changed | self
.pc_changed |
1438 m
.next
= "ISSUE_START"
1440 # also return to Fetch, when no output was a vector
1441 # (regardless of SRCSTEP and VL), or when the last
1442 # instruction was really the last one of the VL loop
1443 with m
.Elif((~pdecode2
.loop_continue
) | is_last
):
1444 # before going back to fetch, update the PC state
1445 # register with the NIA.
1446 # ok here we are not reading the branch unit.
1447 # TODO: this just blithely overwrites whatever
1448 # pipeline updated the PC
1449 comb
+= self
.state_w_pc
.wen
.eq(1 << StateRegs
.PC
)
1450 comb
+= self
.state_w_pc
.i_data
.eq(nia
)
1451 # reset SRCSTEP before returning to Fetch
1453 with m
.If(pdecode2
.loop_continue
):
1454 comb
+= new_svstate
.srcstep
.eq(0)
1455 comb
+= new_svstate
.dststep
.eq(0)
1456 comb
+= self
.update_svstate
.eq(1)
1458 comb
+= new_svstate
.srcstep
.eq(0)
1459 comb
+= new_svstate
.dststep
.eq(0)
1460 comb
+= self
.update_svstate
.eq(1)
1461 m
.next
= "ISSUE_START"
1463 # returning to Execute? then, first update SRCSTEP
1465 comb
+= new_svstate
.srcstep
.eq(next_srcstep
)
1466 comb
+= new_svstate
.dststep
.eq(next_dststep
)
1467 comb
+= self
.update_svstate
.eq(1)
1468 # return to mask skip loop
1469 m
.next
= "PRED_SKIP"
1472 # check if svstate needs updating: if so, write it to State Regfile
1473 with m
.If(self
.update_svstate
):
1474 sync
+= cur_state
.svstate
.eq(self
.new_svstate
) # for next clock
1476 def execute_fsm(self
, m
, core
,
1477 exec_insn_i_valid
, exec_insn_o_ready
,
1478 exec_pc_o_valid
, exec_pc_i_ready
):
1481 execute FSM. this interacts with the "issue" FSM
1482 through exec_insn_ready/valid (incoming) and exec_pc_ready/valid
1483 (outgoing). SVP64 RM prefixes have already been set up by the
1484 "issue" phase, so execute is fairly straightforward.
1490 pdecode2
= self
.pdecode2
1491 cur_state
= self
.cur_state
1494 core_busy_o
= core
.n
.o_data
.busy_o
# core is busy
1495 core_ivalid_i
= core
.p
.i_valid
# instruction is valid
1497 if hasattr(core
, "icache"):
1498 fetch_failed
= core
.icache
.i_out
.fetch_failed
1500 fetch_failed
= Const(0, 1)
1502 with m
.FSM(name
="exec_fsm"):
1504 # waiting for instruction bus (stays there until not busy)
1505 with m
.State("INSN_START"):
1506 comb
+= exec_insn_o_ready
.eq(1)
1507 with m
.If(exec_insn_i_valid
):
1508 comb
+= core_ivalid_i
.eq(1) # instruction is valid/issued
1509 sync
+= self
.sv_changed
.eq(0)
1510 sync
+= self
.pc_changed
.eq(0)
1511 sync
+= self
.msr_changed
.eq(0)
1512 with m
.If(core
.p
.o_ready
): # only move if accepted
1513 m
.next
= "INSN_ACTIVE" # move to "wait completion"
1515 # instruction started: must wait till it finishes
1516 with m
.State("INSN_ACTIVE"):
1517 # note changes to MSR, PC and SVSTATE
1518 with m
.If(self
.state_nia
.wen
& (1 << StateRegs
.SVSTATE
)):
1519 sync
+= self
.sv_changed
.eq(1)
1520 with m
.If(self
.state_nia
.wen
& (1 << StateRegs
.MSR
)):
1521 sync
+= self
.msr_changed
.eq(1)
1522 with m
.If(self
.state_nia
.wen
& (1 << StateRegs
.PC
)):
1523 sync
+= self
.pc_changed
.eq(1)
1524 # and note changes to DEC/TB, to be passed to DEC/TB FSM
1525 with m
.If(self
.state_spr
.wen
& (1 << StateRegs
.TB
)):
1526 comb
+= self
.pause_dec_tb
.eq(1)
1527 # but also zero-out the cur_state DEC so that, on
1528 # the next instruction, if it is "enable interrupt"
1529 # the delay between the DEC/TB FSM reading and updating
1530 # cur_state.dec doesn't trigger a spurious interrupt.
1531 # the DEC/TB FSM will read the regfile and update to
1532 # the correct value, so having cur_state.dec set to zero
1533 # for a while is no big deal.
1534 with m
.If(self
.state_spr
.wen
& (1 << StateRegs
.DEC
)):
1535 comb
+= self
.pause_dec_tb
.eq(1)
1536 sync
+= cur_state
.dec
.eq(0) # only needs top bit clear
1537 with m
.If(~core_busy_o
): # instruction done!
1538 comb
+= exec_pc_o_valid
.eq(1)
1539 with m
.If(exec_pc_i_ready
):
1540 # when finished, indicate "done".
1541 # however, if there was an exception, the instruction
1542 # is *not* yet done. this is an implementation
1543 # detail: we choose to implement exceptions by
1544 # taking the exception information from the LDST
1545 # unit, putting that *back* into the PowerDecoder2,
1546 # and *re-running the entire instruction*.
1547 # if we erroneously indicate "done" here, it is as if
1548 # there were *TWO* instructions:
1549 # 1) the failed LDST 2) a TRAP.
1550 with m
.If(~pdecode2
.ldst_exc
.happened
&
1551 ~pdecode2
.instr_fault
):
1552 comb
+= self
.insn_done
.eq(1)
1553 m
.next
= "INSN_START" # back to fetch
1554 # terminate returns directly to INSN_START
1555 with m
.If(dbg
.terminate_i
):
1556 # comb += self.insn_done.eq(1) - no because it's not
1557 m
.next
= "INSN_START" # back to fetch
1559 def elaborate(self
, platform
):
1560 m
= super().elaborate(platform
)
1562 comb
, sync
= m
.d
.comb
, m
.d
.sync
1563 cur_state
= self
.cur_state
1564 pdecode2
= self
.pdecode2
1568 # set up peripherals and core
1569 core_rst
= self
.core_rst
1571 # indicate to outside world if any FU is still executing
1572 comb
+= self
.any_busy
.eq(core
.n
.o_data
.any_busy_o
) # any FU executing
1574 # address of the next instruction, in the absence of a branch
1575 # depends on the instruction size
1578 # connect up debug signals
1579 with m
.If(core
.o
.core_terminate_o
):
1580 comb
+= dbg
.terminate_i
.eq(1)
1582 # pass the prefix mode from Fetch to Issue, so the latter can loop
1584 is_svp64_mode
= Signal()
1586 # there are *THREE^WFOUR-if-SVP64-enabled* FSMs, fetch (32/64-bit)
1587 # issue, decode/execute, now joined by "Predicate fetch/calculate".
1588 # these are the handshake signals between each
1590 # fetch FSM can run as soon as the PC is valid
1591 fetch_pc_i_valid
= Signal() # Execute tells Fetch "start next read"
1592 fetch_pc_o_ready
= Signal() # Fetch Tells SVSTATE "proceed"
1594 # fetch FSM hands over the instruction to be decoded / issued
1595 fetch_insn_o_valid
= Signal()
1596 fetch_insn_i_ready
= Signal()
1598 # predicate fetch FSM decodes and fetches the predicate
1599 pred_insn_i_valid
= Signal()
1600 pred_insn_o_ready
= Signal()
1602 # predicate fetch FSM delivers the masks
1603 pred_mask_o_valid
= Signal()
1604 pred_mask_i_ready
= Signal()
1606 # issue FSM delivers the instruction to the be executed
1607 exec_insn_i_valid
= Signal()
1608 exec_insn_o_ready
= Signal()
1610 # execute FSM, hands over the PC/SVSTATE back to the issue FSM
1611 exec_pc_o_valid
= Signal()
1612 exec_pc_i_ready
= Signal()
1614 # the FSMs here are perhaps unusual in that they detect conditions
1615 # then "hold" information, combinatorially, for the core
1616 # (as opposed to using sync - which would be on a clock's delay)
1617 # this includes the actual opcode, valid flags and so on.
1619 # Fetch, then predicate fetch, then Issue, then Execute.
1620 # Issue is where the VL for-loop # lives. the ready/valid
1621 # signalling is used to communicate between the four.
1623 self
.fetch_fsm(m
, dbg
, core
, core_rst
, nia
, is_svp64_mode
,
1624 fetch_pc_o_ready
, fetch_pc_i_valid
,
1625 fetch_insn_o_valid
, fetch_insn_i_ready
)
1627 self
.issue_fsm(m
, core
, nia
,
1628 dbg
, core_rst
, is_svp64_mode
,
1629 fetch_pc_o_ready
, fetch_pc_i_valid
,
1630 fetch_insn_o_valid
, fetch_insn_i_ready
,
1631 pred_insn_i_valid
, pred_insn_o_ready
,
1632 pred_mask_o_valid
, pred_mask_i_ready
,
1633 exec_insn_i_valid
, exec_insn_o_ready
,
1634 exec_pc_o_valid
, exec_pc_i_ready
)
1637 self
.fetch_predicate_fsm(m
,
1638 pred_insn_i_valid
, pred_insn_o_ready
,
1639 pred_mask_o_valid
, pred_mask_i_ready
)
1641 self
.execute_fsm(m
, core
,
1642 exec_insn_i_valid
, exec_insn_o_ready
,
1643 exec_pc_o_valid
, exec_pc_i_ready
)
1645 # whatever was done above, over-ride it if core reset is held.
1646 # set NIA to pc_at_reset
1647 with m
.If(core_rst
):
1648 sync
+= nia
.eq(self
.core
.pc_at_reset
)
1653 class TestIssuer(Elaboratable
):
1654 def __init__(self
, pspec
):
1655 self
.ti
= TestIssuerInternal(pspec
)
1656 self
.pll
= DummyPLL(instance
=True)
1658 self
.dbg_rst_i
= Signal(reset_less
=True)
1660 # PLL direct clock or not
1661 self
.pll_en
= hasattr(pspec
, "use_pll") and pspec
.use_pll
1663 self
.pll_test_o
= Signal(reset_less
=True)
1664 self
.pll_vco_o
= Signal(reset_less
=True)
1665 self
.clk_sel_i
= Signal(2, reset_less
=True)
1666 self
.ref_clk
= ClockSignal() # can't rename it but that's ok
1667 self
.pllclk_clk
= ClockSignal("pllclk")
1669 def elaborate(self
, platform
):
1673 # TestIssuer nominally runs at main clock, actually it is
1674 # all combinatorial internally except for coresync'd components
1675 m
.submodules
.ti
= ti
= self
.ti
1678 # ClockSelect runs at PLL output internal clock rate
1679 m
.submodules
.wrappll
= pll
= self
.pll
1681 # add clock domains from PLL
1682 cd_pll
= ClockDomain("pllclk")
1685 # PLL clock established. has the side-effect of running clklsel
1686 # at the PLL's speed (see DomainRenamer("pllclk") above)
1687 pllclk
= self
.pllclk_clk
1688 comb
+= pllclk
.eq(pll
.clk_pll_o
)
1690 # wire up external 24mhz to PLL
1691 #comb += pll.clk_24_i.eq(self.ref_clk)
1692 # output 18 mhz PLL test signal, and analog oscillator out
1693 comb
+= self
.pll_test_o
.eq(pll
.pll_test_o
)
1694 comb
+= self
.pll_vco_o
.eq(pll
.pll_vco_o
)
1696 # input to pll clock selection
1697 comb
+= pll
.clk_sel_i
.eq(self
.clk_sel_i
)
1699 # now wire up ResetSignals. don't mind them being in this domain
1700 pll_rst
= ResetSignal("pllclk")
1701 comb
+= pll_rst
.eq(ResetSignal())
1703 # internal clock is set to selector clock-out. has the side-effect of
1704 # running TestIssuer at this speed (see DomainRenamer("intclk") above)
1705 # debug clock runs at coresync internal clock
1706 if self
.ti
.dbg_domain
!= 'sync':
1707 cd_dbgsync
= ClockDomain("dbgsync")
1708 intclk
= ClockSignal(self
.ti
.core_domain
)
1709 dbgclk
= ClockSignal(self
.ti
.dbg_domain
)
1710 # XXX BYPASS PLL XXX
1711 # XXX BYPASS PLL XXX
1712 # XXX BYPASS PLL XXX
1714 comb
+= intclk
.eq(self
.ref_clk
)
1715 assert self
.ti
.core_domain
!= 'sync', \
1716 "cannot set core_domain to sync and use pll at the same time"
1718 if self
.ti
.core_domain
!= 'sync':
1719 comb
+= intclk
.eq(ClockSignal())
1720 if self
.ti
.dbg_domain
!= 'sync':
1721 dbgclk
= ClockSignal(self
.ti
.dbg_domain
)
1722 comb
+= dbgclk
.eq(intclk
)
1723 comb
+= self
.ti
.dbg_rst_i
.eq(self
.dbg_rst_i
)
1728 return list(self
.ti
.ports()) + list(self
.pll
.ports()) + \
1729 [ClockSignal(), ResetSignal()]
1731 def external_ports(self
):
1732 ports
= self
.ti
.external_ports()
1733 ports
.append(ClockSignal())
1734 ports
.append(ResetSignal())
1736 ports
.append(self
.clk_sel_i
)
1737 ports
.append(self
.pll
.clk_24_i
)
1738 ports
.append(self
.pll_test_o
)
1739 ports
.append(self
.pll_vco_o
)
1740 ports
.append(self
.pllclk_clk
)
1741 ports
.append(self
.ref_clk
)
1745 if __name__
== '__main__':
1746 units
= {'alu': 1, 'cr': 1, 'branch': 1, 'trap': 1, 'logical': 1,
1752 pspec
= TestMemPspec(ldst_ifacetype
='bare_wb',
1753 imem_ifacetype
='bare_wb',
1758 dut
= TestIssuer(pspec
)
1759 vl
= main(dut
, ports
=dut
.ports(), name
="test_issuer")
1761 if len(sys
.argv
) == 1:
1762 vl
= rtlil
.convert(dut
, ports
=dut
.external_ports(), name
="test_issuer")
1763 with
open("test_issuer.il", "w") as f
: