3 not in any way intended for production use. this runs a FSM that:
5 * reads the Program Counter from StateRegs
6 * reads an instruction from a fixed-size Test Memory
7 * issues it to the Simple Core
8 * waits for it to complete
10 * does it all over again
12 the purpose of this module is to verify the functional correctness
13 of the Function Units in the absolute simplest and clearest possible
14 way, and to at provide something that can be further incrementally
18 from nmigen
import (Elaboratable
, Module
, Signal
, ClockSignal
, ResetSignal
,
19 ClockDomain
, DomainRenamer
)
20 from nmigen
.cli
import rtlil
21 from nmigen
.cli
import main
24 from soc
.decoder
.power_decoder
import create_pdecode
25 from soc
.decoder
.power_decoder2
import PowerDecode2
26 from soc
.decoder
.decode2execute1
import Data
27 from soc
.experiment
.testmem
import TestMemory
# test only for instructions
28 from soc
.regfile
.regfiles
import StateRegs
29 from soc
.simple
.core
import NonProductionCore
30 from soc
.config
.test
.test_loadstore
import TestMemPspec
31 from soc
.config
.ifetch
import ConfigFetchUnit
32 from soc
.decoder
.power_enums
import MicrOp
33 from soc
.debug
.dmi
import CoreDebug
, DMIInterface
34 from soc
.config
.state
import CoreState
36 from nmutil
.util
import rising_edge
39 class TestIssuer(Elaboratable
):
40 """TestIssuer - reads instructions from TestMemory and issues them
42 efficiency and speed is not the main goal here: functional correctness is.
44 def __init__(self
, pspec
):
45 # main instruction core
46 self
.core
= core
= NonProductionCore(pspec
)
49 pdecode
= create_pdecode()
50 self
.pdecode2
= PowerDecode2(pdecode
) # decoder
52 # Test Instruction memory
53 self
.imem
= ConfigFetchUnit(pspec
).fu
54 # one-row cache of instruction read
55 self
.iline
= Signal(64) # one instruction line
56 self
.iprev_adr
= Signal(64) # previous address: if different, do read
59 self
.dbg
= CoreDebug()
61 # instruction go/monitor
62 self
.pc_o
= Signal(64, reset_less
=True)
63 self
.pc_i
= Data(64, "pc_i") # set "ok" to indicate "please change me"
64 self
.core_bigendian_i
= Signal()
65 self
.busy_o
= Signal(reset_less
=True)
66 self
.memerr_o
= Signal(reset_less
=True)
68 # FAST regfile read /write ports for PC and MSR
69 self
.state_r_pc
= self
.core
.regs
.rf
['state'].r_ports
['cia'] # PC rd
70 self
.state_w_pc
= self
.core
.regs
.rf
['state'].w_ports
['d_wr1'] # PC wr
71 self
.state_r_msr
= self
.core
.regs
.rf
['state'].r_ports
['msr'] # MSR rd
73 # DMI interface access
74 intrf
= self
.core
.regs
.rf
['int']
75 self
.int_r
= intrf
.r_ports
['dmi'] # INT read
77 # hack method of keeping an eye on whether branch/trap set the PC
78 self
.state_nia
= self
.core
.regs
.rf
['state'].w_ports
['nia']
79 self
.state_nia
.wen
.name
= 'state_nia_wen'
81 def elaborate(self
, platform
):
83 comb
, sync
= m
.d
.comb
, m
.d
.sync
85 m
.submodules
.core
= core
= DomainRenamer("coresync")(self
.core
)
86 m
.submodules
.imem
= imem
= self
.imem
87 m
.submodules
.dbg
= dbg
= self
.dbg
90 pdecode
= create_pdecode()
91 m
.submodules
.dec2
= pdecode2
= self
.pdecode2
96 intrf
= self
.core
.regs
.rf
['int']
98 # clock delay power-on reset
99 cd_por
= ClockDomain(reset_less
=True)
100 cd_sync
= ClockDomain()
101 core_sync
= ClockDomain("coresync")
102 m
.domains
+= cd_por
, cd_sync
, core_sync
104 delay
= Signal(range(4), reset
=3)
105 with m
.If(delay
!= 0):
106 m
.d
.por
+= delay
.eq(delay
- 1)
107 comb
+= cd_por
.clk
.eq(ClockSignal())
108 comb
+= core_sync
.clk
.eq(ClockSignal())
109 # power-on reset delay
110 comb
+= core
.core_reset_i
.eq(delay
!= 0 | dbg
.core_rst_o
)
112 # busy/halted signals from core
113 comb
+= self
.busy_o
.eq(core
.busy_o
)
114 comb
+= pdecode2
.dec
.bigendian
.eq(self
.core_bigendian_i
)
116 # current state (MSR/PC at the moment
117 cur_state
= CoreState("cur")
119 # temporary hack: says "go" immediately for both address gen and ST
121 ldst
= core
.fus
.fus
['ldst0']
122 st_go_edge
= rising_edge(m
, ldst
.st
.rel_o
)
123 m
.d
.comb
+= ldst
.ad
.go_i
.eq(ldst
.ad
.rel_o
) # link addr-go direct to rel
124 m
.d
.comb
+= ldst
.st
.go_i
.eq(st_go_edge
) # link store-go to rising rel
126 # PC and instruction from I-Memory
127 pc_changed
= Signal() # note write to PC
128 comb
+= self
.pc_o
.eq(cur_state
.pc
)
131 # next instruction (+4 on current)
132 nia
= Signal(64, reset_less
=True)
133 comb
+= nia
.eq(cur_state
.pc
+ 4)
136 pc
= Signal(64, reset_less
=True)
137 with m
.If(self
.pc_i
.ok
):
138 # incoming override (start from pc_i)
139 comb
+= pc
.eq(self
.pc_i
.data
)
141 # otherwise read StateRegs regfile for PC
142 comb
+= self
.state_r_pc
.ren
.eq(1<<StateRegs
.PC
)
143 comb
+= pc
.eq(self
.state_r_pc
.data_o
)
145 # don't write pc every cycle
146 sync
+= self
.state_w_pc
.wen
.eq(0)
147 sync
+= self
.state_w_pc
.data_i
.eq(0)
149 # don't read msr every cycle
150 sync
+= self
.state_r_msr
.ren
.eq(0)
152 # connect up debug signals
153 # TODO comb += core.icache_rst_i.eq(dbg.icache_rst_o)
154 comb
+= core
.core_stopped_i
.eq(dbg
.core_stop_o
)
155 comb
+= dbg
.terminate_i
.eq(core
.core_terminate_o
)
156 comb
+= dbg
.state
.pc
.eq(pc
)
157 comb
+= dbg
.state
.msr
.eq(cur_state
.msr
)
160 core_busy_o
= core
.busy_o
# core is busy
161 core_ivalid_i
= core
.ivalid_i
# instruction is valid
162 core_issue_i
= core
.issue_i
# instruction is issued
163 dec_opcode_i
= pdecode2
.dec
.raw_opcode_in
# raw opcode
165 insn_type
= core
.e
.do
.insn_type
166 insn_state
= pdecode2
.state
168 # actually use a nmigen FSM for the first time (w00t)
169 # this FSM is perhaps unusual in that it detects conditions
170 # then "holds" information, combinatorially, for the core
171 # (as opposed to using sync - which would be on a clock's delay)
172 # this includes the actual opcode, valid flags and so on.
176 with m
.State("IDLE"):
177 sync
+= pc_changed
.eq(0)
179 with m
.If(~dbg
.core_stop_o
& ~core
.core_reset_i
):
180 # instruction allowed to go: start by reading the PC
181 # capture the PC and also drop it into Insn Memory
182 # we have joined a pair of combinatorial memory
183 # lookups together. this is Generally Bad.
184 comb
+= self
.imem
.a_pc_i
.eq(pc
)
185 comb
+= self
.imem
.a_valid_i
.eq(1)
186 comb
+= self
.imem
.f_valid_i
.eq(1)
187 sync
+= cur_state
.pc
.eq(pc
)
189 # read MSR, latch it, and put it in decode "state"
190 sync
+= self
.state_r_msr
.ren
.eq(1<<StateRegs
.MSR
)
191 sync
+= cur_state
.msr
.eq(self
.state_r_msr
.data_o
)
193 m
.next
= "INSN_READ" # move to "wait for bus" phase
195 # dummy pause to find out why simulation is not keeping up
196 with m
.State("INSN_READ"):
197 with m
.If(self
.imem
.f_busy_o
): # zzz...
198 # busy: stay in wait-read
199 comb
+= self
.imem
.a_valid_i
.eq(1)
200 comb
+= self
.imem
.f_valid_i
.eq(1)
202 # not busy: instruction fetched
203 f_instr_o
= self
.imem
.f_instr_o
204 if f_instr_o
.width
== 32:
207 insn
= f_instr_o
.word_select(cur_state
.pc
[2], 32)
208 comb
+= dec_opcode_i
.eq(insn
) # actual opcode
209 sync
+= core
.e
.eq(pdecode2
.e
)
210 sync
+= ilatch
.eq(insn
) # latch current insn
211 # also drop PC and MSR into decode "state"
212 sync
+= insn_state
.eq(cur_state
)
213 m
.next
= "INSN_START" # move to "start"
215 # waiting for instruction bus (stays there until not busy)
216 with m
.State("INSN_START"):
217 comb
+= core_ivalid_i
.eq(1) # instruction is valid
218 comb
+= core_issue_i
.eq(1) # and issued
221 m
.next
= "INSN_ACTIVE" # move to "wait completion"
223 # instruction started: must wait till it finishes
224 with m
.State("INSN_ACTIVE"):
225 with m
.If(insn_type
!= MicrOp
.OP_NOP
):
226 comb
+= core_ivalid_i
.eq(1) # instruction is valid
227 with m
.If(self
.state_nia
.wen
):
228 sync
+= pc_changed
.eq(1)
229 with m
.If(~core_busy_o
): # instruction done!
230 # ok here we are not reading the branch unit. TODO
231 # this just blithely overwrites whatever pipeline
233 with m
.If(~pc_changed
):
234 sync
+= self
.state_w_pc
.wen
.eq(1<<StateRegs
.PC
)
235 sync
+= self
.state_w_pc
.data_i
.eq(nia
)
237 m
.next
= "IDLE" # back to idle
239 # this bit doesn't have to be in the FSM: connect up to read
240 # regfiles on demand from DMI
242 with m
.If(d_reg
.req
): # request for regfile access being made
243 # TODO: error-check this
244 # XXX should this be combinatorial? sync better?
246 comb
+= self
.int_r
.ren
.eq(1<<d_reg
.addr
)
248 comb
+= self
.int_r
.addr
.eq(d_reg
.addr
)
249 comb
+= self
.int_r
.ren
.eq(1)
250 comb
+= d_reg
.data
.eq(self
.int_r
.data_o
)
251 comb
+= d_reg
.ack
.eq(1)
256 yield from self
.pc_i
.ports()
259 yield from self
.core
.ports()
260 yield from self
.imem
.ports()
261 yield self
.core_bigendian_i
267 def external_ports(self
):
268 return self
.pc_i
.ports() + [self
.pc_o
,
270 self
.core_bigendian_i
,
275 list(self
.dbg
.dmi
.ports()) + \
276 list(self
.imem
.ibus
.fields
.values()) + \
277 list(self
.core
.l0
.cmpi
.lsmem
.lsi
.dbus
.fields
.values())
283 if __name__
== '__main__':
284 units
= {'alu': 1, 'cr': 1, 'branch': 1, 'trap': 1, 'logical': 1,
290 pspec
= TestMemPspec(ldst_ifacetype
='bare_wb',
291 imem_ifacetype
='bare_wb',
296 dut
= TestIssuer(pspec
)
297 vl
= main(dut
, ports
=dut
.ports(), name
="test_issuer")
299 if len(sys
.argv
) == 1:
300 vl
= rtlil
.convert(dut
, ports
=dut
.external_ports(), name
="test_issuer")
301 with
open("test_issuer.il", "w") as f
: