3 not in any way intended for production use. this runs a FSM that:
5 * reads the Program Counter from StateRegs
6 * reads an instruction from a fixed-size Test Memory
7 * issues it to the Simple Core
8 * waits for it to complete
10 * does it all over again
12 the purpose of this module is to verify the functional correctness
13 of the Function Units in the absolute simplest and clearest possible
14 way, and to at provide something that can be further incrementally
18 from nmigen
import (Elaboratable
, Module
, Signal
, ClockSignal
, ResetSignal
,
19 ClockDomain
, DomainRenamer
, Mux
, Const
, Repl
, Cat
)
20 from nmigen
.cli
import rtlil
21 from nmigen
.cli
import main
24 from nmutil
.singlepipe
import ControlBase
25 from soc
.simple
.core_data
import FetchOutput
, FetchInput
27 from nmigen
.lib
.coding
import PriorityEncoder
29 from openpower
.decoder
.power_decoder
import create_pdecode
30 from openpower
.decoder
.power_decoder2
import PowerDecode2
, SVP64PrefixDecoder
31 from openpower
.decoder
.decode2execute1
import IssuerDecode2ToOperand
32 from openpower
.decoder
.decode2execute1
import Data
33 from openpower
.decoder
.power_enums
import (MicrOp
, SVP64PredInt
, SVP64PredCR
,
35 from openpower
.state
import CoreState
36 from openpower
.consts
import (CR
, SVP64CROffs
, MSR
)
37 from soc
.experiment
.testmem
import TestMemory
# test only for instructions
38 from soc
.regfile
.regfiles
import StateRegs
, FastRegs
39 from soc
.simple
.core
import NonProductionCore
40 from soc
.config
.test
.test_loadstore
import TestMemPspec
41 from soc
.config
.ifetch
import ConfigFetchUnit
42 from soc
.debug
.dmi
import CoreDebug
, DMIInterface
43 from soc
.debug
.jtag
import JTAG
44 from soc
.config
.pinouts
import get_pinspecs
45 from soc
.interrupts
.xics
import XICS_ICP
, XICS_ICS
46 from soc
.bus
.simple_gpio
import SimpleGPIO
47 from soc
.bus
.SPBlock512W64B8W
import SPBlock512W64B8W
48 from soc
.clock
.select
import ClockSelect
49 from soc
.clock
.dummypll
import DummyPLL
50 from openpower
.sv
.svstate
import SVSTATERec
51 from soc
.experiment
.icache
import ICache
53 from nmutil
.util
import rising_edge
56 def get_insn(f_instr_o
, pc
):
57 if f_instr_o
.width
== 32:
60 # 64-bit: bit 2 of pc decides which word to select
61 return f_instr_o
.word_select(pc
[2], 32)
63 # gets state input or reads from state regfile
66 def state_get(m
, res
, core_rst
, state_i
, name
, regfile
, regnum
):
69 # read the {insert state variable here}
70 res_ok_delay
= Signal(name
="%s_ok_delay" % name
)
72 sync
+= res_ok_delay
.eq(~state_i
.ok
)
73 with m
.If(state_i
.ok
):
74 # incoming override (start from pc_i)
75 comb
+= res
.eq(state_i
.data
)
77 # otherwise read StateRegs regfile for {insert state here}...
78 comb
+= regfile
.ren
.eq(1 << regnum
)
79 # ... but on a 1-clock delay
80 with m
.If(res_ok_delay
):
81 comb
+= res
.eq(regfile
.o_data
)
84 def get_predint(m
, mask
, name
):
85 """decode SVP64 predicate integer mask field to reg number and invert
86 this is identical to the equivalent function in ISACaller except that
87 it doesn't read the INT directly, it just decodes "what needs to be done"
88 i.e. which INT reg, whether it is shifted and whether it is bit-inverted.
90 * all1s is set to indicate that no mask is to be applied.
91 * regread indicates the GPR register number to be read
92 * invert is set to indicate that the register value is to be inverted
93 * unary indicates that the contents of the register is to be shifted 1<<r3
96 regread
= Signal(5, name
=name
+"regread")
97 invert
= Signal(name
=name
+"invert")
98 unary
= Signal(name
=name
+"unary")
99 all1s
= Signal(name
=name
+"all1s")
101 with m
.Case(SVP64PredInt
.ALWAYS
.value
):
102 comb
+= all1s
.eq(1) # use 0b1111 (all ones)
103 with m
.Case(SVP64PredInt
.R3_UNARY
.value
):
104 comb
+= regread
.eq(3)
105 comb
+= unary
.eq(1) # 1<<r3 - shift r3 (single bit)
106 with m
.Case(SVP64PredInt
.R3
.value
):
107 comb
+= regread
.eq(3)
108 with m
.Case(SVP64PredInt
.R3_N
.value
):
109 comb
+= regread
.eq(3)
111 with m
.Case(SVP64PredInt
.R10
.value
):
112 comb
+= regread
.eq(10)
113 with m
.Case(SVP64PredInt
.R10_N
.value
):
114 comb
+= regread
.eq(10)
116 with m
.Case(SVP64PredInt
.R30
.value
):
117 comb
+= regread
.eq(30)
118 with m
.Case(SVP64PredInt
.R30_N
.value
):
119 comb
+= regread
.eq(30)
121 return regread
, invert
, unary
, all1s
124 def get_predcr(m
, mask
, name
):
125 """decode SVP64 predicate CR to reg number field and invert status
126 this is identical to _get_predcr in ISACaller
129 idx
= Signal(2, name
=name
+"idx")
130 invert
= Signal(name
=name
+"crinvert")
132 with m
.Case(SVP64PredCR
.LT
.value
):
133 comb
+= idx
.eq(CR
.LT
)
135 with m
.Case(SVP64PredCR
.GE
.value
):
136 comb
+= idx
.eq(CR
.LT
)
138 with m
.Case(SVP64PredCR
.GT
.value
):
139 comb
+= idx
.eq(CR
.GT
)
141 with m
.Case(SVP64PredCR
.LE
.value
):
142 comb
+= idx
.eq(CR
.GT
)
144 with m
.Case(SVP64PredCR
.EQ
.value
):
145 comb
+= idx
.eq(CR
.EQ
)
147 with m
.Case(SVP64PredCR
.NE
.value
):
148 comb
+= idx
.eq(CR
.EQ
)
150 with m
.Case(SVP64PredCR
.SO
.value
):
151 comb
+= idx
.eq(CR
.SO
)
153 with m
.Case(SVP64PredCR
.NS
.value
):
154 comb
+= idx
.eq(CR
.SO
)
159 class TestIssuerBase(Elaboratable
):
160 """TestIssuerBase - common base class for Issuers
162 takes care of power-on reset, peripherals, debug, DEC/TB,
163 and gets PC/MSR/SVSTATE from the State Regfile etc.
166 def __init__(self
, pspec
):
168 # test if microwatt compatibility is to be enabled
169 self
.microwatt_compat
= (hasattr(pspec
, "microwatt_compat") and
170 (pspec
.microwatt_compat
== True))
171 self
.alt_reset
= Signal(reset_less
=True) # not connected yet (microwatt)
173 # test is SVP64 is to be enabled
174 self
.svp64_en
= hasattr(pspec
, "svp64") and (pspec
.svp64
== True)
176 # and if regfiles are reduced
177 self
.regreduce_en
= (hasattr(pspec
, "regreduce") and
178 (pspec
.regreduce
== True))
180 # and if overlap requested
181 self
.allow_overlap
= (hasattr(pspec
, "allow_overlap") and
182 (pspec
.allow_overlap
== True))
184 # and get the core domain
185 self
.core_domain
= "coresync"
186 if (hasattr(pspec
, "core_domain") and
187 isinstance(pspec
.core_domain
, str)):
188 self
.core_domain
= pspec
.core_domain
190 # JTAG interface. add this right at the start because if it's
191 # added it *modifies* the pspec, by adding enable/disable signals
192 # for parts of the rest of the core
193 self
.jtag_en
= hasattr(pspec
, "debug") and pspec
.debug
== 'jtag'
194 #self.dbg_domain = "sync" # sigh "dbgsunc" too problematic
195 self
.dbg_domain
= "dbgsync" # domain for DMI/JTAG clock
197 # XXX MUST keep this up-to-date with litex, and
198 # soc-cocotb-sim, and err.. all needs sorting out, argh
201 'eint', 'gpio', 'mspi0',
202 # 'mspi1', - disabled for now
203 # 'pwm', 'sd0', - disabled for now
205 self
.jtag
= JTAG(get_pinspecs(subset
=subset
),
206 domain
=self
.dbg_domain
)
207 # add signals to pspec to enable/disable icache and dcache
208 # (or data and intstruction wishbone if icache/dcache not included)
209 # https://bugs.libre-soc.org/show_bug.cgi?id=520
210 # TODO: do we actually care if these are not domain-synchronised?
211 # honestly probably not.
212 pspec
.wb_icache_en
= self
.jtag
.wb_icache_en
213 pspec
.wb_dcache_en
= self
.jtag
.wb_dcache_en
214 self
.wb_sram_en
= self
.jtag
.wb_sram_en
216 self
.wb_sram_en
= Const(1)
218 # add 4k sram blocks?
219 self
.sram4x4k
= (hasattr(pspec
, "sram4x4kblock") and
220 pspec
.sram4x4kblock
== True)
224 self
.sram4k
.append(SPBlock512W64B8W(name
="sram4k_%d" % i
,
228 # add interrupt controller?
229 self
.xics
= hasattr(pspec
, "xics") and pspec
.xics
== True
231 self
.xics_icp
= XICS_ICP()
232 self
.xics_ics
= XICS_ICS()
233 self
.int_level_i
= self
.xics_ics
.int_level_i
235 self
.ext_irq
= Signal()
237 # add GPIO peripheral?
238 self
.gpio
= hasattr(pspec
, "gpio") and pspec
.gpio
== True
240 self
.simple_gpio
= SimpleGPIO()
241 self
.gpio_o
= self
.simple_gpio
.gpio_o
243 # main instruction core. suitable for prototyping / demo only
244 self
.core
= core
= NonProductionCore(pspec
)
245 self
.core_rst
= ResetSignal(self
.core_domain
)
247 # instruction decoder. goes into Trap Record
248 #pdecode = create_pdecode()
249 self
.cur_state
= CoreState("cur") # current state (MSR/PC/SVSTATE)
250 self
.pdecode2
= PowerDecode2(None, state
=self
.cur_state
,
251 opkls
=IssuerDecode2ToOperand
,
252 svp64_en
=self
.svp64_en
,
253 regreduce_en
=self
.regreduce_en
)
254 pdecode
= self
.pdecode2
.dec
257 self
.svp64
= SVP64PrefixDecoder() # for decoding SVP64 prefix
259 self
.update_svstate
= Signal() # set this if updating svstate
260 self
.new_svstate
= new_svstate
= SVSTATERec("new_svstate")
262 # Test Instruction memory
263 if hasattr(core
, "icache"):
264 # XXX BLECH! use pspec to transfer the I-Cache to ConfigFetchUnit
265 # truly dreadful. needs a huge reorg.
266 pspec
.icache
= core
.icache
267 self
.imem
= ConfigFetchUnit(pspec
).fu
270 self
.dbg
= CoreDebug()
271 self
.dbg_rst_i
= Signal(reset_less
=True)
273 # instruction go/monitor
274 self
.pc_o
= Signal(64, reset_less
=True)
275 self
.pc_i
= Data(64, "pc_i") # set "ok" to indicate "please change me"
276 self
.msr_i
= Data(64, "msr_i") # set "ok" to indicate "please change me"
277 self
.svstate_i
= Data(64, "svstate_i") # ditto
278 self
.core_bigendian_i
= Signal() # TODO: set based on MSR.LE
279 self
.busy_o
= Signal(reset_less
=True)
280 self
.memerr_o
= Signal(reset_less
=True)
282 # STATE regfile read /write ports for PC, MSR, SVSTATE
283 staterf
= self
.core
.regs
.rf
['state']
284 self
.state_r_msr
= staterf
.r_ports
['msr'] # MSR rd
285 self
.state_r_pc
= staterf
.r_ports
['cia'] # PC rd
286 self
.state_r_sv
= staterf
.r_ports
['sv'] # SVSTATE rd
288 self
.state_w_msr
= staterf
.w_ports
['d_wr2'] # MSR wr
289 self
.state_w_pc
= staterf
.w_ports
['d_wr1'] # PC wr
290 self
.state_w_sv
= staterf
.w_ports
['sv'] # SVSTATE wr
292 # DMI interface access
293 intrf
= self
.core
.regs
.rf
['int']
294 crrf
= self
.core
.regs
.rf
['cr']
295 xerrf
= self
.core
.regs
.rf
['xer']
296 self
.int_r
= intrf
.r_ports
['dmi'] # INT read
297 self
.cr_r
= crrf
.r_ports
['full_cr_dbg'] # CR read
298 self
.xer_r
= xerrf
.r_ports
['full_xer'] # XER read
302 self
.int_pred
= intrf
.r_ports
['pred'] # INT predicate read
303 self
.cr_pred
= crrf
.r_ports
['cr_pred'] # CR predicate read
305 # hack method of keeping an eye on whether branch/trap set the PC
306 self
.state_nia
= self
.core
.regs
.rf
['state'].w_ports
['nia']
307 self
.state_nia
.wen
.name
= 'state_nia_wen'
309 # pulse to synchronize the simulator at instruction end
310 self
.insn_done
= Signal()
312 # indicate any instruction still outstanding, in execution
313 self
.any_busy
= Signal()
316 # store copies of predicate masks
317 self
.srcmask
= Signal(64)
318 self
.dstmask
= Signal(64)
320 # sigh, the wishbone addresses are not wishbone-compliant in microwatt
321 if self
.microwatt_compat
:
322 self
.ibus_adr
= Signal(32, name
='wishbone_insn_out.adr')
323 self
.dbus_adr
= Signal(32, name
='wishbone_data_out.adr')
325 # add an output of the PC and instruction, and whether it was requested
326 # this is for verilator debug purposes
327 if self
.microwatt_compat
:
328 self
.nia
= Signal(64)
329 self
.msr_o
= Signal(64)
330 self
.nia_req
= Signal(1)
331 self
.insn
= Signal(32)
332 self
.ldst_req
= Signal(1)
333 self
.ldst_addr
= Signal(1)
335 # for pausing dec/tb during an SPR pipeline event, this
336 # ensures that an SPR write (mtspr) to TB or DEC does not
337 # get overwritten by the DEC/TB FSM
338 self
.pause_dec_tb
= Signal()
340 def setup_peripherals(self
, m
):
341 comb
, sync
= m
.d
.comb
, m
.d
.sync
343 # okaaaay so the debug module must be in coresync clock domain
344 # but NOT its reset signal. to cope with this, set every single
345 # submodule explicitly in coresync domain, debug and JTAG
346 # in their own one but using *external* reset.
347 csd
= DomainRenamer(self
.core_domain
)
348 dbd
= DomainRenamer(self
.dbg_domain
)
350 if self
.microwatt_compat
:
351 m
.submodules
.core
= core
= self
.core
353 m
.submodules
.core
= core
= csd(self
.core
)
355 # this _so_ needs sorting out. ICache is added down inside
356 # LoadStore1 and is already a submodule of LoadStore1
357 if not isinstance(self
.imem
, ICache
):
358 m
.submodules
.imem
= imem
= csd(self
.imem
)
360 # set up JTAG Debug Module (in correct domain)
361 m
.submodules
.dbg
= dbg
= dbd(self
.dbg
)
363 m
.submodules
.jtag
= jtag
= dbd(self
.jtag
)
364 # TODO: UART2GDB mux, here, from external pin
365 # see https://bugs.libre-soc.org/show_bug.cgi?id=499
366 sync
+= dbg
.dmi
.connect_to(jtag
.dmi
)
368 # fixup the clocks in microwatt-compat mode (but leave resets alone
369 # so that microwatt soc.vhdl can pull a reset on the core or DMI
370 # can do it, just like in TestIssuer)
371 if self
.microwatt_compat
:
372 intclk
= ClockSignal(self
.core_domain
)
373 dbgclk
= ClockSignal(self
.dbg_domain
)
374 if self
.core_domain
!= 'sync':
375 comb
+= intclk
.eq(ClockSignal())
376 if self
.dbg_domain
!= 'sync':
377 comb
+= dbgclk
.eq(ClockSignal())
379 # drop the first 3 bits of the incoming wishbone addresses
380 # this can go if using later versions of microwatt (not now)
381 if self
.microwatt_compat
:
382 ibus
= self
.imem
.ibus
383 dbus
= self
.core
.l0
.cmpi
.wb_bus()
384 comb
+= self
.ibus_adr
.eq(Cat(Const(0, 3), ibus
.adr
))
385 comb
+= self
.dbus_adr
.eq(Cat(Const(0, 3), dbus
.adr
))
386 # microwatt verilator debug purposes
387 pi
= self
.core
.l0
.cmpi
.pi
.pi
388 comb
+= self
.ldst_req
.eq(pi
.addr_ok_o
)
389 comb
+= self
.ldst_addr
.eq(pi
.addr
)
391 cur_state
= self
.cur_state
393 # 4x 4k SRAM blocks. these simply "exist", they get routed in litex
395 for i
, sram
in enumerate(self
.sram4k
):
396 m
.submodules
["sram4k_%d" % i
] = csd(sram
)
397 comb
+= sram
.enable
.eq(self
.wb_sram_en
)
399 # XICS interrupt handler
401 m
.submodules
.xics_icp
= icp
= csd(self
.xics_icp
)
402 m
.submodules
.xics_ics
= ics
= csd(self
.xics_ics
)
403 comb
+= icp
.ics_i
.eq(ics
.icp_o
) # connect ICS to ICP
404 sync
+= cur_state
.eint
.eq(icp
.core_irq_o
) # connect ICP to core
406 sync
+= cur_state
.eint
.eq(self
.ext_irq
) # connect externally
408 # GPIO test peripheral
410 m
.submodules
.simple_gpio
= simple_gpio
= csd(self
.simple_gpio
)
412 # connect one GPIO output to ICS bit 15 (like in microwatt soc.vhdl)
413 # XXX causes litex ECP5 test to get wrong idea about input and output
414 # (but works with verilator sim *sigh*)
415 # if self.gpio and self.xics:
416 # comb += self.int_level_i[15].eq(simple_gpio.gpio_o[0])
418 # instruction decoder
419 pdecode
= create_pdecode()
420 m
.submodules
.dec2
= pdecode2
= csd(self
.pdecode2
)
422 m
.submodules
.svp64
= svp64
= csd(self
.svp64
)
425 dmi
, d_reg
, d_cr
, d_xer
, = dbg
.dmi
, dbg
.d_gpr
, dbg
.d_cr
, dbg
.d_xer
426 intrf
= self
.core
.regs
.rf
['int']
428 # clock delay power-on reset
429 cd_por
= ClockDomain(reset_less
=True)
430 cd_sync
= ClockDomain()
431 m
.domains
+= cd_por
, cd_sync
432 core_sync
= ClockDomain(self
.core_domain
)
433 if self
.core_domain
!= "sync":
434 m
.domains
+= core_sync
435 if self
.dbg_domain
!= "sync":
436 dbg_sync
= ClockDomain(self
.dbg_domain
)
437 m
.domains
+= dbg_sync
439 ti_rst
= Signal(reset_less
=True)
440 delay
= Signal(range(4), reset
=3)
441 with m
.If(delay
!= 0):
442 m
.d
.por
+= delay
.eq(delay
- 1)
443 comb
+= cd_por
.clk
.eq(ClockSignal())
445 # power-on reset delay
446 core_rst
= ResetSignal(self
.core_domain
)
447 if self
.core_domain
!= "sync":
448 comb
+= ti_rst
.eq(delay
!= 0 | dbg
.core_rst_o |
ResetSignal())
449 comb
+= core_rst
.eq(ti_rst
)
451 with m
.If(delay
!= 0 | dbg
.core_rst_o
):
452 comb
+= core_rst
.eq(1)
454 # connect external reset signal to DMI Reset
455 if self
.dbg_domain
!= "sync":
456 dbg_rst
= ResetSignal(self
.dbg_domain
)
457 comb
+= dbg_rst
.eq(self
.dbg_rst_i
)
459 # busy/halted signals from core
460 core_busy_o
= ~core
.p
.o_ready | core
.n
.o_data
.busy_o
# core is busy
461 comb
+= self
.busy_o
.eq(core_busy_o
)
462 comb
+= pdecode2
.dec
.bigendian
.eq(self
.core_bigendian_i
)
464 # temporary hack: says "go" immediately for both address gen and ST
466 ldst
= core
.fus
.fus
['ldst0']
467 st_go_edge
= rising_edge(m
, ldst
.st
.rel_o
)
468 # link addr-go direct to rel
469 m
.d
.comb
+= ldst
.ad
.go_i
.eq(ldst
.ad
.rel_o
)
470 m
.d
.comb
+= ldst
.st
.go_i
.eq(st_go_edge
) # link store-go to rising rel
472 def do_dmi(self
, m
, dbg
):
473 """deals with DMI debug requests
475 currently only provides read requests for the INT regfile, CR and XER
476 it will later also deal with *writing* to these regfiles.
480 dmi
, d_reg
, d_cr
, d_xer
, = dbg
.dmi
, dbg
.d_gpr
, dbg
.d_cr
, dbg
.d_xer
481 intrf
= self
.core
.regs
.rf
['int']
483 with m
.If(d_reg
.req
): # request for regfile access being made
484 # TODO: error-check this
485 # XXX should this be combinatorial? sync better?
487 comb
+= self
.int_r
.ren
.eq(1 << d_reg
.addr
)
489 comb
+= self
.int_r
.addr
.eq(d_reg
.addr
)
490 comb
+= self
.int_r
.ren
.eq(1)
491 d_reg_delay
= Signal()
492 sync
+= d_reg_delay
.eq(d_reg
.req
)
493 with m
.If(d_reg_delay
):
494 # data arrives one clock later
495 comb
+= d_reg
.data
.eq(self
.int_r
.o_data
)
496 comb
+= d_reg
.ack
.eq(1)
498 # sigh same thing for CR debug
499 with m
.If(d_cr
.req
): # request for regfile access being made
500 comb
+= self
.cr_r
.ren
.eq(0b11111111) # enable all
501 d_cr_delay
= Signal()
502 sync
+= d_cr_delay
.eq(d_cr
.req
)
503 with m
.If(d_cr_delay
):
504 # data arrives one clock later
505 comb
+= d_cr
.data
.eq(self
.cr_r
.o_data
)
506 comb
+= d_cr
.ack
.eq(1)
509 with m
.If(d_xer
.req
): # request for regfile access being made
510 comb
+= self
.xer_r
.ren
.eq(0b111111) # enable all
511 d_xer_delay
= Signal()
512 sync
+= d_xer_delay
.eq(d_xer
.req
)
513 with m
.If(d_xer_delay
):
514 # data arrives one clock later
515 comb
+= d_xer
.data
.eq(self
.xer_r
.o_data
)
516 comb
+= d_xer
.ack
.eq(1)
518 def tb_dec_fsm(self
, m
, spr_dec
):
521 this is a FSM for updating either dec or tb. it runs alternately
522 DEC, TB, DEC, TB. note that SPR pipeline could have written a new
523 value to DEC, however the regfile has "passthrough" on it so this
526 see v3.0B p1097-1099 for Timeer Resource and p1065 and p1076
529 comb
, sync
= m
.d
.comb
, m
.d
.sync
530 fast_rf
= self
.core
.regs
.rf
['fast']
531 fast_r_dectb
= fast_rf
.r_ports
['issue'] # DEC/TB
532 fast_w_dectb
= fast_rf
.w_ports
['issue'] # DEC/TB
536 # initiates read of current DEC
537 with m
.State("DEC_READ"):
538 comb
+= fast_r_dectb
.addr
.eq(FastRegs
.DEC
)
539 comb
+= fast_r_dectb
.ren
.eq(1)
540 with m
.If(~self
.pause_dec_tb
):
543 # waits for DEC read to arrive (1 cycle), updates with new value
544 # respects if dec/tb writing has been paused
545 with m
.State("DEC_WRITE"):
546 with m
.If(self
.pause_dec_tb
):
547 # if paused, return to reading
551 # TODO: MSR.LPCR 32-bit decrement mode
552 comb
+= new_dec
.eq(fast_r_dectb
.o_data
- 1)
553 comb
+= fast_w_dectb
.addr
.eq(FastRegs
.DEC
)
554 comb
+= fast_w_dectb
.wen
.eq(1)
555 comb
+= fast_w_dectb
.i_data
.eq(new_dec
)
556 # copy to cur_state for decoder, for an interrupt
557 sync
+= spr_dec
.eq(new_dec
)
560 # initiates read of current TB
561 with m
.State("TB_READ"):
562 comb
+= fast_r_dectb
.addr
.eq(FastRegs
.TB
)
563 comb
+= fast_r_dectb
.ren
.eq(1)
564 with m
.If(~self
.pause_dec_tb
):
567 # waits for read TB to arrive, initiates write of current TB
568 # respects if dec/tb writing has been paused
569 with m
.State("TB_WRITE"):
570 with m
.If(self
.pause_dec_tb
):
571 # if paused, return to reading
575 comb
+= new_tb
.eq(fast_r_dectb
.o_data
+ 1)
576 comb
+= fast_w_dectb
.addr
.eq(FastRegs
.TB
)
577 comb
+= fast_w_dectb
.wen
.eq(1)
578 comb
+= fast_w_dectb
.i_data
.eq(new_tb
)
583 def elaborate(self
, platform
):
586 comb
, sync
= m
.d
.comb
, m
.d
.sync
587 cur_state
= self
.cur_state
588 pdecode2
= self
.pdecode2
591 # set up peripherals and core
592 core_rst
= self
.core_rst
593 self
.setup_peripherals(m
)
595 # reset current state if core reset requested
597 m
.d
.sync
+= self
.cur_state
.eq(0)
599 # check halted condition: requested PC to execute matches DMI stop addr
600 # and immediately stop. address of 0xffff_ffff_ffff_ffff can never
603 comb
+= halted
.eq(dbg
.stop_addr_o
== dbg
.state
.pc
)
605 comb
+= dbg
.core_stopped_i
.eq(1)
606 comb
+= dbg
.terminate_i
.eq(1)
608 # PC and instruction from I-Memory
609 comb
+= self
.pc_o
.eq(cur_state
.pc
)
610 self
.pc_changed
= Signal() # note write to PC
611 self
.msr_changed
= Signal() # note write to MSR
612 self
.sv_changed
= Signal() # note write to SVSTATE
614 # read state either from incoming override or from regfile
615 state
= CoreState("get") # current state (MSR/PC/SVSTATE)
616 state_get(m
, state
.msr
, core_rst
, self
.msr_i
,
618 self
.state_r_msr
, StateRegs
.MSR
)
619 state_get(m
, state
.pc
, core_rst
, self
.pc_i
,
621 self
.state_r_pc
, StateRegs
.PC
)
622 state_get(m
, state
.svstate
, core_rst
, self
.svstate_i
,
623 "svstate", # read SVSTATE
624 self
.state_r_sv
, StateRegs
.SVSTATE
)
626 # don't write pc every cycle
627 comb
+= self
.state_w_pc
.wen
.eq(0)
628 comb
+= self
.state_w_pc
.i_data
.eq(0)
630 # connect up debug state. note "combinatorially same" below,
631 # this is a bit naff, passing state over in the dbg class, but
632 # because it is combinatorial it achieves the desired goal
633 comb
+= dbg
.state
.eq(state
)
635 # this bit doesn't have to be in the FSM: connect up to read
636 # regfiles on demand from DMI
639 # DEC and TB inc/dec FSM. copy of DEC is put into CoreState,
640 # (which uses that in PowerDecoder2 to raise 0x900 exception)
641 self
.tb_dec_fsm(m
, cur_state
.dec
)
643 # while stopped, allow updating the MSR, PC and SVSTATE.
644 # these are mainly for debugging purposes (including DMI/JTAG)
645 with m
.If(dbg
.core_stopped_i
):
646 with m
.If(self
.pc_i
.ok
):
647 comb
+= self
.state_w_pc
.wen
.eq(1 << StateRegs
.PC
)
648 comb
+= self
.state_w_pc
.i_data
.eq(self
.pc_i
.data
)
649 sync
+= self
.pc_changed
.eq(1)
650 with m
.If(self
.msr_i
.ok
):
651 comb
+= self
.state_w_msr
.wen
.eq(1 << StateRegs
.MSR
)
652 comb
+= self
.state_w_msr
.i_data
.eq(self
.msr_i
.data
)
653 sync
+= self
.msr_changed
.eq(1)
654 with m
.If(self
.svstate_i
.ok | self
.update_svstate
):
655 with m
.If(self
.svstate_i
.ok
): # over-ride from external source
656 comb
+= self
.new_svstate
.eq(self
.svstate_i
.data
)
657 comb
+= self
.state_w_sv
.wen
.eq(1 << StateRegs
.SVSTATE
)
658 comb
+= self
.state_w_sv
.i_data
.eq(self
.new_svstate
)
659 sync
+= self
.sv_changed
.eq(1)
661 # start renaming some of the ports to match microwatt
662 if self
.microwatt_compat
:
663 self
.core
.o
.core_terminate_o
.name
= "terminated_out"
664 # names of DMI interface
665 self
.dbg
.dmi
.addr_i
.name
= 'dmi_addr'
666 self
.dbg
.dmi
.din
.name
= 'dmi_din'
667 self
.dbg
.dmi
.dout
.name
= 'dmi_dout'
668 self
.dbg
.dmi
.req_i
.name
= 'dmi_req'
669 self
.dbg
.dmi
.we_i
.name
= 'dmi_wr'
670 self
.dbg
.dmi
.ack_o
.name
= 'dmi_ack'
671 # wishbone instruction bus
672 ibus
= self
.imem
.ibus
673 ibus
.adr
.name
= 'wishbone_insn_out.adr'
674 ibus
.dat_w
.name
= 'wishbone_insn_out.dat'
675 ibus
.sel
.name
= 'wishbone_insn_out.sel'
676 ibus
.cyc
.name
= 'wishbone_insn_out.cyc'
677 ibus
.stb
.name
= 'wishbone_insn_out.stb'
678 ibus
.we
.name
= 'wishbone_insn_out.we'
679 ibus
.dat_r
.name
= 'wishbone_insn_in.dat'
680 ibus
.ack
.name
= 'wishbone_insn_in.ack'
681 ibus
.stall
.name
= 'wishbone_insn_in.stall'
683 dbus
= self
.core
.l0
.cmpi
.wb_bus()
684 dbus
.adr
.name
= 'wishbone_data_out.adr'
685 dbus
.dat_w
.name
= 'wishbone_data_out.dat'
686 dbus
.sel
.name
= 'wishbone_data_out.sel'
687 dbus
.cyc
.name
= 'wishbone_data_out.cyc'
688 dbus
.stb
.name
= 'wishbone_data_out.stb'
689 dbus
.we
.name
= 'wishbone_data_out.we'
690 dbus
.dat_r
.name
= 'wishbone_data_in.dat'
691 dbus
.ack
.name
= 'wishbone_data_in.ack'
692 dbus
.stall
.name
= 'wishbone_data_in.stall'
697 yield from self
.pc_i
.ports()
698 yield from self
.msr_i
.ports()
701 yield from self
.core
.ports()
702 yield from self
.imem
.ports()
703 yield self
.core_bigendian_i
709 def external_ports(self
):
710 if self
.microwatt_compat
:
711 ports
= [self
.core
.o
.core_terminate_o
,
713 self
.alt_reset
, # not connected yet
714 self
.nia
, self
.insn
, self
.nia_req
, self
.msr_o
,
715 self
.ldst_req
, self
.ldst_addr
,
719 ports
+= list(self
.dbg
.dmi
.ports())
720 # for dbus/ibus microwatt, exclude err btw and cti
721 for name
, sig
in self
.imem
.ibus
.fields
.items():
722 if name
not in ['err', 'bte', 'cti', 'adr']:
724 for name
, sig
in self
.core
.l0
.cmpi
.wb_bus().fields
.items():
725 if name
not in ['err', 'bte', 'cti', 'adr']:
727 # microwatt non-compliant with wishbone
728 ports
.append(self
.ibus_adr
)
729 ports
.append(self
.dbus_adr
)
732 ports
= self
.pc_i
.ports()
733 ports
= self
.msr_i
.ports()
734 ports
+= [self
.pc_o
, self
.memerr_o
, self
.core_bigendian_i
, self
.busy_o
,
738 ports
+= list(self
.jtag
.external_ports())
740 # don't add DMI if JTAG is enabled
741 ports
+= list(self
.dbg
.dmi
.ports())
743 ports
+= list(self
.imem
.ibus
.fields
.values())
744 ports
+= list(self
.core
.l0
.cmpi
.wb_bus().fields
.values())
747 for sram
in self
.sram4k
:
748 ports
+= list(sram
.bus
.fields
.values())
751 ports
+= list(self
.xics_icp
.bus
.fields
.values())
752 ports
+= list(self
.xics_ics
.bus
.fields
.values())
753 ports
.append(self
.int_level_i
)
755 ports
.append(self
.ext_irq
)
758 ports
+= list(self
.simple_gpio
.bus
.fields
.values())
759 ports
.append(self
.gpio_o
)
767 class TestIssuerInternal(TestIssuerBase
):
768 """TestIssuer - reads instructions from TestMemory and issues them
770 efficiency and speed is not the main goal here: functional correctness
771 and code clarity is. optimisations (which almost 100% interfere with
772 easy understanding) come later.
775 def fetch_fsm(self
, m
, dbg
, core
, pc
, msr
, svstate
, nia
, is_svp64_mode
,
776 fetch_pc_o_ready
, fetch_pc_i_valid
,
777 fetch_insn_o_valid
, fetch_insn_i_ready
):
780 this FSM performs fetch of raw instruction data, partial-decodes
781 it 32-bit at a time to detect SVP64 prefixes, and will optionally
782 read a 2nd 32-bit quantity if that occurs.
786 pdecode2
= self
.pdecode2
787 cur_state
= self
.cur_state
788 dec_opcode_i
= pdecode2
.dec
.raw_opcode_in
# raw opcode
790 # also note instruction fetch failed
791 if hasattr(core
, "icache"):
792 fetch_failed
= core
.icache
.i_out
.fetch_failed
795 fetch_failed
= Const(0, 1)
798 # set priv / virt mode on I-Cache, sigh
799 if isinstance(self
.imem
, ICache
):
800 comb
+= self
.imem
.i_in
.priv_mode
.eq(~msr
[MSR
.PR
])
801 comb
+= self
.imem
.i_in
.virt_mode
.eq(msr
[MSR
.IR
]) # Instr. Redir (VM)
803 with m
.FSM(name
='fetch_fsm'):
806 with m
.State("IDLE"):
807 # fetch allowed if not failed and stopped but not stepping
808 # (see dmi.py for how core_stop_o is generated)
809 with m
.If(~fetch_failed
& ~dbg
.core_stop_o
):
810 comb
+= fetch_pc_o_ready
.eq(1)
811 with m
.If(fetch_pc_i_valid
& ~pdecode2
.instr_fault
813 # instruction allowed to go: start by reading the PC
814 # capture the PC and also drop it into Insn Memory
815 # we have joined a pair of combinatorial memory
816 # lookups together. this is Generally Bad.
817 comb
+= self
.imem
.a_pc_i
.eq(pc
)
818 comb
+= self
.imem
.a_i_valid
.eq(1)
819 comb
+= self
.imem
.f_i_valid
.eq(1)
820 # transfer state to output
821 sync
+= cur_state
.pc
.eq(pc
)
822 sync
+= cur_state
.svstate
.eq(svstate
) # and svstate
823 sync
+= cur_state
.msr
.eq(msr
) # and msr
825 m
.next
= "INSN_READ" # move to "wait for bus" phase
827 # dummy pause to find out why simulation is not keeping up
828 with m
.State("INSN_READ"):
829 # when using "single-step" mode, checking dbg.stopping_o
830 # prevents progress. allow fetch to proceed once started
832 #if self.allow_overlap:
833 # stopping = dbg.stopping_o
835 # stopping: jump back to idle
838 with m
.If(self
.imem
.f_busy_o
&
839 ~pdecode2
.instr_fault
): # zzz...
840 # busy but not fetch failed: stay in wait-read
841 comb
+= self
.imem
.a_pc_i
.eq(pc
)
842 comb
+= self
.imem
.a_i_valid
.eq(1)
843 comb
+= self
.imem
.f_i_valid
.eq(1)
845 # not busy (or fetch failed!): instruction fetched
846 # when fetch failed, the instruction gets ignored
848 if hasattr(core
, "icache"):
849 # blech, icache returns actual instruction
850 insn
= self
.imem
.f_instr_o
852 # but these return raw memory
853 insn
= get_insn(self
.imem
.f_instr_o
, cur_state
.pc
)
856 # decode the SVP64 prefix, if any
857 comb
+= svp64
.raw_opcode_in
.eq(insn
)
858 comb
+= svp64
.bigendian
.eq(self
.core_bigendian_i
)
859 # pass the decoded prefix (if any) to PowerDecoder2
860 sync
+= pdecode2
.sv_rm
.eq(svp64
.svp64_rm
)
861 sync
+= pdecode2
.is_svp64_mode
.eq(is_svp64_mode
)
862 # remember whether this is a prefixed instruction,
863 # so the FSM can readily loop when VL==0
864 sync
+= is_svp64_mode
.eq(svp64
.is_svp64_mode
)
865 # calculate the address of the following instruction
866 insn_size
= Mux(svp64
.is_svp64_mode
, 8, 4)
867 sync
+= nia
.eq(cur_state
.pc
+ insn_size
)
868 with m
.If(~svp64
.is_svp64_mode
):
869 # with no prefix, store the instruction
870 # and hand it directly to the next FSM
871 sync
+= dec_opcode_i
.eq(insn
)
872 m
.next
= "INSN_READY"
874 # fetch the rest of the instruction from memory
875 comb
+= self
.imem
.a_pc_i
.eq(cur_state
.pc
+ 4)
876 comb
+= self
.imem
.a_i_valid
.eq(1)
877 comb
+= self
.imem
.f_i_valid
.eq(1)
878 m
.next
= "INSN_READ2"
880 # not SVP64 - 32-bit only
881 sync
+= nia
.eq(cur_state
.pc
+ 4)
882 sync
+= dec_opcode_i
.eq(insn
)
883 if self
.microwatt_compat
:
884 # for verilator debug purposes
885 comb
+= self
.insn
.eq(insn
)
886 comb
+= self
.nia
.eq(cur_state
.pc
)
887 comb
+= self
.msr_o
.eq(cur_state
.msr
)
888 comb
+= self
.nia_req
.eq(1)
889 m
.next
= "INSN_READY"
891 with m
.State("INSN_READ2"):
892 with m
.If(self
.imem
.f_busy_o
): # zzz...
893 # busy: stay in wait-read
894 comb
+= self
.imem
.a_i_valid
.eq(1)
895 comb
+= self
.imem
.f_i_valid
.eq(1)
897 # not busy: instruction fetched
898 if hasattr(core
, "icache"):
899 # blech, icache returns actual instruction
900 insn
= self
.imem
.f_instr_o
902 insn
= get_insn(self
.imem
.f_instr_o
, cur_state
.pc
+4)
903 sync
+= dec_opcode_i
.eq(insn
)
904 m
.next
= "INSN_READY"
905 # TODO: probably can start looking at pdecode2.rm_dec
906 # here or maybe even in INSN_READ state, if svp64_mode
907 # detected, in order to trigger - and wait for - the
910 pmode
= pdecode2
.rm_dec
.predmode
912 if pmode != SVP64PredMode.ALWAYS.value:
913 fire predicate loading FSM and wait before
916 sync += self.srcmask.eq(-1) # set to all 1s
917 sync += self.dstmask.eq(-1) # set to all 1s
918 m.next = "INSN_READY"
921 with m
.State("INSN_READY"):
922 # hand over the instruction, to be decoded
923 comb
+= fetch_insn_o_valid
.eq(1)
924 with m
.If(fetch_insn_i_ready
):
928 def fetch_predicate_fsm(self
, m
,
929 pred_insn_i_valid
, pred_insn_o_ready
,
930 pred_mask_o_valid
, pred_mask_i_ready
):
931 """fetch_predicate_fsm - obtains (constructs in the case of CR)
932 src/dest predicate masks
934 https://bugs.libre-soc.org/show_bug.cgi?id=617
935 the predicates can be read here, by using IntRegs r_ports['pred']
936 or CRRegs r_ports['pred']. in the case of CRs it will have to
937 be done through multiple reads, extracting one relevant at a time.
938 later, a faster way would be to use the 32-bit-wide CR port but
939 this is more complex decoding, here. equivalent code used in
940 ISACaller is "from openpower.decoder.isa.caller import get_predcr"
942 note: this ENTIRE FSM is not to be called when svp64 is disabled
946 pdecode2
= self
.pdecode2
947 rm_dec
= pdecode2
.rm_dec
# SVP64RMModeDecode
948 predmode
= rm_dec
.predmode
949 srcpred
, dstpred
= rm_dec
.srcpred
, rm_dec
.dstpred
950 cr_pred
, int_pred
= self
.cr_pred
, self
.int_pred
# read regfiles
951 # get src/dst step, so we can skip already used mask bits
952 cur_state
= self
.cur_state
953 srcstep
= cur_state
.svstate
.srcstep
954 dststep
= cur_state
.svstate
.dststep
955 cur_vl
= cur_state
.svstate
.vl
958 sregread
, sinvert
, sunary
, sall1s
= get_predint(m
, srcpred
, 's')
959 dregread
, dinvert
, dunary
, dall1s
= get_predint(m
, dstpred
, 'd')
960 sidx
, scrinvert
= get_predcr(m
, srcpred
, 's')
961 didx
, dcrinvert
= get_predcr(m
, dstpred
, 'd')
963 # store fetched masks, for either intpred or crpred
964 # when src/dst step is not zero, the skipped mask bits need to be
965 # shifted-out, before actually storing them in src/dest mask
966 new_srcmask
= Signal(64, reset_less
=True)
967 new_dstmask
= Signal(64, reset_less
=True)
969 with m
.FSM(name
="fetch_predicate"):
971 with m
.State("FETCH_PRED_IDLE"):
972 comb
+= pred_insn_o_ready
.eq(1)
973 with m
.If(pred_insn_i_valid
):
974 with m
.If(predmode
== SVP64PredMode
.INT
):
975 # skip fetching destination mask register, when zero
977 sync
+= new_dstmask
.eq(-1)
978 # directly go to fetch source mask register
979 # guaranteed not to be zero (otherwise predmode
980 # would be SVP64PredMode.ALWAYS, not INT)
981 comb
+= int_pred
.addr
.eq(sregread
)
982 comb
+= int_pred
.ren
.eq(1)
983 m
.next
= "INT_SRC_READ"
984 # fetch destination predicate register
986 comb
+= int_pred
.addr
.eq(dregread
)
987 comb
+= int_pred
.ren
.eq(1)
988 m
.next
= "INT_DST_READ"
989 with m
.Elif(predmode
== SVP64PredMode
.CR
):
990 # go fetch masks from the CR register file
991 sync
+= new_srcmask
.eq(0)
992 sync
+= new_dstmask
.eq(0)
995 sync
+= self
.srcmask
.eq(-1)
996 sync
+= self
.dstmask
.eq(-1)
997 m
.next
= "FETCH_PRED_DONE"
999 with m
.State("INT_DST_READ"):
1000 # store destination mask
1001 inv
= Repl(dinvert
, 64)
1003 # set selected mask bit for 1<<r3 mode
1004 dst_shift
= Signal(range(64))
1005 comb
+= dst_shift
.eq(self
.int_pred
.o_data
& 0b111111)
1006 sync
+= new_dstmask
.eq(1 << dst_shift
)
1008 # invert mask if requested
1009 sync
+= new_dstmask
.eq(self
.int_pred
.o_data ^ inv
)
1010 # skip fetching source mask register, when zero
1012 sync
+= new_srcmask
.eq(-1)
1013 m
.next
= "FETCH_PRED_SHIFT_MASK"
1014 # fetch source predicate register
1016 comb
+= int_pred
.addr
.eq(sregread
)
1017 comb
+= int_pred
.ren
.eq(1)
1018 m
.next
= "INT_SRC_READ"
1020 with m
.State("INT_SRC_READ"):
1022 inv
= Repl(sinvert
, 64)
1024 # set selected mask bit for 1<<r3 mode
1025 src_shift
= Signal(range(64))
1026 comb
+= src_shift
.eq(self
.int_pred
.o_data
& 0b111111)
1027 sync
+= new_srcmask
.eq(1 << src_shift
)
1029 # invert mask if requested
1030 sync
+= new_srcmask
.eq(self
.int_pred
.o_data ^ inv
)
1031 m
.next
= "FETCH_PRED_SHIFT_MASK"
1033 # fetch masks from the CR register file
1034 # implements the following loop:
1035 # idx, inv = get_predcr(mask)
1037 # for cr_idx in range(vl):
1038 # cr = crl[cr_idx + SVP64CROffs.CRPred] # takes one cycle
1040 # mask |= 1 << cr_idx
1042 with m
.State("CR_READ"):
1043 # CR index to be read, which will be ready by the next cycle
1044 cr_idx
= Signal
.like(cur_vl
, reset_less
=True)
1045 # submit the read operation to the regfile
1046 with m
.If(cr_idx
!= cur_vl
):
1047 # the CR read port is unary ...
1049 # ... in MSB0 convention ...
1050 # ren = 1 << (7 - cr_idx)
1051 # ... and with an offset:
1052 # ren = 1 << (7 - off - cr_idx)
1053 idx
= SVP64CROffs
.CRPred
+ cr_idx
1054 comb
+= cr_pred
.ren
.eq(1 << (7 - idx
))
1055 # signal data valid in the next cycle
1056 cr_read
= Signal(reset_less
=True)
1057 sync
+= cr_read
.eq(1)
1058 # load the next index
1059 sync
+= cr_idx
.eq(cr_idx
+ 1)
1062 sync
+= cr_read
.eq(0)
1063 sync
+= cr_idx
.eq(0)
1064 m
.next
= "FETCH_PRED_SHIFT_MASK"
1066 # compensate for the one cycle delay on the regfile
1067 cur_cr_idx
= Signal
.like(cur_vl
)
1068 comb
+= cur_cr_idx
.eq(cr_idx
- 1)
1069 # read the CR field, select the appropriate bit
1070 cr_field
= Signal(4)
1073 comb
+= cr_field
.eq(cr_pred
.o_data
)
1074 comb
+= scr_bit
.eq(cr_field
.bit_select(sidx
, 1)
1076 comb
+= dcr_bit
.eq(cr_field
.bit_select(didx
, 1)
1078 # set the corresponding mask bit
1079 bit_to_set
= Signal
.like(self
.srcmask
)
1080 comb
+= bit_to_set
.eq(1 << cur_cr_idx
)
1082 sync
+= new_srcmask
.eq(new_srcmask | bit_to_set
)
1084 sync
+= new_dstmask
.eq(new_dstmask | bit_to_set
)
1086 with m
.State("FETCH_PRED_SHIFT_MASK"):
1087 # shift-out skipped mask bits
1088 sync
+= self
.srcmask
.eq(new_srcmask
>> srcstep
)
1089 sync
+= self
.dstmask
.eq(new_dstmask
>> dststep
)
1090 m
.next
= "FETCH_PRED_DONE"
1092 with m
.State("FETCH_PRED_DONE"):
1093 comb
+= pred_mask_o_valid
.eq(1)
1094 with m
.If(pred_mask_i_ready
):
1095 m
.next
= "FETCH_PRED_IDLE"
1097 def issue_fsm(self
, m
, core
, nia
,
1098 dbg
, core_rst
, is_svp64_mode
,
1099 fetch_pc_o_ready
, fetch_pc_i_valid
,
1100 fetch_insn_o_valid
, fetch_insn_i_ready
,
1101 pred_insn_i_valid
, pred_insn_o_ready
,
1102 pred_mask_o_valid
, pred_mask_i_ready
,
1103 exec_insn_i_valid
, exec_insn_o_ready
,
1104 exec_pc_o_valid
, exec_pc_i_ready
):
1107 decode / issue FSM. this interacts with the "fetch" FSM
1108 through fetch_insn_ready/valid (incoming) and fetch_pc_ready/valid
1109 (outgoing). also interacts with the "execute" FSM
1110 through exec_insn_ready/valid (outgoing) and exec_pc_ready/valid
1112 SVP64 RM prefixes have already been set up by the
1113 "fetch" phase, so execute is fairly straightforward.
1118 pdecode2
= self
.pdecode2
1119 cur_state
= self
.cur_state
1120 new_svstate
= self
.new_svstate
1123 dec_opcode_i
= pdecode2
.dec
.raw_opcode_in
# raw opcode
1125 # for updating svstate (things like srcstep etc.)
1126 comb
+= new_svstate
.eq(cur_state
.svstate
)
1128 # precalculate srcstep+1 and dststep+1
1129 cur_srcstep
= cur_state
.svstate
.srcstep
1130 cur_dststep
= cur_state
.svstate
.dststep
1131 next_srcstep
= Signal
.like(cur_srcstep
)
1132 next_dststep
= Signal
.like(cur_dststep
)
1133 comb
+= next_srcstep
.eq(cur_state
.svstate
.srcstep
+1)
1134 comb
+= next_dststep
.eq(cur_state
.svstate
.dststep
+1)
1136 # note if an exception happened. in a pipelined or OoO design
1137 # this needs to be accompanied by "shadowing" (or stalling)
1138 exc_happened
= self
.core
.o
.exc_happened
1139 # also note instruction fetch failed
1140 if hasattr(core
, "icache"):
1141 fetch_failed
= core
.icache
.i_out
.fetch_failed
1143 # set to fault in decoder
1144 # update (highest priority) instruction fault
1145 rising_fetch_failed
= rising_edge(m
, fetch_failed
)
1146 with m
.If(rising_fetch_failed
):
1147 sync
+= pdecode2
.instr_fault
.eq(1)
1149 fetch_failed
= Const(0, 1)
1150 flush_needed
= False
1152 with m
.FSM(name
="issue_fsm"):
1154 # sync with the "fetch" phase which is reading the instruction
1155 # at this point, there is no instruction running, that
1156 # could inadvertently update the PC.
1157 with m
.State("ISSUE_START"):
1158 # reset instruction fault
1159 sync
+= pdecode2
.instr_fault
.eq(0)
1160 # wait on "core stop" release, before next fetch
1161 # need to do this here, in case we are in a VL==0 loop
1162 with m
.If(~dbg
.core_stop_o
& ~core_rst
):
1163 comb
+= fetch_pc_i_valid
.eq(1) # tell fetch to start
1164 with m
.If(fetch_pc_o_ready
): # fetch acknowledged us
1165 m
.next
= "INSN_WAIT"
1167 # tell core it's stopped, and acknowledge debug handshake
1168 comb
+= dbg
.core_stopped_i
.eq(1)
1169 # while stopped, allow updating SVSTATE
1170 with m
.If(self
.svstate_i
.ok
):
1171 comb
+= new_svstate
.eq(self
.svstate_i
.data
)
1172 comb
+= self
.update_svstate
.eq(1)
1173 sync
+= self
.sv_changed
.eq(1)
1175 # wait for an instruction to arrive from Fetch
1176 with m
.State("INSN_WAIT"):
1177 # when using "single-step" mode, checking dbg.stopping_o
1178 # prevents progress. allow issue to proceed once started
1180 #if self.allow_overlap:
1181 # stopping = dbg.stopping_o
1182 with m
.If(stopping
):
1183 # stopping: jump back to idle
1184 m
.next
= "ISSUE_START"
1186 # request the icache to stop asserting "failed"
1187 comb
+= core
.icache
.flush_in
.eq(1)
1188 # stop instruction fault
1189 sync
+= pdecode2
.instr_fault
.eq(0)
1191 comb
+= fetch_insn_i_ready
.eq(1)
1192 with m
.If(fetch_insn_o_valid
):
1193 # loop into ISSUE_START if it's a SVP64 instruction
1194 # and VL == 0. this because VL==0 is a for-loop
1195 # from 0 to 0 i.e. always, always a NOP.
1196 cur_vl
= cur_state
.svstate
.vl
1197 with m
.If(is_svp64_mode
& (cur_vl
== 0)):
1198 # update the PC before fetching the next instruction
1199 # since we are in a VL==0 loop, no instruction was
1200 # executed that we could be overwriting
1201 comb
+= self
.state_w_pc
.wen
.eq(1 << StateRegs
.PC
)
1202 comb
+= self
.state_w_pc
.i_data
.eq(nia
)
1203 comb
+= self
.insn_done
.eq(1)
1204 m
.next
= "ISSUE_START"
1207 m
.next
= "PRED_START" # fetching predicate
1209 m
.next
= "DECODE_SV" # skip predication
1211 with m
.State("PRED_START"):
1212 comb
+= pred_insn_i_valid
.eq(1) # tell fetch_pred to start
1213 with m
.If(pred_insn_o_ready
): # fetch_pred acknowledged us
1214 m
.next
= "MASK_WAIT"
1216 with m
.State("MASK_WAIT"):
1217 comb
+= pred_mask_i_ready
.eq(1) # ready to receive the masks
1218 with m
.If(pred_mask_o_valid
): # predication masks are ready
1219 m
.next
= "PRED_SKIP"
1221 # skip zeros in predicate
1222 with m
.State("PRED_SKIP"):
1223 with m
.If(~is_svp64_mode
):
1224 m
.next
= "DECODE_SV" # nothing to do
1227 pred_src_zero
= pdecode2
.rm_dec
.pred_sz
1228 pred_dst_zero
= pdecode2
.rm_dec
.pred_dz
1230 # new srcstep, after skipping zeros
1231 skip_srcstep
= Signal
.like(cur_srcstep
)
1232 # value to be added to the current srcstep
1233 src_delta
= Signal
.like(cur_srcstep
)
1234 # add leading zeros to srcstep, if not in zero mode
1235 with m
.If(~pred_src_zero
):
1236 # priority encoder (count leading zeros)
1237 # append guard bit, in case the mask is all zeros
1238 pri_enc_src
= PriorityEncoder(65)
1239 m
.submodules
.pri_enc_src
= pri_enc_src
1240 comb
+= pri_enc_src
.i
.eq(Cat(self
.srcmask
,
1242 comb
+= src_delta
.eq(pri_enc_src
.o
)
1243 # apply delta to srcstep
1244 comb
+= skip_srcstep
.eq(cur_srcstep
+ src_delta
)
1245 # shift-out all leading zeros from the mask
1246 # plus the leading "one" bit
1247 # TODO count leading zeros and shift-out the zero
1248 # bits, in the same step, in hardware
1249 sync
+= self
.srcmask
.eq(self
.srcmask
>> (src_delta
+1))
1251 # same as above, but for dststep
1252 skip_dststep
= Signal
.like(cur_dststep
)
1253 dst_delta
= Signal
.like(cur_dststep
)
1254 with m
.If(~pred_dst_zero
):
1255 pri_enc_dst
= PriorityEncoder(65)
1256 m
.submodules
.pri_enc_dst
= pri_enc_dst
1257 comb
+= pri_enc_dst
.i
.eq(Cat(self
.dstmask
,
1259 comb
+= dst_delta
.eq(pri_enc_dst
.o
)
1260 comb
+= skip_dststep
.eq(cur_dststep
+ dst_delta
)
1261 sync
+= self
.dstmask
.eq(self
.dstmask
>> (dst_delta
+1))
1263 # TODO: initialize mask[VL]=1 to avoid passing past VL
1264 with m
.If((skip_srcstep
>= cur_vl
) |
1265 (skip_dststep
>= cur_vl
)):
1266 # end of VL loop. Update PC and reset src/dst step
1267 comb
+= self
.state_w_pc
.wen
.eq(1 << StateRegs
.PC
)
1268 comb
+= self
.state_w_pc
.i_data
.eq(nia
)
1269 comb
+= new_svstate
.srcstep
.eq(0)
1270 comb
+= new_svstate
.dststep
.eq(0)
1271 comb
+= self
.update_svstate
.eq(1)
1272 # synchronize with the simulator
1273 comb
+= self
.insn_done
.eq(1)
1275 m
.next
= "ISSUE_START"
1277 # update new src/dst step
1278 comb
+= new_svstate
.srcstep
.eq(skip_srcstep
)
1279 comb
+= new_svstate
.dststep
.eq(skip_dststep
)
1280 comb
+= self
.update_svstate
.eq(1)
1282 m
.next
= "DECODE_SV"
1284 # pass predicate mask bits through to satellite decoders
1285 # TODO: for SIMD this will be *multiple* bits
1286 sync
+= core
.i
.sv_pred_sm
.eq(self
.srcmask
[0])
1287 sync
+= core
.i
.sv_pred_dm
.eq(self
.dstmask
[0])
1289 # after src/dst step have been updated, we are ready
1290 # to decode the instruction
1291 with m
.State("DECODE_SV"):
1292 # decode the instruction
1293 with m
.If(~fetch_failed
):
1294 sync
+= pdecode2
.instr_fault
.eq(0)
1295 sync
+= core
.i
.e
.eq(pdecode2
.e
)
1296 sync
+= core
.i
.state
.eq(cur_state
)
1297 sync
+= core
.i
.raw_insn_i
.eq(dec_opcode_i
)
1298 sync
+= core
.i
.bigendian_i
.eq(self
.core_bigendian_i
)
1300 sync
+= core
.i
.sv_rm
.eq(pdecode2
.sv_rm
)
1301 # set RA_OR_ZERO detection in satellite decoders
1302 sync
+= core
.i
.sv_a_nz
.eq(pdecode2
.sv_a_nz
)
1303 # and svp64 detection
1304 sync
+= core
.i
.is_svp64_mode
.eq(is_svp64_mode
)
1305 # and svp64 bit-rev'd ldst mode
1306 ldst_dec
= pdecode2
.use_svp64_ldst_dec
1307 sync
+= core
.i
.use_svp64_ldst_dec
.eq(ldst_dec
)
1308 # after decoding, reset any previous exception condition,
1309 # allowing it to be set again during the next execution
1310 sync
+= pdecode2
.ldst_exc
.eq(0)
1312 m
.next
= "INSN_EXECUTE" # move to "execute"
1314 # handshake with execution FSM, move to "wait" once acknowledged
1315 with m
.State("INSN_EXECUTE"):
1316 # when using "single-step" mode, checking dbg.stopping_o
1317 # prevents progress. allow execute to proceed once started
1319 #if self.allow_overlap:
1320 # stopping = dbg.stopping_o
1321 with m
.If(stopping
):
1322 # stopping: jump back to idle
1323 m
.next
= "ISSUE_START"
1325 # request the icache to stop asserting "failed"
1326 comb
+= core
.icache
.flush_in
.eq(1)
1327 # stop instruction fault
1328 sync
+= pdecode2
.instr_fault
.eq(0)
1330 comb
+= exec_insn_i_valid
.eq(1) # trigger execute
1331 with m
.If(exec_insn_o_ready
): # execute acknowledged us
1332 m
.next
= "EXECUTE_WAIT"
1334 with m
.State("EXECUTE_WAIT"):
1335 comb
+= exec_pc_i_ready
.eq(1)
1336 # see https://bugs.libre-soc.org/show_bug.cgi?id=636
1337 # the exception info needs to be blatted into
1338 # pdecode.ldst_exc, and the instruction "re-run".
1339 # when ldst_exc.happened is set, the PowerDecoder2
1340 # reacts very differently: it re-writes the instruction
1341 # with a "trap" (calls PowerDecoder2.trap()) which
1342 # will *overwrite* whatever was requested and jump the
1343 # PC to the exception address, as well as alter MSR.
1344 # nothing else needs to be done other than to note
1345 # the change of PC and MSR (and, later, SVSTATE)
1346 with m
.If(exc_happened
):
1347 mmu
= core
.fus
.get_exc("mmu0")
1348 ldst
= core
.fus
.get_exc("ldst0")
1350 with m
.If(fetch_failed
):
1351 # instruction fetch: exception is from MMU
1352 # reset instr_fault (highest priority)
1353 sync
+= pdecode2
.ldst_exc
.eq(mmu
)
1354 sync
+= pdecode2
.instr_fault
.eq(0)
1356 # request icache to stop asserting "failed"
1357 comb
+= core
.icache
.flush_in
.eq(1)
1358 with m
.If(~fetch_failed
):
1359 # otherwise assume it was a LDST exception
1360 sync
+= pdecode2
.ldst_exc
.eq(ldst
)
1362 with m
.If(exec_pc_o_valid
):
1364 # was this the last loop iteration?
1366 cur_vl
= cur_state
.svstate
.vl
1367 comb
+= is_last
.eq(next_srcstep
== cur_vl
)
1369 with m
.If(pdecode2
.instr_fault
):
1370 # reset instruction fault, try again
1371 sync
+= pdecode2
.instr_fault
.eq(0)
1372 m
.next
= "ISSUE_START"
1374 # return directly to Decode if Execute generated an
1376 with m
.Elif(pdecode2
.ldst_exc
.happened
):
1377 m
.next
= "DECODE_SV"
1379 # if MSR, PC or SVSTATE were changed by the previous
1380 # instruction, go directly back to Fetch, without
1381 # updating either MSR PC or SVSTATE
1382 with m
.Elif(self
.msr_changed | self
.pc_changed |
1384 m
.next
= "ISSUE_START"
1386 # also return to Fetch, when no output was a vector
1387 # (regardless of SRCSTEP and VL), or when the last
1388 # instruction was really the last one of the VL loop
1389 with m
.Elif((~pdecode2
.loop_continue
) | is_last
):
1390 # before going back to fetch, update the PC state
1391 # register with the NIA.
1392 # ok here we are not reading the branch unit.
1393 # TODO: this just blithely overwrites whatever
1394 # pipeline updated the PC
1395 comb
+= self
.state_w_pc
.wen
.eq(1 << StateRegs
.PC
)
1396 comb
+= self
.state_w_pc
.i_data
.eq(nia
)
1397 # reset SRCSTEP before returning to Fetch
1399 with m
.If(pdecode2
.loop_continue
):
1400 comb
+= new_svstate
.srcstep
.eq(0)
1401 comb
+= new_svstate
.dststep
.eq(0)
1402 comb
+= self
.update_svstate
.eq(1)
1404 comb
+= new_svstate
.srcstep
.eq(0)
1405 comb
+= new_svstate
.dststep
.eq(0)
1406 comb
+= self
.update_svstate
.eq(1)
1407 m
.next
= "ISSUE_START"
1409 # returning to Execute? then, first update SRCSTEP
1411 comb
+= new_svstate
.srcstep
.eq(next_srcstep
)
1412 comb
+= new_svstate
.dststep
.eq(next_dststep
)
1413 comb
+= self
.update_svstate
.eq(1)
1414 # return to mask skip loop
1415 m
.next
= "PRED_SKIP"
1418 # check if svstate needs updating: if so, write it to State Regfile
1419 with m
.If(self
.update_svstate
):
1420 sync
+= cur_state
.svstate
.eq(self
.new_svstate
) # for next clock
1422 def execute_fsm(self
, m
, core
,
1423 exec_insn_i_valid
, exec_insn_o_ready
,
1424 exec_pc_o_valid
, exec_pc_i_ready
):
1427 execute FSM. this interacts with the "issue" FSM
1428 through exec_insn_ready/valid (incoming) and exec_pc_ready/valid
1429 (outgoing). SVP64 RM prefixes have already been set up by the
1430 "issue" phase, so execute is fairly straightforward.
1436 pdecode2
= self
.pdecode2
1439 core_busy_o
= core
.n
.o_data
.busy_o
# core is busy
1440 core_ivalid_i
= core
.p
.i_valid
# instruction is valid
1442 if hasattr(core
, "icache"):
1443 fetch_failed
= core
.icache
.i_out
.fetch_failed
1445 fetch_failed
= Const(0, 1)
1447 with m
.FSM(name
="exec_fsm"):
1449 # waiting for instruction bus (stays there until not busy)
1450 with m
.State("INSN_START"):
1451 comb
+= exec_insn_o_ready
.eq(1)
1452 with m
.If(exec_insn_i_valid
):
1453 comb
+= core_ivalid_i
.eq(1) # instruction is valid/issued
1454 sync
+= self
.sv_changed
.eq(0)
1455 sync
+= self
.pc_changed
.eq(0)
1456 sync
+= self
.msr_changed
.eq(0)
1457 with m
.If(core
.p
.o_ready
): # only move if accepted
1458 m
.next
= "INSN_ACTIVE" # move to "wait completion"
1460 # instruction started: must wait till it finishes
1461 with m
.State("INSN_ACTIVE"):
1462 # note changes to MSR, PC and SVSTATE
1463 # XXX oops, really must monitor *all* State Regfile write
1464 # ports looking for changes!
1465 with m
.If(self
.state_nia
.wen
& (1 << StateRegs
.SVSTATE
)):
1466 sync
+= self
.sv_changed
.eq(1)
1467 with m
.If(self
.state_nia
.wen
& (1 << StateRegs
.MSR
)):
1468 sync
+= self
.msr_changed
.eq(1)
1469 with m
.If(self
.state_nia
.wen
& (1 << StateRegs
.PC
)):
1470 sync
+= self
.pc_changed
.eq(1)
1471 with m
.If(~core_busy_o
): # instruction done!
1472 comb
+= exec_pc_o_valid
.eq(1)
1473 with m
.If(exec_pc_i_ready
):
1474 # when finished, indicate "done".
1475 # however, if there was an exception, the instruction
1476 # is *not* yet done. this is an implementation
1477 # detail: we choose to implement exceptions by
1478 # taking the exception information from the LDST
1479 # unit, putting that *back* into the PowerDecoder2,
1480 # and *re-running the entire instruction*.
1481 # if we erroneously indicate "done" here, it is as if
1482 # there were *TWO* instructions:
1483 # 1) the failed LDST 2) a TRAP.
1484 with m
.If(~pdecode2
.ldst_exc
.happened
&
1485 ~pdecode2
.instr_fault
):
1486 comb
+= self
.insn_done
.eq(1)
1487 m
.next
= "INSN_START" # back to fetch
1488 # terminate returns directly to INSN_START
1489 with m
.If(dbg
.terminate_i
):
1490 # comb += self.insn_done.eq(1) - no because it's not
1491 m
.next
= "INSN_START" # back to fetch
1493 def elaborate(self
, platform
):
1494 m
= super().elaborate(platform
)
1496 comb
, sync
= m
.d
.comb
, m
.d
.sync
1497 cur_state
= self
.cur_state
1498 pdecode2
= self
.pdecode2
1502 # set up peripherals and core
1503 core_rst
= self
.core_rst
1505 # indicate to outside world if any FU is still executing
1506 comb
+= self
.any_busy
.eq(core
.n
.o_data
.any_busy_o
) # any FU executing
1508 # address of the next instruction, in the absence of a branch
1509 # depends on the instruction size
1512 # connect up debug signals
1513 with m
.If(core
.o
.core_terminate_o
):
1514 comb
+= dbg
.terminate_i
.eq(1)
1516 # pass the prefix mode from Fetch to Issue, so the latter can loop
1518 is_svp64_mode
= Signal()
1520 # there are *THREE^WFOUR-if-SVP64-enabled* FSMs, fetch (32/64-bit)
1521 # issue, decode/execute, now joined by "Predicate fetch/calculate".
1522 # these are the handshake signals between each
1524 # fetch FSM can run as soon as the PC is valid
1525 fetch_pc_i_valid
= Signal() # Execute tells Fetch "start next read"
1526 fetch_pc_o_ready
= Signal() # Fetch Tells SVSTATE "proceed"
1528 # fetch FSM hands over the instruction to be decoded / issued
1529 fetch_insn_o_valid
= Signal()
1530 fetch_insn_i_ready
= Signal()
1532 # predicate fetch FSM decodes and fetches the predicate
1533 pred_insn_i_valid
= Signal()
1534 pred_insn_o_ready
= Signal()
1536 # predicate fetch FSM delivers the masks
1537 pred_mask_o_valid
= Signal()
1538 pred_mask_i_ready
= Signal()
1540 # issue FSM delivers the instruction to the be executed
1541 exec_insn_i_valid
= Signal()
1542 exec_insn_o_ready
= Signal()
1544 # execute FSM, hands over the PC/SVSTATE back to the issue FSM
1545 exec_pc_o_valid
= Signal()
1546 exec_pc_i_ready
= Signal()
1548 # the FSMs here are perhaps unusual in that they detect conditions
1549 # then "hold" information, combinatorially, for the core
1550 # (as opposed to using sync - which would be on a clock's delay)
1551 # this includes the actual opcode, valid flags and so on.
1553 # Fetch, then predicate fetch, then Issue, then Execute.
1554 # Issue is where the VL for-loop # lives. the ready/valid
1555 # signalling is used to communicate between the four.
1557 self
.fetch_fsm(m
, dbg
, core
, dbg
.state
.pc
, dbg
.state
.msr
,
1558 dbg
.state
.svstate
, nia
, is_svp64_mode
,
1559 fetch_pc_o_ready
, fetch_pc_i_valid
,
1560 fetch_insn_o_valid
, fetch_insn_i_ready
)
1562 self
.issue_fsm(m
, core
, nia
,
1563 dbg
, core_rst
, is_svp64_mode
,
1564 fetch_pc_o_ready
, fetch_pc_i_valid
,
1565 fetch_insn_o_valid
, fetch_insn_i_ready
,
1566 pred_insn_i_valid
, pred_insn_o_ready
,
1567 pred_mask_o_valid
, pred_mask_i_ready
,
1568 exec_insn_i_valid
, exec_insn_o_ready
,
1569 exec_pc_o_valid
, exec_pc_i_ready
)
1572 self
.fetch_predicate_fsm(m
,
1573 pred_insn_i_valid
, pred_insn_o_ready
,
1574 pred_mask_o_valid
, pred_mask_i_ready
)
1576 self
.execute_fsm(m
, core
,
1577 exec_insn_i_valid
, exec_insn_o_ready
,
1578 exec_pc_o_valid
, exec_pc_i_ready
)
1580 # whatever was done above, over-ride it if core reset is held
1581 with m
.If(core_rst
):
1587 class TestIssuer(Elaboratable
):
1588 def __init__(self
, pspec
):
1589 self
.ti
= TestIssuerInternal(pspec
)
1590 self
.pll
= DummyPLL(instance
=True)
1592 self
.dbg_rst_i
= Signal(reset_less
=True)
1594 # PLL direct clock or not
1595 self
.pll_en
= hasattr(pspec
, "use_pll") and pspec
.use_pll
1597 self
.pll_test_o
= Signal(reset_less
=True)
1598 self
.pll_vco_o
= Signal(reset_less
=True)
1599 self
.clk_sel_i
= Signal(2, reset_less
=True)
1600 self
.ref_clk
= ClockSignal() # can't rename it but that's ok
1601 self
.pllclk_clk
= ClockSignal("pllclk")
1603 def elaborate(self
, platform
):
1607 # TestIssuer nominally runs at main clock, actually it is
1608 # all combinatorial internally except for coresync'd components
1609 m
.submodules
.ti
= ti
= self
.ti
1612 # ClockSelect runs at PLL output internal clock rate
1613 m
.submodules
.wrappll
= pll
= self
.pll
1615 # add clock domains from PLL
1616 cd_pll
= ClockDomain("pllclk")
1619 # PLL clock established. has the side-effect of running clklsel
1620 # at the PLL's speed (see DomainRenamer("pllclk") above)
1621 pllclk
= self
.pllclk_clk
1622 comb
+= pllclk
.eq(pll
.clk_pll_o
)
1624 # wire up external 24mhz to PLL
1625 #comb += pll.clk_24_i.eq(self.ref_clk)
1626 # output 18 mhz PLL test signal, and analog oscillator out
1627 comb
+= self
.pll_test_o
.eq(pll
.pll_test_o
)
1628 comb
+= self
.pll_vco_o
.eq(pll
.pll_vco_o
)
1630 # input to pll clock selection
1631 comb
+= pll
.clk_sel_i
.eq(self
.clk_sel_i
)
1633 # now wire up ResetSignals. don't mind them being in this domain
1634 pll_rst
= ResetSignal("pllclk")
1635 comb
+= pll_rst
.eq(ResetSignal())
1637 # internal clock is set to selector clock-out. has the side-effect of
1638 # running TestIssuer at this speed (see DomainRenamer("intclk") above)
1639 # debug clock runs at coresync internal clock
1640 if self
.ti
.dbg_domain
!= 'sync':
1641 cd_dbgsync
= ClockDomain("dbgsync")
1642 intclk
= ClockSignal(self
.ti
.core_domain
)
1643 dbgclk
= ClockSignal(self
.ti
.dbg_domain
)
1644 # XXX BYPASS PLL XXX
1645 # XXX BYPASS PLL XXX
1646 # XXX BYPASS PLL XXX
1648 comb
+= intclk
.eq(self
.ref_clk
)
1649 assert self
.ti
.core_domain
!= 'sync', \
1650 "cannot set core_domain to sync and use pll at the same time"
1652 if self
.ti
.core_domain
!= 'sync':
1653 comb
+= intclk
.eq(ClockSignal())
1654 if self
.ti
.dbg_domain
!= 'sync':
1655 dbgclk
= ClockSignal(self
.ti
.dbg_domain
)
1656 comb
+= dbgclk
.eq(intclk
)
1657 comb
+= self
.ti
.dbg_rst_i
.eq(self
.dbg_rst_i
)
1662 return list(self
.ti
.ports()) + list(self
.pll
.ports()) + \
1663 [ClockSignal(), ResetSignal()]
1665 def external_ports(self
):
1666 ports
= self
.ti
.external_ports()
1667 ports
.append(ClockSignal())
1668 ports
.append(ResetSignal())
1670 ports
.append(self
.clk_sel_i
)
1671 ports
.append(self
.pll
.clk_24_i
)
1672 ports
.append(self
.pll_test_o
)
1673 ports
.append(self
.pll_vco_o
)
1674 ports
.append(self
.pllclk_clk
)
1675 ports
.append(self
.ref_clk
)
1679 if __name__
== '__main__':
1680 units
= {'alu': 1, 'cr': 1, 'branch': 1, 'trap': 1, 'logical': 1,
1686 pspec
= TestMemPspec(ldst_ifacetype
='bare_wb',
1687 imem_ifacetype
='bare_wb',
1692 dut
= TestIssuer(pspec
)
1693 vl
= main(dut
, ports
=dut
.ports(), name
="test_issuer")
1695 if len(sys
.argv
) == 1:
1696 vl
= rtlil
.convert(dut
, ports
=dut
.external_ports(), name
="test_issuer")
1697 with
open("test_issuer.il", "w") as f
: