3 not in any way intended for production use. this runs a FSM that:
5 * reads the Program Counter from StateRegs
6 * reads an instruction from a fixed-size Test Memory
7 * issues it to the Simple Core
8 * waits for it to complete
10 * does it all over again
12 the purpose of this module is to verify the functional correctness
13 of the Function Units in the absolute simplest and clearest possible
14 way, and to at provide something that can be further incrementally
18 from nmigen
import (Elaboratable
, Module
, Signal
, ClockSignal
, ResetSignal
,
19 ClockDomain
, DomainRenamer
, Mux
, Const
, Repl
, Cat
)
20 from nmigen
.cli
import rtlil
21 from nmigen
.cli
import main
24 from nmutil
.singlepipe
import ControlBase
25 from soc
.simple
.core_data
import FetchOutput
, FetchInput
27 from nmigen
.lib
.coding
import PriorityEncoder
29 from openpower
.decoder
.power_decoder
import create_pdecode
30 from openpower
.decoder
.power_decoder2
import PowerDecode2
, SVP64PrefixDecoder
31 from openpower
.decoder
.decode2execute1
import IssuerDecode2ToOperand
32 from openpower
.decoder
.decode2execute1
import Data
33 from openpower
.decoder
.power_enums
import (MicrOp
, SVP64PredInt
, SVP64PredCR
,
35 from openpower
.state
import CoreState
36 from openpower
.consts
import (CR
, SVP64CROffs
, MSR
)
37 from soc
.experiment
.testmem
import TestMemory
# test only for instructions
38 from soc
.regfile
.regfiles
import StateRegs
, FastRegs
39 from soc
.simple
.core
import NonProductionCore
40 from soc
.config
.test
.test_loadstore
import TestMemPspec
41 from soc
.config
.ifetch
import ConfigFetchUnit
42 from soc
.debug
.dmi
import CoreDebug
, DMIInterface
43 from soc
.debug
.jtag
import JTAG
44 from soc
.config
.pinouts
import get_pinspecs
45 from soc
.interrupts
.xics
import XICS_ICP
, XICS_ICS
46 from soc
.bus
.simple_gpio
import SimpleGPIO
47 from soc
.bus
.SPBlock512W64B8W
import SPBlock512W64B8W
48 from soc
.clock
.select
import ClockSelect
49 from soc
.clock
.dummypll
import DummyPLL
50 from openpower
.sv
.svstate
import SVSTATERec
51 from soc
.experiment
.icache
import ICache
53 from nmutil
.util
import rising_edge
56 def get_insn(f_instr_o
, pc
):
57 if f_instr_o
.width
== 32:
60 # 64-bit: bit 2 of pc decides which word to select
61 return f_instr_o
.word_select(pc
[2], 32)
63 # gets state input or reads from state regfile
66 def state_get(m
, res
, core_rst
, state_i
, name
, regfile
, regnum
):
69 # read the {insert state variable here}
70 res_ok_delay
= Signal(name
="%s_ok_delay" % name
)
72 sync
+= res_ok_delay
.eq(~state_i
.ok
)
73 with m
.If(state_i
.ok
):
74 # incoming override (start from pc_i)
75 comb
+= res
.eq(state_i
.data
)
77 # otherwise read StateRegs regfile for {insert state here}...
78 comb
+= regfile
.ren
.eq(1 << regnum
)
79 # ... but on a 1-clock delay
80 with m
.If(res_ok_delay
):
81 comb
+= res
.eq(regfile
.o_data
)
84 def get_predint(m
, mask
, name
):
85 """decode SVP64 predicate integer mask field to reg number and invert
86 this is identical to the equivalent function in ISACaller except that
87 it doesn't read the INT directly, it just decodes "what needs to be done"
88 i.e. which INT reg, whether it is shifted and whether it is bit-inverted.
90 * all1s is set to indicate that no mask is to be applied.
91 * regread indicates the GPR register number to be read
92 * invert is set to indicate that the register value is to be inverted
93 * unary indicates that the contents of the register is to be shifted 1<<r3
96 regread
= Signal(5, name
=name
+"regread")
97 invert
= Signal(name
=name
+"invert")
98 unary
= Signal(name
=name
+"unary")
99 all1s
= Signal(name
=name
+"all1s")
101 with m
.Case(SVP64PredInt
.ALWAYS
.value
):
102 comb
+= all1s
.eq(1) # use 0b1111 (all ones)
103 with m
.Case(SVP64PredInt
.R3_UNARY
.value
):
104 comb
+= regread
.eq(3)
105 comb
+= unary
.eq(1) # 1<<r3 - shift r3 (single bit)
106 with m
.Case(SVP64PredInt
.R3
.value
):
107 comb
+= regread
.eq(3)
108 with m
.Case(SVP64PredInt
.R3_N
.value
):
109 comb
+= regread
.eq(3)
111 with m
.Case(SVP64PredInt
.R10
.value
):
112 comb
+= regread
.eq(10)
113 with m
.Case(SVP64PredInt
.R10_N
.value
):
114 comb
+= regread
.eq(10)
116 with m
.Case(SVP64PredInt
.R30
.value
):
117 comb
+= regread
.eq(30)
118 with m
.Case(SVP64PredInt
.R30_N
.value
):
119 comb
+= regread
.eq(30)
121 return regread
, invert
, unary
, all1s
124 def get_predcr(m
, mask
, name
):
125 """decode SVP64 predicate CR to reg number field and invert status
126 this is identical to _get_predcr in ISACaller
129 idx
= Signal(2, name
=name
+"idx")
130 invert
= Signal(name
=name
+"crinvert")
132 with m
.Case(SVP64PredCR
.LT
.value
):
133 comb
+= idx
.eq(CR
.LT
)
135 with m
.Case(SVP64PredCR
.GE
.value
):
136 comb
+= idx
.eq(CR
.LT
)
138 with m
.Case(SVP64PredCR
.GT
.value
):
139 comb
+= idx
.eq(CR
.GT
)
141 with m
.Case(SVP64PredCR
.LE
.value
):
142 comb
+= idx
.eq(CR
.GT
)
144 with m
.Case(SVP64PredCR
.EQ
.value
):
145 comb
+= idx
.eq(CR
.EQ
)
147 with m
.Case(SVP64PredCR
.NE
.value
):
148 comb
+= idx
.eq(CR
.EQ
)
150 with m
.Case(SVP64PredCR
.SO
.value
):
151 comb
+= idx
.eq(CR
.SO
)
153 with m
.Case(SVP64PredCR
.NS
.value
):
154 comb
+= idx
.eq(CR
.SO
)
159 class TestIssuerBase(Elaboratable
):
160 """TestIssuerBase - common base class for Issuers
162 takes care of power-on reset, peripherals, debug, DEC/TB,
163 and gets PC/MSR/SVSTATE from the State Regfile etc.
166 def __init__(self
, pspec
):
168 # test if microwatt compatibility is to be enabled
169 self
.microwatt_compat
= (hasattr(pspec
, "microwatt_compat") and
170 (pspec
.microwatt_compat
== True))
171 self
.alt_reset
= Signal(reset_less
=True) # not connected yet (microwatt)
173 # test is SVP64 is to be enabled
174 self
.svp64_en
= hasattr(pspec
, "svp64") and (pspec
.svp64
== True)
176 # and if regfiles are reduced
177 self
.regreduce_en
= (hasattr(pspec
, "regreduce") and
178 (pspec
.regreduce
== True))
180 # and if overlap requested
181 self
.allow_overlap
= (hasattr(pspec
, "allow_overlap") and
182 (pspec
.allow_overlap
== True))
184 # and get the core domain
185 self
.core_domain
= "coresync"
186 if (hasattr(pspec
, "core_domain") and
187 isinstance(pspec
.core_domain
, str)):
188 self
.core_domain
= pspec
.core_domain
190 # JTAG interface. add this right at the start because if it's
191 # added it *modifies* the pspec, by adding enable/disable signals
192 # for parts of the rest of the core
193 self
.jtag_en
= hasattr(pspec
, "debug") and pspec
.debug
== 'jtag'
194 #self.dbg_domain = "sync" # sigh "dbgsunc" too problematic
195 self
.dbg_domain
= "dbgsync" # domain for DMI/JTAG clock
197 # XXX MUST keep this up-to-date with litex, and
198 # soc-cocotb-sim, and err.. all needs sorting out, argh
201 'eint', 'gpio', 'mspi0',
202 # 'mspi1', - disabled for now
203 # 'pwm', 'sd0', - disabled for now
205 self
.jtag
= JTAG(get_pinspecs(subset
=subset
),
206 domain
=self
.dbg_domain
)
207 # add signals to pspec to enable/disable icache and dcache
208 # (or data and intstruction wishbone if icache/dcache not included)
209 # https://bugs.libre-soc.org/show_bug.cgi?id=520
210 # TODO: do we actually care if these are not domain-synchronised?
211 # honestly probably not.
212 pspec
.wb_icache_en
= self
.jtag
.wb_icache_en
213 pspec
.wb_dcache_en
= self
.jtag
.wb_dcache_en
214 self
.wb_sram_en
= self
.jtag
.wb_sram_en
216 self
.wb_sram_en
= Const(1)
218 # add 4k sram blocks?
219 self
.sram4x4k
= (hasattr(pspec
, "sram4x4kblock") and
220 pspec
.sram4x4kblock
== True)
224 self
.sram4k
.append(SPBlock512W64B8W(name
="sram4k_%d" % i
,
228 # add interrupt controller?
229 self
.xics
= hasattr(pspec
, "xics") and pspec
.xics
== True
231 self
.xics_icp
= XICS_ICP()
232 self
.xics_ics
= XICS_ICS()
233 self
.int_level_i
= self
.xics_ics
.int_level_i
235 self
.ext_irq
= Signal()
237 # add GPIO peripheral?
238 self
.gpio
= hasattr(pspec
, "gpio") and pspec
.gpio
== True
240 self
.simple_gpio
= SimpleGPIO()
241 self
.gpio_o
= self
.simple_gpio
.gpio_o
243 # main instruction core. suitable for prototyping / demo only
244 self
.core
= core
= NonProductionCore(pspec
)
245 self
.core_rst
= ResetSignal(self
.core_domain
)
247 # instruction decoder. goes into Trap Record
248 #pdecode = create_pdecode()
249 self
.cur_state
= CoreState("cur") # current state (MSR/PC/SVSTATE)
250 self
.pdecode2
= PowerDecode2(None, state
=self
.cur_state
,
251 opkls
=IssuerDecode2ToOperand
,
252 svp64_en
=self
.svp64_en
,
253 regreduce_en
=self
.regreduce_en
)
254 pdecode
= self
.pdecode2
.dec
257 self
.svp64
= SVP64PrefixDecoder() # for decoding SVP64 prefix
259 self
.update_svstate
= Signal() # set this if updating svstate
260 self
.new_svstate
= new_svstate
= SVSTATERec("new_svstate")
262 # Test Instruction memory
263 if hasattr(core
, "icache"):
264 # XXX BLECH! use pspec to transfer the I-Cache to ConfigFetchUnit
265 # truly dreadful. needs a huge reorg.
266 pspec
.icache
= core
.icache
267 self
.imem
= ConfigFetchUnit(pspec
).fu
270 self
.dbg
= CoreDebug()
271 self
.dbg_rst_i
= Signal(reset_less
=True)
273 # instruction go/monitor
274 self
.pc_o
= Signal(64, reset_less
=True)
275 self
.pc_i
= Data(64, "pc_i") # set "ok" to indicate "please change me"
276 self
.msr_i
= Data(64, "msr_i") # set "ok" to indicate "please change me"
277 self
.svstate_i
= Data(64, "svstate_i") # ditto
278 self
.core_bigendian_i
= Signal() # TODO: set based on MSR.LE
279 self
.busy_o
= Signal(reset_less
=True)
280 self
.memerr_o
= Signal(reset_less
=True)
282 # STATE regfile read /write ports for PC, MSR, SVSTATE
283 staterf
= self
.core
.regs
.rf
['state']
284 self
.state_r_msr
= staterf
.r_ports
['msr'] # MSR rd
285 self
.state_r_pc
= staterf
.r_ports
['cia'] # PC rd
286 self
.state_r_sv
= staterf
.r_ports
['sv'] # SVSTATE rd
288 self
.state_w_msr
= staterf
.w_ports
['d_wr2'] # MSR wr
289 self
.state_w_pc
= staterf
.w_ports
['d_wr1'] # PC wr
290 self
.state_w_sv
= staterf
.w_ports
['sv'] # SVSTATE wr
292 # DMI interface access
293 intrf
= self
.core
.regs
.rf
['int']
294 fastrf
= self
.core
.regs
.rf
['fast']
295 crrf
= self
.core
.regs
.rf
['cr']
296 xerrf
= self
.core
.regs
.rf
['xer']
297 self
.int_r
= intrf
.r_ports
['dmi'] # INT DMI read
298 self
.cr_r
= crrf
.r_ports
['full_cr_dbg'] # CR DMI read
299 self
.xer_r
= xerrf
.r_ports
['full_xer'] # XER DMI read
300 self
.fast_r
= fastrf
.r_ports
['dmi'] # FAST DMI read
304 self
.int_pred
= intrf
.r_ports
['pred'] # INT predicate read
305 self
.cr_pred
= crrf
.r_ports
['cr_pred'] # CR predicate read
307 # hack method of keeping an eye on whether branch/trap set the PC
308 self
.state_nia
= self
.core
.regs
.rf
['state'].w_ports
['nia']
309 self
.state_nia
.wen
.name
= 'state_nia_wen'
311 # pulse to synchronize the simulator at instruction end
312 self
.insn_done
= Signal()
314 # indicate any instruction still outstanding, in execution
315 self
.any_busy
= Signal()
318 # store copies of predicate masks
319 self
.srcmask
= Signal(64)
320 self
.dstmask
= Signal(64)
322 # sigh, the wishbone addresses are not wishbone-compliant in microwatt
323 if self
.microwatt_compat
:
324 self
.ibus_adr
= Signal(32, name
='wishbone_insn_out.adr')
325 self
.dbus_adr
= Signal(32, name
='wishbone_data_out.adr')
327 # add an output of the PC and instruction, and whether it was requested
328 # this is for verilator debug purposes
329 if self
.microwatt_compat
:
330 self
.nia
= Signal(64)
331 self
.msr_o
= Signal(64)
332 self
.nia_req
= Signal(1)
333 self
.insn
= Signal(32)
334 self
.ldst_req
= Signal(1)
335 self
.ldst_addr
= Signal(1)
337 # for pausing dec/tb during an SPR pipeline event, this
338 # ensures that an SPR write (mtspr) to TB or DEC does not
339 # get overwritten by the DEC/TB FSM
340 self
.pause_dec_tb
= Signal()
342 def setup_peripherals(self
, m
):
343 comb
, sync
= m
.d
.comb
, m
.d
.sync
345 # okaaaay so the debug module must be in coresync clock domain
346 # but NOT its reset signal. to cope with this, set every single
347 # submodule explicitly in coresync domain, debug and JTAG
348 # in their own one but using *external* reset.
349 csd
= DomainRenamer(self
.core_domain
)
350 dbd
= DomainRenamer(self
.dbg_domain
)
352 if self
.microwatt_compat
:
353 m
.submodules
.core
= core
= self
.core
355 m
.submodules
.core
= core
= csd(self
.core
)
357 # this _so_ needs sorting out. ICache is added down inside
358 # LoadStore1 and is already a submodule of LoadStore1
359 if not isinstance(self
.imem
, ICache
):
360 m
.submodules
.imem
= imem
= csd(self
.imem
)
362 # set up JTAG Debug Module (in correct domain)
363 m
.submodules
.dbg
= dbg
= dbd(self
.dbg
)
365 m
.submodules
.jtag
= jtag
= dbd(self
.jtag
)
366 # TODO: UART2GDB mux, here, from external pin
367 # see https://bugs.libre-soc.org/show_bug.cgi?id=499
368 sync
+= dbg
.dmi
.connect_to(jtag
.dmi
)
370 # fixup the clocks in microwatt-compat mode (but leave resets alone
371 # so that microwatt soc.vhdl can pull a reset on the core or DMI
372 # can do it, just like in TestIssuer)
373 if self
.microwatt_compat
:
374 intclk
= ClockSignal(self
.core_domain
)
375 dbgclk
= ClockSignal(self
.dbg_domain
)
376 if self
.core_domain
!= 'sync':
377 comb
+= intclk
.eq(ClockSignal())
378 if self
.dbg_domain
!= 'sync':
379 comb
+= dbgclk
.eq(ClockSignal())
381 # drop the first 3 bits of the incoming wishbone addresses
382 # this can go if using later versions of microwatt (not now)
383 if self
.microwatt_compat
:
384 ibus
= self
.imem
.ibus
385 dbus
= self
.core
.l0
.cmpi
.wb_bus()
386 comb
+= self
.ibus_adr
.eq(Cat(Const(0, 3), ibus
.adr
))
387 comb
+= self
.dbus_adr
.eq(Cat(Const(0, 3), dbus
.adr
))
388 # microwatt verilator debug purposes
389 pi
= self
.core
.l0
.cmpi
.pi
.pi
390 comb
+= self
.ldst_req
.eq(pi
.addr_ok_o
)
391 comb
+= self
.ldst_addr
.eq(pi
.addr
)
393 cur_state
= self
.cur_state
395 # 4x 4k SRAM blocks. these simply "exist", they get routed in litex
397 for i
, sram
in enumerate(self
.sram4k
):
398 m
.submodules
["sram4k_%d" % i
] = csd(sram
)
399 comb
+= sram
.enable
.eq(self
.wb_sram_en
)
401 # terrible hack to stop a potential race condition. if core
402 # is doing any operation (at all) pause the DEC/TB FSM
403 comb
+= self
.pause_dec_tb
.eq(core
.pause_dec_tb
)
405 # XICS interrupt handler
407 m
.submodules
.xics_icp
= icp
= csd(self
.xics_icp
)
408 m
.submodules
.xics_ics
= ics
= csd(self
.xics_ics
)
409 comb
+= icp
.ics_i
.eq(ics
.icp_o
) # connect ICS to ICP
410 sync
+= cur_state
.eint
.eq(icp
.core_irq_o
) # connect ICP to core
412 sync
+= cur_state
.eint
.eq(self
.ext_irq
) # connect externally
414 # GPIO test peripheral
416 m
.submodules
.simple_gpio
= simple_gpio
= csd(self
.simple_gpio
)
418 # connect one GPIO output to ICS bit 15 (like in microwatt soc.vhdl)
419 # XXX causes litex ECP5 test to get wrong idea about input and output
420 # (but works with verilator sim *sigh*)
421 # if self.gpio and self.xics:
422 # comb += self.int_level_i[15].eq(simple_gpio.gpio_o[0])
424 # instruction decoder
425 pdecode
= create_pdecode()
426 m
.submodules
.dec2
= pdecode2
= csd(self
.pdecode2
)
428 m
.submodules
.svp64
= svp64
= csd(self
.svp64
)
430 # clock delay power-on reset
431 cd_por
= ClockDomain(reset_less
=True)
432 cd_sync
= ClockDomain()
433 m
.domains
+= cd_por
, cd_sync
434 core_sync
= ClockDomain(self
.core_domain
)
435 if self
.core_domain
!= "sync":
436 m
.domains
+= core_sync
437 if self
.dbg_domain
!= "sync":
438 dbg_sync
= ClockDomain(self
.dbg_domain
)
439 m
.domains
+= dbg_sync
441 ti_rst
= Signal(reset_less
=True)
442 delay
= Signal(range(4), reset
=3)
443 with m
.If(delay
!= 0):
444 m
.d
.por
+= delay
.eq(delay
- 1)
445 comb
+= cd_por
.clk
.eq(ClockSignal())
447 # power-on reset delay
448 core_rst
= ResetSignal(self
.core_domain
)
449 if self
.core_domain
!= "sync":
450 comb
+= ti_rst
.eq(delay
!= 0 | dbg
.core_rst_o |
ResetSignal())
451 comb
+= core_rst
.eq(ti_rst
)
453 with m
.If(delay
!= 0 | dbg
.core_rst_o
):
454 comb
+= core_rst
.eq(1)
456 # connect external reset signal to DMI Reset
457 if self
.dbg_domain
!= "sync":
458 dbg_rst
= ResetSignal(self
.dbg_domain
)
459 comb
+= dbg_rst
.eq(self
.dbg_rst_i
)
461 # busy/halted signals from core
462 core_busy_o
= ~core
.p
.o_ready | core
.n
.o_data
.busy_o
# core is busy
463 comb
+= self
.busy_o
.eq(core_busy_o
)
464 comb
+= pdecode2
.dec
.bigendian
.eq(self
.core_bigendian_i
)
466 # temporary hack: says "go" immediately for both address gen and ST
468 ldst
= core
.fus
.fus
['ldst0']
469 st_go_edge
= rising_edge(m
, ldst
.st
.rel_o
)
470 # link addr-go direct to rel
471 m
.d
.comb
+= ldst
.ad
.go_i
.eq(ldst
.ad
.rel_o
)
472 m
.d
.comb
+= ldst
.st
.go_i
.eq(st_go_edge
) # link store-go to rising rel
474 def do_dmi(self
, m
, dbg
):
475 """deals with DMI debug requests
477 currently only provides read requests for the INT regfile, CR and XER
478 it will later also deal with *writing* to these regfiles.
482 dmi
, d_reg
, d_cr
, d_xer
, = dbg
.dmi
, dbg
.d_gpr
, dbg
.d_cr
, dbg
.d_xer
484 intrf
= self
.core
.regs
.rf
['int']
485 fastrf
= self
.core
.regs
.rf
['fast']
487 with m
.If(d_reg
.req
): # request for regfile access being made
488 # TODO: error-check this
489 # XXX should this be combinatorial? sync better?
491 comb
+= self
.int_r
.ren
.eq(1 << d_reg
.addr
)
493 comb
+= self
.int_r
.addr
.eq(d_reg
.addr
)
494 comb
+= self
.int_r
.ren
.eq(1)
495 d_reg_delay
= Signal()
496 sync
+= d_reg_delay
.eq(d_reg
.req
)
497 with m
.If(d_reg_delay
):
498 # data arrives one clock later
499 comb
+= d_reg
.data
.eq(self
.int_r
.o_data
)
500 comb
+= d_reg
.ack
.eq(1)
503 with m
.If(d_fast
.req
): # request for regfile access being made
505 comb
+= self
.fast_r
.ren
.eq(1 << d_fast
.addr
)
507 comb
+= self
.fast_r
.addr
.eq(d_fast
.addr
)
508 comb
+= self
.fast_r
.ren
.eq(1)
509 d_fast_delay
= Signal()
510 sync
+= d_fast_delay
.eq(d_fast
.req
)
511 with m
.If(d_fast_delay
):
512 # data arrives one clock later
513 comb
+= d_fast
.data
.eq(self
.fast_r
.o_data
)
514 comb
+= d_fast
.ack
.eq(1)
516 # sigh same thing for CR debug
517 with m
.If(d_cr
.req
): # request for regfile access being made
518 comb
+= self
.cr_r
.ren
.eq(0b11111111) # enable all
519 d_cr_delay
= Signal()
520 sync
+= d_cr_delay
.eq(d_cr
.req
)
521 with m
.If(d_cr_delay
):
522 # data arrives one clock later
523 comb
+= d_cr
.data
.eq(self
.cr_r
.o_data
)
524 comb
+= d_cr
.ack
.eq(1)
527 with m
.If(d_xer
.req
): # request for regfile access being made
528 comb
+= self
.xer_r
.ren
.eq(0b111111) # enable all
529 d_xer_delay
= Signal()
530 sync
+= d_xer_delay
.eq(d_xer
.req
)
531 with m
.If(d_xer_delay
):
532 # data arrives one clock later
533 comb
+= d_xer
.data
.eq(self
.xer_r
.o_data
)
534 comb
+= d_xer
.ack
.eq(1)
536 def tb_dec_fsm(self
, m
, spr_dec
):
539 this is a FSM for updating either dec or tb. it runs alternately
540 DEC, TB, DEC, TB. note that SPR pipeline could have written a new
541 value to DEC, however the regfile has "passthrough" on it so this
544 see v3.0B p1097-1099 for Timeer Resource and p1065 and p1076
547 comb
, sync
= m
.d
.comb
, m
.d
.sync
548 fast_rf
= self
.core
.regs
.rf
['fast']
549 fast_r_dectb
= fast_rf
.r_ports
['issue'] # DEC/TB
550 fast_w_dectb
= fast_rf
.w_ports
['issue'] # DEC/TB
554 # initiates read of current DEC
555 with m
.State("DEC_READ"):
556 comb
+= fast_r_dectb
.addr
.eq(FastRegs
.DEC
)
557 comb
+= fast_r_dectb
.ren
.eq(1)
558 with m
.If(~self
.pause_dec_tb
):
561 # waits for DEC read to arrive (1 cycle), updates with new value
562 # respects if dec/tb writing has been paused
563 with m
.State("DEC_WRITE"):
564 with m
.If(self
.pause_dec_tb
):
565 # if paused, return to reading
569 # TODO: MSR.LPCR 32-bit decrement mode
570 comb
+= new_dec
.eq(fast_r_dectb
.o_data
- 1)
571 comb
+= fast_w_dectb
.addr
.eq(FastRegs
.DEC
)
572 comb
+= fast_w_dectb
.wen
.eq(1)
573 comb
+= fast_w_dectb
.i_data
.eq(new_dec
)
574 # copy to cur_state for decoder, for an interrupt
575 sync
+= spr_dec
.eq(new_dec
)
578 # initiates read of current TB
579 with m
.State("TB_READ"):
580 comb
+= fast_r_dectb
.addr
.eq(FastRegs
.TB
)
581 comb
+= fast_r_dectb
.ren
.eq(1)
582 with m
.If(~self
.pause_dec_tb
):
585 # waits for read TB to arrive, initiates write of current TB
586 # respects if dec/tb writing has been paused
587 with m
.State("TB_WRITE"):
588 with m
.If(self
.pause_dec_tb
):
589 # if paused, return to reading
593 comb
+= new_tb
.eq(fast_r_dectb
.o_data
+ 1)
594 comb
+= fast_w_dectb
.addr
.eq(FastRegs
.TB
)
595 comb
+= fast_w_dectb
.wen
.eq(1)
596 comb
+= fast_w_dectb
.i_data
.eq(new_tb
)
601 def elaborate(self
, platform
):
604 comb
, sync
= m
.d
.comb
, m
.d
.sync
605 cur_state
= self
.cur_state
606 pdecode2
= self
.pdecode2
609 # set up peripherals and core
610 core_rst
= self
.core_rst
611 self
.setup_peripherals(m
)
613 # reset current state if core reset requested
615 m
.d
.sync
+= self
.cur_state
.eq(0)
617 # check halted condition: requested PC to execute matches DMI stop addr
618 # and immediately stop. address of 0xffff_ffff_ffff_ffff can never
621 comb
+= halted
.eq(dbg
.stop_addr_o
== dbg
.state
.pc
)
623 comb
+= dbg
.core_stopped_i
.eq(1)
624 comb
+= dbg
.terminate_i
.eq(1)
626 # PC and instruction from I-Memory
627 comb
+= self
.pc_o
.eq(cur_state
.pc
)
628 self
.pc_changed
= Signal() # note write to PC
629 self
.msr_changed
= Signal() # note write to MSR
630 self
.sv_changed
= Signal() # note write to SVSTATE
632 # read state either from incoming override or from regfile
633 state
= CoreState("get") # current state (MSR/PC/SVSTATE)
634 state_get(m
, state
.msr
, core_rst
, self
.msr_i
,
636 self
.state_r_msr
, StateRegs
.MSR
)
637 state_get(m
, state
.pc
, core_rst
, self
.pc_i
,
639 self
.state_r_pc
, StateRegs
.PC
)
640 state_get(m
, state
.svstate
, core_rst
, self
.svstate_i
,
641 "svstate", # read SVSTATE
642 self
.state_r_sv
, StateRegs
.SVSTATE
)
644 # don't write pc every cycle
645 comb
+= self
.state_w_pc
.wen
.eq(0)
646 comb
+= self
.state_w_pc
.i_data
.eq(0)
648 # connect up debug state. note "combinatorially same" below,
649 # this is a bit naff, passing state over in the dbg class, but
650 # because it is combinatorial it achieves the desired goal
651 comb
+= dbg
.state
.eq(state
)
653 # this bit doesn't have to be in the FSM: connect up to read
654 # regfiles on demand from DMI
657 # DEC and TB inc/dec FSM. copy of DEC is put into CoreState,
658 # (which uses that in PowerDecoder2 to raise 0x900 exception)
659 self
.tb_dec_fsm(m
, cur_state
.dec
)
661 # while stopped, allow updating the MSR, PC and SVSTATE.
662 # these are mainly for debugging purposes (including DMI/JTAG)
663 with m
.If(dbg
.core_stopped_i
):
664 with m
.If(self
.pc_i
.ok
):
665 comb
+= self
.state_w_pc
.wen
.eq(1 << StateRegs
.PC
)
666 comb
+= self
.state_w_pc
.i_data
.eq(self
.pc_i
.data
)
667 sync
+= self
.pc_changed
.eq(1)
668 with m
.If(self
.msr_i
.ok
):
669 comb
+= self
.state_w_msr
.wen
.eq(1 << StateRegs
.MSR
)
670 comb
+= self
.state_w_msr
.i_data
.eq(self
.msr_i
.data
)
671 sync
+= self
.msr_changed
.eq(1)
672 with m
.If(self
.svstate_i
.ok | self
.update_svstate
):
673 with m
.If(self
.svstate_i
.ok
): # over-ride from external source
674 comb
+= self
.new_svstate
.eq(self
.svstate_i
.data
)
675 comb
+= self
.state_w_sv
.wen
.eq(1 << StateRegs
.SVSTATE
)
676 comb
+= self
.state_w_sv
.i_data
.eq(self
.new_svstate
)
677 sync
+= self
.sv_changed
.eq(1)
679 # start renaming some of the ports to match microwatt
680 if self
.microwatt_compat
:
681 self
.core
.o
.core_terminate_o
.name
= "terminated_out"
682 # names of DMI interface
683 self
.dbg
.dmi
.addr_i
.name
= 'dmi_addr'
684 self
.dbg
.dmi
.din
.name
= 'dmi_din'
685 self
.dbg
.dmi
.dout
.name
= 'dmi_dout'
686 self
.dbg
.dmi
.req_i
.name
= 'dmi_req'
687 self
.dbg
.dmi
.we_i
.name
= 'dmi_wr'
688 self
.dbg
.dmi
.ack_o
.name
= 'dmi_ack'
689 # wishbone instruction bus
690 ibus
= self
.imem
.ibus
691 ibus
.adr
.name
= 'wishbone_insn_out.adr'
692 ibus
.dat_w
.name
= 'wishbone_insn_out.dat'
693 ibus
.sel
.name
= 'wishbone_insn_out.sel'
694 ibus
.cyc
.name
= 'wishbone_insn_out.cyc'
695 ibus
.stb
.name
= 'wishbone_insn_out.stb'
696 ibus
.we
.name
= 'wishbone_insn_out.we'
697 ibus
.dat_r
.name
= 'wishbone_insn_in.dat'
698 ibus
.ack
.name
= 'wishbone_insn_in.ack'
699 ibus
.stall
.name
= 'wishbone_insn_in.stall'
701 dbus
= self
.core
.l0
.cmpi
.wb_bus()
702 dbus
.adr
.name
= 'wishbone_data_out.adr'
703 dbus
.dat_w
.name
= 'wishbone_data_out.dat'
704 dbus
.sel
.name
= 'wishbone_data_out.sel'
705 dbus
.cyc
.name
= 'wishbone_data_out.cyc'
706 dbus
.stb
.name
= 'wishbone_data_out.stb'
707 dbus
.we
.name
= 'wishbone_data_out.we'
708 dbus
.dat_r
.name
= 'wishbone_data_in.dat'
709 dbus
.ack
.name
= 'wishbone_data_in.ack'
710 dbus
.stall
.name
= 'wishbone_data_in.stall'
715 yield from self
.pc_i
.ports()
716 yield from self
.msr_i
.ports()
719 yield from self
.core
.ports()
720 yield from self
.imem
.ports()
721 yield self
.core_bigendian_i
727 def external_ports(self
):
728 if self
.microwatt_compat
:
729 ports
= [self
.core
.o
.core_terminate_o
,
731 self
.alt_reset
, # not connected yet
732 self
.nia
, self
.insn
, self
.nia_req
, self
.msr_o
,
733 self
.ldst_req
, self
.ldst_addr
,
737 ports
+= list(self
.dbg
.dmi
.ports())
738 # for dbus/ibus microwatt, exclude err btw and cti
739 for name
, sig
in self
.imem
.ibus
.fields
.items():
740 if name
not in ['err', 'bte', 'cti', 'adr']:
742 for name
, sig
in self
.core
.l0
.cmpi
.wb_bus().fields
.items():
743 if name
not in ['err', 'bte', 'cti', 'adr']:
745 # microwatt non-compliant with wishbone
746 ports
.append(self
.ibus_adr
)
747 ports
.append(self
.dbus_adr
)
750 ports
= self
.pc_i
.ports()
751 ports
= self
.msr_i
.ports()
752 ports
+= [self
.pc_o
, self
.memerr_o
, self
.core_bigendian_i
, self
.busy_o
,
756 ports
+= list(self
.jtag
.external_ports())
758 # don't add DMI if JTAG is enabled
759 ports
+= list(self
.dbg
.dmi
.ports())
761 ports
+= list(self
.imem
.ibus
.fields
.values())
762 ports
+= list(self
.core
.l0
.cmpi
.wb_bus().fields
.values())
765 for sram
in self
.sram4k
:
766 ports
+= list(sram
.bus
.fields
.values())
769 ports
+= list(self
.xics_icp
.bus
.fields
.values())
770 ports
+= list(self
.xics_ics
.bus
.fields
.values())
771 ports
.append(self
.int_level_i
)
773 ports
.append(self
.ext_irq
)
776 ports
+= list(self
.simple_gpio
.bus
.fields
.values())
777 ports
.append(self
.gpio_o
)
785 class TestIssuerInternal(TestIssuerBase
):
786 """TestIssuer - reads instructions from TestMemory and issues them
788 efficiency and speed is not the main goal here: functional correctness
789 and code clarity is. optimisations (which almost 100% interfere with
790 easy understanding) come later.
793 def fetch_fsm(self
, m
, dbg
, core
, pc
, msr
, svstate
, nia
, is_svp64_mode
,
794 fetch_pc_o_ready
, fetch_pc_i_valid
,
795 fetch_insn_o_valid
, fetch_insn_i_ready
):
798 this FSM performs fetch of raw instruction data, partial-decodes
799 it 32-bit at a time to detect SVP64 prefixes, and will optionally
800 read a 2nd 32-bit quantity if that occurs.
804 pdecode2
= self
.pdecode2
805 cur_state
= self
.cur_state
806 dec_opcode_i
= pdecode2
.dec
.raw_opcode_in
# raw opcode
808 # also note instruction fetch failed
809 if hasattr(core
, "icache"):
810 fetch_failed
= core
.icache
.i_out
.fetch_failed
813 fetch_failed
= Const(0, 1)
816 # set priv / virt mode on I-Cache, sigh
817 if isinstance(self
.imem
, ICache
):
818 comb
+= self
.imem
.i_in
.priv_mode
.eq(~msr
[MSR
.PR
])
819 comb
+= self
.imem
.i_in
.virt_mode
.eq(msr
[MSR
.IR
]) # Instr. Redir (VM)
821 with m
.FSM(name
='fetch_fsm'):
824 with m
.State("IDLE"):
825 # fetch allowed if not failed and stopped but not stepping
826 # (see dmi.py for how core_stop_o is generated)
827 with m
.If(~fetch_failed
& ~dbg
.core_stop_o
):
828 comb
+= fetch_pc_o_ready
.eq(1)
829 with m
.If(fetch_pc_i_valid
& ~pdecode2
.instr_fault
831 # instruction allowed to go: start by reading the PC
832 # capture the PC and also drop it into Insn Memory
833 # we have joined a pair of combinatorial memory
834 # lookups together. this is Generally Bad.
835 comb
+= self
.imem
.a_pc_i
.eq(pc
)
836 comb
+= self
.imem
.a_i_valid
.eq(1)
837 comb
+= self
.imem
.f_i_valid
.eq(1)
838 # transfer state to output
839 sync
+= cur_state
.pc
.eq(pc
)
840 sync
+= cur_state
.svstate
.eq(svstate
) # and svstate
841 sync
+= cur_state
.msr
.eq(msr
) # and msr
843 m
.next
= "INSN_READ" # move to "wait for bus" phase
845 # dummy pause to find out why simulation is not keeping up
846 with m
.State("INSN_READ"):
847 # when using "single-step" mode, checking dbg.stopping_o
848 # prevents progress. allow fetch to proceed once started
850 #if self.allow_overlap:
851 # stopping = dbg.stopping_o
853 # stopping: jump back to idle
856 with m
.If(self
.imem
.f_busy_o
&
857 ~pdecode2
.instr_fault
): # zzz...
858 # busy but not fetch failed: stay in wait-read
859 comb
+= self
.imem
.a_pc_i
.eq(pc
)
860 comb
+= self
.imem
.a_i_valid
.eq(1)
861 comb
+= self
.imem
.f_i_valid
.eq(1)
863 # not busy (or fetch failed!): instruction fetched
864 # when fetch failed, the instruction gets ignored
866 if hasattr(core
, "icache"):
867 # blech, icache returns actual instruction
868 insn
= self
.imem
.f_instr_o
870 # but these return raw memory
871 insn
= get_insn(self
.imem
.f_instr_o
, cur_state
.pc
)
874 # decode the SVP64 prefix, if any
875 comb
+= svp64
.raw_opcode_in
.eq(insn
)
876 comb
+= svp64
.bigendian
.eq(self
.core_bigendian_i
)
877 # pass the decoded prefix (if any) to PowerDecoder2
878 sync
+= pdecode2
.sv_rm
.eq(svp64
.svp64_rm
)
879 sync
+= pdecode2
.is_svp64_mode
.eq(is_svp64_mode
)
880 # remember whether this is a prefixed instruction,
881 # so the FSM can readily loop when VL==0
882 sync
+= is_svp64_mode
.eq(svp64
.is_svp64_mode
)
883 # calculate the address of the following instruction
884 insn_size
= Mux(svp64
.is_svp64_mode
, 8, 4)
885 sync
+= nia
.eq(cur_state
.pc
+ insn_size
)
886 with m
.If(~svp64
.is_svp64_mode
):
887 # with no prefix, store the instruction
888 # and hand it directly to the next FSM
889 sync
+= dec_opcode_i
.eq(insn
)
890 m
.next
= "INSN_READY"
892 # fetch the rest of the instruction from memory
893 comb
+= self
.imem
.a_pc_i
.eq(cur_state
.pc
+ 4)
894 comb
+= self
.imem
.a_i_valid
.eq(1)
895 comb
+= self
.imem
.f_i_valid
.eq(1)
896 m
.next
= "INSN_READ2"
898 # not SVP64 - 32-bit only
899 sync
+= nia
.eq(cur_state
.pc
+ 4)
900 sync
+= dec_opcode_i
.eq(insn
)
901 if self
.microwatt_compat
:
902 # for verilator debug purposes
903 comb
+= self
.insn
.eq(insn
)
904 comb
+= self
.nia
.eq(cur_state
.pc
)
905 comb
+= self
.msr_o
.eq(cur_state
.msr
)
906 comb
+= self
.nia_req
.eq(1)
907 m
.next
= "INSN_READY"
909 with m
.State("INSN_READ2"):
910 with m
.If(self
.imem
.f_busy_o
): # zzz...
911 # busy: stay in wait-read
912 comb
+= self
.imem
.a_i_valid
.eq(1)
913 comb
+= self
.imem
.f_i_valid
.eq(1)
915 # not busy: instruction fetched
916 if hasattr(core
, "icache"):
917 # blech, icache returns actual instruction
918 insn
= self
.imem
.f_instr_o
920 insn
= get_insn(self
.imem
.f_instr_o
, cur_state
.pc
+4)
921 sync
+= dec_opcode_i
.eq(insn
)
922 m
.next
= "INSN_READY"
923 # TODO: probably can start looking at pdecode2.rm_dec
924 # here or maybe even in INSN_READ state, if svp64_mode
925 # detected, in order to trigger - and wait for - the
928 pmode
= pdecode2
.rm_dec
.predmode
930 if pmode != SVP64PredMode.ALWAYS.value:
931 fire predicate loading FSM and wait before
934 sync += self.srcmask.eq(-1) # set to all 1s
935 sync += self.dstmask.eq(-1) # set to all 1s
936 m.next = "INSN_READY"
939 with m
.State("INSN_READY"):
940 # hand over the instruction, to be decoded
941 comb
+= fetch_insn_o_valid
.eq(1)
942 with m
.If(fetch_insn_i_ready
):
946 def fetch_predicate_fsm(self
, m
,
947 pred_insn_i_valid
, pred_insn_o_ready
,
948 pred_mask_o_valid
, pred_mask_i_ready
):
949 """fetch_predicate_fsm - obtains (constructs in the case of CR)
950 src/dest predicate masks
952 https://bugs.libre-soc.org/show_bug.cgi?id=617
953 the predicates can be read here, by using IntRegs r_ports['pred']
954 or CRRegs r_ports['pred']. in the case of CRs it will have to
955 be done through multiple reads, extracting one relevant at a time.
956 later, a faster way would be to use the 32-bit-wide CR port but
957 this is more complex decoding, here. equivalent code used in
958 ISACaller is "from openpower.decoder.isa.caller import get_predcr"
960 note: this ENTIRE FSM is not to be called when svp64 is disabled
964 pdecode2
= self
.pdecode2
965 rm_dec
= pdecode2
.rm_dec
# SVP64RMModeDecode
966 predmode
= rm_dec
.predmode
967 srcpred
, dstpred
= rm_dec
.srcpred
, rm_dec
.dstpred
968 cr_pred
, int_pred
= self
.cr_pred
, self
.int_pred
# read regfiles
969 # get src/dst step, so we can skip already used mask bits
970 cur_state
= self
.cur_state
971 srcstep
= cur_state
.svstate
.srcstep
972 dststep
= cur_state
.svstate
.dststep
973 cur_vl
= cur_state
.svstate
.vl
976 sregread
, sinvert
, sunary
, sall1s
= get_predint(m
, srcpred
, 's')
977 dregread
, dinvert
, dunary
, dall1s
= get_predint(m
, dstpred
, 'd')
978 sidx
, scrinvert
= get_predcr(m
, srcpred
, 's')
979 didx
, dcrinvert
= get_predcr(m
, dstpred
, 'd')
981 # store fetched masks, for either intpred or crpred
982 # when src/dst step is not zero, the skipped mask bits need to be
983 # shifted-out, before actually storing them in src/dest mask
984 new_srcmask
= Signal(64, reset_less
=True)
985 new_dstmask
= Signal(64, reset_less
=True)
987 with m
.FSM(name
="fetch_predicate"):
989 with m
.State("FETCH_PRED_IDLE"):
990 comb
+= pred_insn_o_ready
.eq(1)
991 with m
.If(pred_insn_i_valid
):
992 with m
.If(predmode
== SVP64PredMode
.INT
):
993 # skip fetching destination mask register, when zero
995 sync
+= new_dstmask
.eq(-1)
996 # directly go to fetch source mask register
997 # guaranteed not to be zero (otherwise predmode
998 # would be SVP64PredMode.ALWAYS, not INT)
999 comb
+= int_pred
.addr
.eq(sregread
)
1000 comb
+= int_pred
.ren
.eq(1)
1001 m
.next
= "INT_SRC_READ"
1002 # fetch destination predicate register
1004 comb
+= int_pred
.addr
.eq(dregread
)
1005 comb
+= int_pred
.ren
.eq(1)
1006 m
.next
= "INT_DST_READ"
1007 with m
.Elif(predmode
== SVP64PredMode
.CR
):
1008 # go fetch masks from the CR register file
1009 sync
+= new_srcmask
.eq(0)
1010 sync
+= new_dstmask
.eq(0)
1013 sync
+= self
.srcmask
.eq(-1)
1014 sync
+= self
.dstmask
.eq(-1)
1015 m
.next
= "FETCH_PRED_DONE"
1017 with m
.State("INT_DST_READ"):
1018 # store destination mask
1019 inv
= Repl(dinvert
, 64)
1021 # set selected mask bit for 1<<r3 mode
1022 dst_shift
= Signal(range(64))
1023 comb
+= dst_shift
.eq(self
.int_pred
.o_data
& 0b111111)
1024 sync
+= new_dstmask
.eq(1 << dst_shift
)
1026 # invert mask if requested
1027 sync
+= new_dstmask
.eq(self
.int_pred
.o_data ^ inv
)
1028 # skip fetching source mask register, when zero
1030 sync
+= new_srcmask
.eq(-1)
1031 m
.next
= "FETCH_PRED_SHIFT_MASK"
1032 # fetch source predicate register
1034 comb
+= int_pred
.addr
.eq(sregread
)
1035 comb
+= int_pred
.ren
.eq(1)
1036 m
.next
= "INT_SRC_READ"
1038 with m
.State("INT_SRC_READ"):
1040 inv
= Repl(sinvert
, 64)
1042 # set selected mask bit for 1<<r3 mode
1043 src_shift
= Signal(range(64))
1044 comb
+= src_shift
.eq(self
.int_pred
.o_data
& 0b111111)
1045 sync
+= new_srcmask
.eq(1 << src_shift
)
1047 # invert mask if requested
1048 sync
+= new_srcmask
.eq(self
.int_pred
.o_data ^ inv
)
1049 m
.next
= "FETCH_PRED_SHIFT_MASK"
1051 # fetch masks from the CR register file
1052 # implements the following loop:
1053 # idx, inv = get_predcr(mask)
1055 # for cr_idx in range(vl):
1056 # cr = crl[cr_idx + SVP64CROffs.CRPred] # takes one cycle
1058 # mask |= 1 << cr_idx
1060 with m
.State("CR_READ"):
1061 # CR index to be read, which will be ready by the next cycle
1062 cr_idx
= Signal
.like(cur_vl
, reset_less
=True)
1063 # submit the read operation to the regfile
1064 with m
.If(cr_idx
!= cur_vl
):
1065 # the CR read port is unary ...
1067 # ... in MSB0 convention ...
1068 # ren = 1 << (7 - cr_idx)
1069 # ... and with an offset:
1070 # ren = 1 << (7 - off - cr_idx)
1071 idx
= SVP64CROffs
.CRPred
+ cr_idx
1072 comb
+= cr_pred
.ren
.eq(1 << (7 - idx
))
1073 # signal data valid in the next cycle
1074 cr_read
= Signal(reset_less
=True)
1075 sync
+= cr_read
.eq(1)
1076 # load the next index
1077 sync
+= cr_idx
.eq(cr_idx
+ 1)
1080 sync
+= cr_read
.eq(0)
1081 sync
+= cr_idx
.eq(0)
1082 m
.next
= "FETCH_PRED_SHIFT_MASK"
1084 # compensate for the one cycle delay on the regfile
1085 cur_cr_idx
= Signal
.like(cur_vl
)
1086 comb
+= cur_cr_idx
.eq(cr_idx
- 1)
1087 # read the CR field, select the appropriate bit
1088 cr_field
= Signal(4)
1091 comb
+= cr_field
.eq(cr_pred
.o_data
)
1092 comb
+= scr_bit
.eq(cr_field
.bit_select(sidx
, 1)
1094 comb
+= dcr_bit
.eq(cr_field
.bit_select(didx
, 1)
1096 # set the corresponding mask bit
1097 bit_to_set
= Signal
.like(self
.srcmask
)
1098 comb
+= bit_to_set
.eq(1 << cur_cr_idx
)
1100 sync
+= new_srcmask
.eq(new_srcmask | bit_to_set
)
1102 sync
+= new_dstmask
.eq(new_dstmask | bit_to_set
)
1104 with m
.State("FETCH_PRED_SHIFT_MASK"):
1105 # shift-out skipped mask bits
1106 sync
+= self
.srcmask
.eq(new_srcmask
>> srcstep
)
1107 sync
+= self
.dstmask
.eq(new_dstmask
>> dststep
)
1108 m
.next
= "FETCH_PRED_DONE"
1110 with m
.State("FETCH_PRED_DONE"):
1111 comb
+= pred_mask_o_valid
.eq(1)
1112 with m
.If(pred_mask_i_ready
):
1113 m
.next
= "FETCH_PRED_IDLE"
1115 def issue_fsm(self
, m
, core
, nia
,
1116 dbg
, core_rst
, is_svp64_mode
,
1117 fetch_pc_o_ready
, fetch_pc_i_valid
,
1118 fetch_insn_o_valid
, fetch_insn_i_ready
,
1119 pred_insn_i_valid
, pred_insn_o_ready
,
1120 pred_mask_o_valid
, pred_mask_i_ready
,
1121 exec_insn_i_valid
, exec_insn_o_ready
,
1122 exec_pc_o_valid
, exec_pc_i_ready
):
1125 decode / issue FSM. this interacts with the "fetch" FSM
1126 through fetch_insn_ready/valid (incoming) and fetch_pc_ready/valid
1127 (outgoing). also interacts with the "execute" FSM
1128 through exec_insn_ready/valid (outgoing) and exec_pc_ready/valid
1130 SVP64 RM prefixes have already been set up by the
1131 "fetch" phase, so execute is fairly straightforward.
1136 pdecode2
= self
.pdecode2
1137 cur_state
= self
.cur_state
1138 new_svstate
= self
.new_svstate
1141 dec_opcode_i
= pdecode2
.dec
.raw_opcode_in
# raw opcode
1143 # for updating svstate (things like srcstep etc.)
1144 comb
+= new_svstate
.eq(cur_state
.svstate
)
1146 # precalculate srcstep+1 and dststep+1
1147 cur_srcstep
= cur_state
.svstate
.srcstep
1148 cur_dststep
= cur_state
.svstate
.dststep
1149 next_srcstep
= Signal
.like(cur_srcstep
)
1150 next_dststep
= Signal
.like(cur_dststep
)
1151 comb
+= next_srcstep
.eq(cur_state
.svstate
.srcstep
+1)
1152 comb
+= next_dststep
.eq(cur_state
.svstate
.dststep
+1)
1154 # note if an exception happened. in a pipelined or OoO design
1155 # this needs to be accompanied by "shadowing" (or stalling)
1156 exc_happened
= self
.core
.o
.exc_happened
1157 # also note instruction fetch failed
1158 if hasattr(core
, "icache"):
1159 fetch_failed
= core
.icache
.i_out
.fetch_failed
1161 # set to fault in decoder
1162 # update (highest priority) instruction fault
1163 rising_fetch_failed
= rising_edge(m
, fetch_failed
)
1164 with m
.If(rising_fetch_failed
):
1165 sync
+= pdecode2
.instr_fault
.eq(1)
1167 fetch_failed
= Const(0, 1)
1168 flush_needed
= False
1170 with m
.FSM(name
="issue_fsm"):
1172 # sync with the "fetch" phase which is reading the instruction
1173 # at this point, there is no instruction running, that
1174 # could inadvertently update the PC.
1175 with m
.State("ISSUE_START"):
1176 # reset instruction fault
1177 sync
+= pdecode2
.instr_fault
.eq(0)
1178 # wait on "core stop" release, before next fetch
1179 # need to do this here, in case we are in a VL==0 loop
1180 with m
.If(~dbg
.core_stop_o
& ~core_rst
):
1181 comb
+= fetch_pc_i_valid
.eq(1) # tell fetch to start
1182 with m
.If(fetch_pc_o_ready
): # fetch acknowledged us
1183 m
.next
= "INSN_WAIT"
1185 # tell core it's stopped, and acknowledge debug handshake
1186 comb
+= dbg
.core_stopped_i
.eq(1)
1187 # while stopped, allow updating SVSTATE
1188 with m
.If(self
.svstate_i
.ok
):
1189 comb
+= new_svstate
.eq(self
.svstate_i
.data
)
1190 comb
+= self
.update_svstate
.eq(1)
1191 sync
+= self
.sv_changed
.eq(1)
1193 # wait for an instruction to arrive from Fetch
1194 with m
.State("INSN_WAIT"):
1195 # when using "single-step" mode, checking dbg.stopping_o
1196 # prevents progress. allow issue to proceed once started
1198 #if self.allow_overlap:
1199 # stopping = dbg.stopping_o
1200 with m
.If(stopping
):
1201 # stopping: jump back to idle
1202 m
.next
= "ISSUE_START"
1204 # request the icache to stop asserting "failed"
1205 comb
+= core
.icache
.flush_in
.eq(1)
1206 # stop instruction fault
1207 sync
+= pdecode2
.instr_fault
.eq(0)
1209 comb
+= fetch_insn_i_ready
.eq(1)
1210 with m
.If(fetch_insn_o_valid
):
1211 # loop into ISSUE_START if it's a SVP64 instruction
1212 # and VL == 0. this because VL==0 is a for-loop
1213 # from 0 to 0 i.e. always, always a NOP.
1214 cur_vl
= cur_state
.svstate
.vl
1215 with m
.If(is_svp64_mode
& (cur_vl
== 0)):
1216 # update the PC before fetching the next instruction
1217 # since we are in a VL==0 loop, no instruction was
1218 # executed that we could be overwriting
1219 comb
+= self
.state_w_pc
.wen
.eq(1 << StateRegs
.PC
)
1220 comb
+= self
.state_w_pc
.i_data
.eq(nia
)
1221 comb
+= self
.insn_done
.eq(1)
1222 m
.next
= "ISSUE_START"
1225 m
.next
= "PRED_START" # fetching predicate
1227 m
.next
= "DECODE_SV" # skip predication
1229 with m
.State("PRED_START"):
1230 comb
+= pred_insn_i_valid
.eq(1) # tell fetch_pred to start
1231 with m
.If(pred_insn_o_ready
): # fetch_pred acknowledged us
1232 m
.next
= "MASK_WAIT"
1234 with m
.State("MASK_WAIT"):
1235 comb
+= pred_mask_i_ready
.eq(1) # ready to receive the masks
1236 with m
.If(pred_mask_o_valid
): # predication masks are ready
1237 m
.next
= "PRED_SKIP"
1239 # skip zeros in predicate
1240 with m
.State("PRED_SKIP"):
1241 with m
.If(~is_svp64_mode
):
1242 m
.next
= "DECODE_SV" # nothing to do
1245 pred_src_zero
= pdecode2
.rm_dec
.pred_sz
1246 pred_dst_zero
= pdecode2
.rm_dec
.pred_dz
1248 # new srcstep, after skipping zeros
1249 skip_srcstep
= Signal
.like(cur_srcstep
)
1250 # value to be added to the current srcstep
1251 src_delta
= Signal
.like(cur_srcstep
)
1252 # add leading zeros to srcstep, if not in zero mode
1253 with m
.If(~pred_src_zero
):
1254 # priority encoder (count leading zeros)
1255 # append guard bit, in case the mask is all zeros
1256 pri_enc_src
= PriorityEncoder(65)
1257 m
.submodules
.pri_enc_src
= pri_enc_src
1258 comb
+= pri_enc_src
.i
.eq(Cat(self
.srcmask
,
1260 comb
+= src_delta
.eq(pri_enc_src
.o
)
1261 # apply delta to srcstep
1262 comb
+= skip_srcstep
.eq(cur_srcstep
+ src_delta
)
1263 # shift-out all leading zeros from the mask
1264 # plus the leading "one" bit
1265 # TODO count leading zeros and shift-out the zero
1266 # bits, in the same step, in hardware
1267 sync
+= self
.srcmask
.eq(self
.srcmask
>> (src_delta
+1))
1269 # same as above, but for dststep
1270 skip_dststep
= Signal
.like(cur_dststep
)
1271 dst_delta
= Signal
.like(cur_dststep
)
1272 with m
.If(~pred_dst_zero
):
1273 pri_enc_dst
= PriorityEncoder(65)
1274 m
.submodules
.pri_enc_dst
= pri_enc_dst
1275 comb
+= pri_enc_dst
.i
.eq(Cat(self
.dstmask
,
1277 comb
+= dst_delta
.eq(pri_enc_dst
.o
)
1278 comb
+= skip_dststep
.eq(cur_dststep
+ dst_delta
)
1279 sync
+= self
.dstmask
.eq(self
.dstmask
>> (dst_delta
+1))
1281 # TODO: initialize mask[VL]=1 to avoid passing past VL
1282 with m
.If((skip_srcstep
>= cur_vl
) |
1283 (skip_dststep
>= cur_vl
)):
1284 # end of VL loop. Update PC and reset src/dst step
1285 comb
+= self
.state_w_pc
.wen
.eq(1 << StateRegs
.PC
)
1286 comb
+= self
.state_w_pc
.i_data
.eq(nia
)
1287 comb
+= new_svstate
.srcstep
.eq(0)
1288 comb
+= new_svstate
.dststep
.eq(0)
1289 comb
+= self
.update_svstate
.eq(1)
1290 # synchronize with the simulator
1291 comb
+= self
.insn_done
.eq(1)
1293 m
.next
= "ISSUE_START"
1295 # update new src/dst step
1296 comb
+= new_svstate
.srcstep
.eq(skip_srcstep
)
1297 comb
+= new_svstate
.dststep
.eq(skip_dststep
)
1298 comb
+= self
.update_svstate
.eq(1)
1300 m
.next
= "DECODE_SV"
1302 # pass predicate mask bits through to satellite decoders
1303 # TODO: for SIMD this will be *multiple* bits
1304 sync
+= core
.i
.sv_pred_sm
.eq(self
.srcmask
[0])
1305 sync
+= core
.i
.sv_pred_dm
.eq(self
.dstmask
[0])
1307 # after src/dst step have been updated, we are ready
1308 # to decode the instruction
1309 with m
.State("DECODE_SV"):
1310 # decode the instruction
1311 with m
.If(~fetch_failed
):
1312 sync
+= pdecode2
.instr_fault
.eq(0)
1313 sync
+= core
.i
.e
.eq(pdecode2
.e
)
1314 sync
+= core
.i
.state
.eq(cur_state
)
1315 sync
+= core
.i
.raw_insn_i
.eq(dec_opcode_i
)
1316 sync
+= core
.i
.bigendian_i
.eq(self
.core_bigendian_i
)
1318 sync
+= core
.i
.sv_rm
.eq(pdecode2
.sv_rm
)
1319 # set RA_OR_ZERO detection in satellite decoders
1320 sync
+= core
.i
.sv_a_nz
.eq(pdecode2
.sv_a_nz
)
1321 # and svp64 detection
1322 sync
+= core
.i
.is_svp64_mode
.eq(is_svp64_mode
)
1323 # and svp64 bit-rev'd ldst mode
1324 ldst_dec
= pdecode2
.use_svp64_ldst_dec
1325 sync
+= core
.i
.use_svp64_ldst_dec
.eq(ldst_dec
)
1326 # after decoding, reset any previous exception condition,
1327 # allowing it to be set again during the next execution
1328 sync
+= pdecode2
.ldst_exc
.eq(0)
1330 m
.next
= "INSN_EXECUTE" # move to "execute"
1332 # handshake with execution FSM, move to "wait" once acknowledged
1333 with m
.State("INSN_EXECUTE"):
1334 # when using "single-step" mode, checking dbg.stopping_o
1335 # prevents progress. allow execute to proceed once started
1337 #if self.allow_overlap:
1338 # stopping = dbg.stopping_o
1339 with m
.If(stopping
):
1340 # stopping: jump back to idle
1341 m
.next
= "ISSUE_START"
1343 # request the icache to stop asserting "failed"
1344 comb
+= core
.icache
.flush_in
.eq(1)
1345 # stop instruction fault
1346 sync
+= pdecode2
.instr_fault
.eq(0)
1348 comb
+= exec_insn_i_valid
.eq(1) # trigger execute
1349 with m
.If(exec_insn_o_ready
): # execute acknowledged us
1350 m
.next
= "EXECUTE_WAIT"
1352 with m
.State("EXECUTE_WAIT"):
1353 comb
+= exec_pc_i_ready
.eq(1)
1354 # see https://bugs.libre-soc.org/show_bug.cgi?id=636
1355 # the exception info needs to be blatted into
1356 # pdecode.ldst_exc, and the instruction "re-run".
1357 # when ldst_exc.happened is set, the PowerDecoder2
1358 # reacts very differently: it re-writes the instruction
1359 # with a "trap" (calls PowerDecoder2.trap()) which
1360 # will *overwrite* whatever was requested and jump the
1361 # PC to the exception address, as well as alter MSR.
1362 # nothing else needs to be done other than to note
1363 # the change of PC and MSR (and, later, SVSTATE)
1364 with m
.If(exc_happened
):
1365 mmu
= core
.fus
.get_exc("mmu0")
1366 ldst
= core
.fus
.get_exc("ldst0")
1368 with m
.If(fetch_failed
):
1369 # instruction fetch: exception is from MMU
1370 # reset instr_fault (highest priority)
1371 sync
+= pdecode2
.ldst_exc
.eq(mmu
)
1372 sync
+= pdecode2
.instr_fault
.eq(0)
1374 # request icache to stop asserting "failed"
1375 comb
+= core
.icache
.flush_in
.eq(1)
1376 with m
.If(~fetch_failed
):
1377 # otherwise assume it was a LDST exception
1378 sync
+= pdecode2
.ldst_exc
.eq(ldst
)
1380 with m
.If(exec_pc_o_valid
):
1382 # was this the last loop iteration?
1384 cur_vl
= cur_state
.svstate
.vl
1385 comb
+= is_last
.eq(next_srcstep
== cur_vl
)
1387 with m
.If(pdecode2
.instr_fault
):
1388 # reset instruction fault, try again
1389 sync
+= pdecode2
.instr_fault
.eq(0)
1390 m
.next
= "ISSUE_START"
1392 # return directly to Decode if Execute generated an
1394 with m
.Elif(pdecode2
.ldst_exc
.happened
):
1395 m
.next
= "DECODE_SV"
1397 # if MSR, PC or SVSTATE were changed by the previous
1398 # instruction, go directly back to Fetch, without
1399 # updating either MSR PC or SVSTATE
1400 with m
.Elif(self
.msr_changed | self
.pc_changed |
1402 m
.next
= "ISSUE_START"
1404 # also return to Fetch, when no output was a vector
1405 # (regardless of SRCSTEP and VL), or when the last
1406 # instruction was really the last one of the VL loop
1407 with m
.Elif((~pdecode2
.loop_continue
) | is_last
):
1408 # before going back to fetch, update the PC state
1409 # register with the NIA.
1410 # ok here we are not reading the branch unit.
1411 # TODO: this just blithely overwrites whatever
1412 # pipeline updated the PC
1413 comb
+= self
.state_w_pc
.wen
.eq(1 << StateRegs
.PC
)
1414 comb
+= self
.state_w_pc
.i_data
.eq(nia
)
1415 # reset SRCSTEP before returning to Fetch
1417 with m
.If(pdecode2
.loop_continue
):
1418 comb
+= new_svstate
.srcstep
.eq(0)
1419 comb
+= new_svstate
.dststep
.eq(0)
1420 comb
+= self
.update_svstate
.eq(1)
1422 comb
+= new_svstate
.srcstep
.eq(0)
1423 comb
+= new_svstate
.dststep
.eq(0)
1424 comb
+= self
.update_svstate
.eq(1)
1425 m
.next
= "ISSUE_START"
1427 # returning to Execute? then, first update SRCSTEP
1429 comb
+= new_svstate
.srcstep
.eq(next_srcstep
)
1430 comb
+= new_svstate
.dststep
.eq(next_dststep
)
1431 comb
+= self
.update_svstate
.eq(1)
1432 # return to mask skip loop
1433 m
.next
= "PRED_SKIP"
1436 # check if svstate needs updating: if so, write it to State Regfile
1437 with m
.If(self
.update_svstate
):
1438 sync
+= cur_state
.svstate
.eq(self
.new_svstate
) # for next clock
1440 def execute_fsm(self
, m
, core
,
1441 exec_insn_i_valid
, exec_insn_o_ready
,
1442 exec_pc_o_valid
, exec_pc_i_ready
):
1445 execute FSM. this interacts with the "issue" FSM
1446 through exec_insn_ready/valid (incoming) and exec_pc_ready/valid
1447 (outgoing). SVP64 RM prefixes have already been set up by the
1448 "issue" phase, so execute is fairly straightforward.
1454 pdecode2
= self
.pdecode2
1457 core_busy_o
= core
.n
.o_data
.busy_o
# core is busy
1458 core_ivalid_i
= core
.p
.i_valid
# instruction is valid
1460 if hasattr(core
, "icache"):
1461 fetch_failed
= core
.icache
.i_out
.fetch_failed
1463 fetch_failed
= Const(0, 1)
1465 with m
.FSM(name
="exec_fsm"):
1467 # waiting for instruction bus (stays there until not busy)
1468 with m
.State("INSN_START"):
1469 comb
+= exec_insn_o_ready
.eq(1)
1470 with m
.If(exec_insn_i_valid
):
1471 comb
+= core_ivalid_i
.eq(1) # instruction is valid/issued
1472 sync
+= self
.sv_changed
.eq(0)
1473 sync
+= self
.pc_changed
.eq(0)
1474 sync
+= self
.msr_changed
.eq(0)
1475 with m
.If(core
.p
.o_ready
): # only move if accepted
1476 m
.next
= "INSN_ACTIVE" # move to "wait completion"
1478 # instruction started: must wait till it finishes
1479 with m
.State("INSN_ACTIVE"):
1480 # note changes to MSR, PC and SVSTATE
1481 # XXX oops, really must monitor *all* State Regfile write
1482 # ports looking for changes!
1483 with m
.If(self
.state_nia
.wen
& (1 << StateRegs
.SVSTATE
)):
1484 sync
+= self
.sv_changed
.eq(1)
1485 with m
.If(self
.state_nia
.wen
& (1 << StateRegs
.MSR
)):
1486 sync
+= self
.msr_changed
.eq(1)
1487 with m
.If(self
.state_nia
.wen
& (1 << StateRegs
.PC
)):
1488 sync
+= self
.pc_changed
.eq(1)
1489 with m
.If(~core_busy_o
): # instruction done!
1490 comb
+= exec_pc_o_valid
.eq(1)
1491 with m
.If(exec_pc_i_ready
):
1492 # when finished, indicate "done".
1493 # however, if there was an exception, the instruction
1494 # is *not* yet done. this is an implementation
1495 # detail: we choose to implement exceptions by
1496 # taking the exception information from the LDST
1497 # unit, putting that *back* into the PowerDecoder2,
1498 # and *re-running the entire instruction*.
1499 # if we erroneously indicate "done" here, it is as if
1500 # there were *TWO* instructions:
1501 # 1) the failed LDST 2) a TRAP.
1502 with m
.If(~pdecode2
.ldst_exc
.happened
&
1503 ~pdecode2
.instr_fault
):
1504 comb
+= self
.insn_done
.eq(1)
1505 m
.next
= "INSN_START" # back to fetch
1506 # terminate returns directly to INSN_START
1507 with m
.If(dbg
.terminate_i
):
1508 # comb += self.insn_done.eq(1) - no because it's not
1509 m
.next
= "INSN_START" # back to fetch
1511 def elaborate(self
, platform
):
1512 m
= super().elaborate(platform
)
1514 comb
, sync
= m
.d
.comb
, m
.d
.sync
1515 cur_state
= self
.cur_state
1516 pdecode2
= self
.pdecode2
1520 # set up peripherals and core
1521 core_rst
= self
.core_rst
1523 # indicate to outside world if any FU is still executing
1524 comb
+= self
.any_busy
.eq(core
.n
.o_data
.any_busy_o
) # any FU executing
1526 # address of the next instruction, in the absence of a branch
1527 # depends on the instruction size
1530 # connect up debug signals
1531 with m
.If(core
.o
.core_terminate_o
):
1532 comb
+= dbg
.terminate_i
.eq(1)
1534 # pass the prefix mode from Fetch to Issue, so the latter can loop
1536 is_svp64_mode
= Signal()
1538 # there are *THREE^WFOUR-if-SVP64-enabled* FSMs, fetch (32/64-bit)
1539 # issue, decode/execute, now joined by "Predicate fetch/calculate".
1540 # these are the handshake signals between each
1542 # fetch FSM can run as soon as the PC is valid
1543 fetch_pc_i_valid
= Signal() # Execute tells Fetch "start next read"
1544 fetch_pc_o_ready
= Signal() # Fetch Tells SVSTATE "proceed"
1546 # fetch FSM hands over the instruction to be decoded / issued
1547 fetch_insn_o_valid
= Signal()
1548 fetch_insn_i_ready
= Signal()
1550 # predicate fetch FSM decodes and fetches the predicate
1551 pred_insn_i_valid
= Signal()
1552 pred_insn_o_ready
= Signal()
1554 # predicate fetch FSM delivers the masks
1555 pred_mask_o_valid
= Signal()
1556 pred_mask_i_ready
= Signal()
1558 # issue FSM delivers the instruction to the be executed
1559 exec_insn_i_valid
= Signal()
1560 exec_insn_o_ready
= Signal()
1562 # execute FSM, hands over the PC/SVSTATE back to the issue FSM
1563 exec_pc_o_valid
= Signal()
1564 exec_pc_i_ready
= Signal()
1566 # the FSMs here are perhaps unusual in that they detect conditions
1567 # then "hold" information, combinatorially, for the core
1568 # (as opposed to using sync - which would be on a clock's delay)
1569 # this includes the actual opcode, valid flags and so on.
1571 # Fetch, then predicate fetch, then Issue, then Execute.
1572 # Issue is where the VL for-loop # lives. the ready/valid
1573 # signalling is used to communicate between the four.
1575 self
.fetch_fsm(m
, dbg
, core
, dbg
.state
.pc
, dbg
.state
.msr
,
1576 dbg
.state
.svstate
, nia
, is_svp64_mode
,
1577 fetch_pc_o_ready
, fetch_pc_i_valid
,
1578 fetch_insn_o_valid
, fetch_insn_i_ready
)
1580 self
.issue_fsm(m
, core
, nia
,
1581 dbg
, core_rst
, is_svp64_mode
,
1582 fetch_pc_o_ready
, fetch_pc_i_valid
,
1583 fetch_insn_o_valid
, fetch_insn_i_ready
,
1584 pred_insn_i_valid
, pred_insn_o_ready
,
1585 pred_mask_o_valid
, pred_mask_i_ready
,
1586 exec_insn_i_valid
, exec_insn_o_ready
,
1587 exec_pc_o_valid
, exec_pc_i_ready
)
1590 self
.fetch_predicate_fsm(m
,
1591 pred_insn_i_valid
, pred_insn_o_ready
,
1592 pred_mask_o_valid
, pred_mask_i_ready
)
1594 self
.execute_fsm(m
, core
,
1595 exec_insn_i_valid
, exec_insn_o_ready
,
1596 exec_pc_o_valid
, exec_pc_i_ready
)
1598 # whatever was done above, over-ride it if core reset is held
1599 with m
.If(core_rst
):
1605 class TestIssuer(Elaboratable
):
1606 def __init__(self
, pspec
):
1607 self
.ti
= TestIssuerInternal(pspec
)
1608 self
.pll
= DummyPLL(instance
=True)
1610 self
.dbg_rst_i
= Signal(reset_less
=True)
1612 # PLL direct clock or not
1613 self
.pll_en
= hasattr(pspec
, "use_pll") and pspec
.use_pll
1615 self
.pll_test_o
= Signal(reset_less
=True)
1616 self
.pll_vco_o
= Signal(reset_less
=True)
1617 self
.clk_sel_i
= Signal(2, reset_less
=True)
1618 self
.ref_clk
= ClockSignal() # can't rename it but that's ok
1619 self
.pllclk_clk
= ClockSignal("pllclk")
1621 def elaborate(self
, platform
):
1625 # TestIssuer nominally runs at main clock, actually it is
1626 # all combinatorial internally except for coresync'd components
1627 m
.submodules
.ti
= ti
= self
.ti
1630 # ClockSelect runs at PLL output internal clock rate
1631 m
.submodules
.wrappll
= pll
= self
.pll
1633 # add clock domains from PLL
1634 cd_pll
= ClockDomain("pllclk")
1637 # PLL clock established. has the side-effect of running clklsel
1638 # at the PLL's speed (see DomainRenamer("pllclk") above)
1639 pllclk
= self
.pllclk_clk
1640 comb
+= pllclk
.eq(pll
.clk_pll_o
)
1642 # wire up external 24mhz to PLL
1643 #comb += pll.clk_24_i.eq(self.ref_clk)
1644 # output 18 mhz PLL test signal, and analog oscillator out
1645 comb
+= self
.pll_test_o
.eq(pll
.pll_test_o
)
1646 comb
+= self
.pll_vco_o
.eq(pll
.pll_vco_o
)
1648 # input to pll clock selection
1649 comb
+= pll
.clk_sel_i
.eq(self
.clk_sel_i
)
1651 # now wire up ResetSignals. don't mind them being in this domain
1652 pll_rst
= ResetSignal("pllclk")
1653 comb
+= pll_rst
.eq(ResetSignal())
1655 # internal clock is set to selector clock-out. has the side-effect of
1656 # running TestIssuer at this speed (see DomainRenamer("intclk") above)
1657 # debug clock runs at coresync internal clock
1658 if self
.ti
.dbg_domain
!= 'sync':
1659 cd_dbgsync
= ClockDomain("dbgsync")
1660 intclk
= ClockSignal(self
.ti
.core_domain
)
1661 dbgclk
= ClockSignal(self
.ti
.dbg_domain
)
1662 # XXX BYPASS PLL XXX
1663 # XXX BYPASS PLL XXX
1664 # XXX BYPASS PLL XXX
1666 comb
+= intclk
.eq(self
.ref_clk
)
1667 assert self
.ti
.core_domain
!= 'sync', \
1668 "cannot set core_domain to sync and use pll at the same time"
1670 if self
.ti
.core_domain
!= 'sync':
1671 comb
+= intclk
.eq(ClockSignal())
1672 if self
.ti
.dbg_domain
!= 'sync':
1673 dbgclk
= ClockSignal(self
.ti
.dbg_domain
)
1674 comb
+= dbgclk
.eq(intclk
)
1675 comb
+= self
.ti
.dbg_rst_i
.eq(self
.dbg_rst_i
)
1680 return list(self
.ti
.ports()) + list(self
.pll
.ports()) + \
1681 [ClockSignal(), ResetSignal()]
1683 def external_ports(self
):
1684 ports
= self
.ti
.external_ports()
1685 ports
.append(ClockSignal())
1686 ports
.append(ResetSignal())
1688 ports
.append(self
.clk_sel_i
)
1689 ports
.append(self
.pll
.clk_24_i
)
1690 ports
.append(self
.pll_test_o
)
1691 ports
.append(self
.pll_vco_o
)
1692 ports
.append(self
.pllclk_clk
)
1693 ports
.append(self
.ref_clk
)
1697 if __name__
== '__main__':
1698 units
= {'alu': 1, 'cr': 1, 'branch': 1, 'trap': 1, 'logical': 1,
1704 pspec
= TestMemPspec(ldst_ifacetype
='bare_wb',
1705 imem_ifacetype
='bare_wb',
1710 dut
= TestIssuer(pspec
)
1711 vl
= main(dut
, ports
=dut
.ports(), name
="test_issuer")
1713 if len(sys
.argv
) == 1:
1714 vl
= rtlil
.convert(dut
, ports
=dut
.external_ports(), name
="test_issuer")
1715 with
open("test_issuer.il", "w") as f
: