src/soc/simple/issuer.py

   1 """simple core issuer
   2
   3 not in any way intended for production use.  this runs a FSM that:
   4
   5 * reads the Program Counter from StateRegs
   6 * reads an instruction from a fixed-size Test Memory
   7 * issues it to the Simple Core
   8 * waits for it to complete
   9 * increments the PC
  10 * does it all over again
  11
  12 the purpose of this module is to verify the functional correctness
  13 of the Function Units in the absolute simplest and clearest possible
  14 way, and to at provide something that can be further incrementally
  15 improved.
  16 """
  17
  18 from nmigen import (Elaboratable, Module, Signal, ClockSignal, ResetSignal,
  19                     ClockDomain, DomainRenamer, Mux)
  20 from nmigen.cli import rtlil
  21 from nmigen.cli import main
  22 import sys
  23
  24 from soc.decoder.power_decoder import create_pdecode
  25 from soc.decoder.power_decoder2 import PowerDecode2, SVP64PrefixDecoder
  26 from soc.decoder.decode2execute1 import IssuerDecode2ToOperand
  27 from soc.decoder.decode2execute1 import Data
  28 from soc.experiment.testmem import TestMemory # test only for instructions
  29 from soc.regfile.regfiles import StateRegs, FastRegs
  30 from soc.simple.core import NonProductionCore
  31 from soc.config.test.test_loadstore import TestMemPspec
  32 from soc.config.ifetch import ConfigFetchUnit
  33 from soc.decoder.power_enums import MicrOp
  34 from soc.debug.dmi import CoreDebug, DMIInterface
  35 from soc.debug.jtag import JTAG
  36 from soc.config.pinouts import get_pinspecs
  37 from soc.config.state import CoreState
  38 from soc.interrupts.xics import XICS_ICP, XICS_ICS
  39 from soc.bus.simple_gpio import SimpleGPIO
  40 from soc.clock.select import ClockSelect
  41 from soc.clock.dummypll import DummyPLL
  42 from soc.sv.svstate import SVSTATERec
  43
  44
  45 from nmutil.util import rising_edge
  46
  47 def get_insn(f_instr_o, pc):
  48     if f_instr_o.width == 32:
  49         return f_instr_o
  50     else:
  51         # 64-bit: bit 2 of pc decides which word to select
  52         return f_instr_o.word_select(pc[2], 32)
  53
  54
  55 class TestIssuerInternal(Elaboratable):
  56     """TestIssuer - reads instructions from TestMemory and issues them
  57
  58     efficiency and speed is not the main goal here: functional correctness is.
  59     """
  60     def __init__(self, pspec):
  61
  62         # JTAG interface.  add this right at the start because if it's
  63         # added it *modifies* the pspec, by adding enable/disable signals
  64         # for parts of the rest of the core
  65         self.jtag_en = hasattr(pspec, "debug") and pspec.debug == 'jtag'
  66         if self.jtag_en:
  67             subset = {'uart', 'mtwi', 'eint', 'gpio', 'mspi0', 'mspi1',
  68                       'pwm', 'sd0', 'sdr'}
  69             self.jtag = JTAG(get_pinspecs(subset=subset))
  70             # add signals to pspec to enable/disable icache and dcache
  71             # (or data and intstruction wishbone if icache/dcache not included)
  72             # https://bugs.libre-soc.org/show_bug.cgi?id=520
  73             # TODO: do we actually care if these are not domain-synchronised?
  74             # honestly probably not.
  75             pspec.wb_icache_en = self.jtag.wb_icache_en
  76             pspec.wb_dcache_en = self.jtag.wb_dcache_en
  77
  78         # add interrupt controller?
  79         self.xics = hasattr(pspec, "xics") and pspec.xics == True
  80         if self.xics:
  81             self.xics_icp = XICS_ICP()
  82             self.xics_ics = XICS_ICS()
  83             self.int_level_i = self.xics_ics.int_level_i
  84
  85         # add GPIO peripheral?
  86         self.gpio = hasattr(pspec, "gpio") and pspec.gpio == True
  87         if self.gpio:
  88             self.simple_gpio = SimpleGPIO()
  89             self.gpio_o = self.simple_gpio.gpio_o
  90
  91         # main instruction core25
  92         self.core = core = NonProductionCore(pspec)
  93
  94         # instruction decoder.  goes into Trap Record
  95         pdecode = create_pdecode()
  96         self.cur_state = CoreState("cur") # current state (MSR/PC/EINT/SVSTATE)
  97         self.pdecode2 = PowerDecode2(pdecode, state=self.cur_state,
  98                                      opkls=IssuerDecode2ToOperand)
  99         self.svp64 = SVP64PrefixDecoder() # for decoding SVP64 prefix
 100
 101         # Test Instruction memory
 102         self.imem = ConfigFetchUnit(pspec).fu
 103         # one-row cache of instruction read
 104         self.iline = Signal(64) # one instruction line
 105         self.iprev_adr = Signal(64) # previous address: if different, do read
 106
 107         # DMI interface
 108         self.dbg = CoreDebug()
 109
 110         # instruction go/monitor
 111         self.pc_o = Signal(64, reset_less=True)
 112         self.pc_i = Data(64, "pc_i") # set "ok" to indicate "please change me"
 113         self.core_bigendian_i = Signal()
 114         self.busy_o = Signal(reset_less=True)
 115         self.memerr_o = Signal(reset_less=True)
 116
 117         # STATE regfile read /write ports for PC, MSR, SVSTATE
 118         staterf = self.core.regs.rf['state']
 119         self.state_r_pc = staterf.r_ports['cia'] # PC rd
 120         self.state_w_pc = staterf.w_ports['d_wr1'] # PC wr
 121         self.state_r_msr = staterf.r_ports['msr'] # MSR rd
 122         self.state_r_sv = staterf.r_ports['sv'] # SVSTATE rd
 123         self.state_w_sv = staterf.w_ports['sv'] # SVSTATE wr
 124
 125         # DMI interface access
 126         intrf = self.core.regs.rf['int']
 127         crrf = self.core.regs.rf['cr']
 128         xerrf = self.core.regs.rf['xer']
 129         self.int_r = intrf.r_ports['dmi'] # INT read
 130         self.cr_r = crrf.r_ports['full_cr_dbg'] # CR read
 131         self.xer_r = xerrf.r_ports['full_xer'] # XER read
 132
 133         # hack method of keeping an eye on whether branch/trap set the PC
 134         self.state_nia = self.core.regs.rf['state'].w_ports['nia']
 135         self.state_nia.wen.name = 'state_nia_wen'
 136
 137     def elaborate(self, platform):
 138         m = Module()
 139         comb, sync = m.d.comb, m.d.sync
 140
 141         m.submodules.core = core = DomainRenamer("coresync")(self.core)
 142         m.submodules.imem = imem = self.imem
 143         m.submodules.dbg = dbg = self.dbg
 144         if self.jtag_en:
 145             m.submodules.jtag = jtag = self.jtag
 146             # TODO: UART2GDB mux, here, from external pin
 147             # see https://bugs.libre-soc.org/show_bug.cgi?id=499
 148             sync += dbg.dmi.connect_to(jtag.dmi)
 149
 150         cur_state = self.cur_state
 151
 152         # XICS interrupt handler
 153         if self.xics:
 154             m.submodules.xics_icp = icp = self.xics_icp
 155             m.submodules.xics_ics = ics = self.xics_ics
 156             comb += icp.ics_i.eq(ics.icp_o)           # connect ICS to ICP
 157             sync += cur_state.eint.eq(icp.core_irq_o) # connect ICP to core
 158
 159         # GPIO test peripheral
 160         if self.gpio:
 161             m.submodules.simple_gpio = simple_gpio = self.simple_gpio
 162
 163         # connect one GPIO output to ICS bit 15 (like in microwatt soc.vhdl)
 164         # XXX causes litex ECP5 test to get wrong idea about input and output
 165         # (but works with verilator sim *sigh*)
 166         #if self.gpio and self.xics:
 167         #   comb += self.int_level_i[15].eq(simple_gpio.gpio_o[0])
 168
 169         # instruction decoder
 170         pdecode = create_pdecode()
 171         m.submodules.dec2 = pdecode2 = self.pdecode2
 172         m.submodules.svp64 = svp64 = self.svp64
 173
 174         # convenience
 175         dmi, d_reg, d_cr, d_xer, = dbg.dmi, dbg.d_gpr, dbg.d_cr, dbg.d_xer
 176         intrf = self.core.regs.rf['int']
 177
 178         # clock delay power-on reset
 179         cd_por  = ClockDomain(reset_less=True)
 180         cd_sync = ClockDomain()
 181         core_sync = ClockDomain("coresync")
 182         m.domains += cd_por, cd_sync, core_sync
 183
 184         ti_rst = Signal(reset_less=True)
 185         delay = Signal(range(4), reset=3)
 186         with m.If(delay != 0):
 187             m.d.por += delay.eq(delay - 1)
 188         comb += cd_por.clk.eq(ClockSignal())
 189
 190         # power-on reset delay
 191         core_rst = ResetSignal("coresync")
 192         comb += ti_rst.eq(delay != 0 | dbg.core_rst_o | ResetSignal())
 193         comb += core_rst.eq(ti_rst)
 194
 195         # busy/halted signals from core
 196         comb += self.busy_o.eq(core.busy_o)
 197         comb += pdecode2.dec.bigendian.eq(self.core_bigendian_i)
 198
 199         # temporary hack: says "go" immediately for both address gen and ST
 200         l0 = core.l0
 201         ldst = core.fus.fus['ldst0']
 202         st_go_edge = rising_edge(m, ldst.st.rel_o)
 203         m.d.comb += ldst.ad.go_i.eq(ldst.ad.rel_o) # link addr-go direct to rel
 204         m.d.comb += ldst.st.go_i.eq(st_go_edge) # link store-go to rising rel
 205
 206         # PC and instruction from I-Memory
 207         pc_changed = Signal() # note write to PC
 208         comb += self.pc_o.eq(cur_state.pc)
 209         ilatch = Signal(32)
 210
 211         # address of the next instruction, in the absence of a branch
 212         # depends on the instruction size
 213         nia = Signal(64, reset_less=True)
 214
 215         # read the PC
 216         pc = Signal(64, reset_less=True)
 217         pc_ok_delay = Signal()
 218         sync += pc_ok_delay.eq(~self.pc_i.ok)
 219         with m.If(self.pc_i.ok):
 220             # incoming override (start from pc_i)
 221             comb += pc.eq(self.pc_i.data)
 222         with m.Else():
 223             # otherwise read StateRegs regfile for PC...
 224             comb += self.state_r_pc.ren.eq(1<<StateRegs.PC)
 225         # ... but on a 1-clock delay
 226         with m.If(pc_ok_delay):
 227             comb += pc.eq(self.state_r_pc.data_o)
 228
 229         # don't write pc every cycle
 230         comb += self.state_w_pc.wen.eq(0)
 231         comb += self.state_w_pc.data_i.eq(0)
 232
 233         # don't read msr or svstate every cycle
 234         comb += self.state_r_sv.ren.eq(0)
 235         comb += self.state_r_msr.ren.eq(0)
 236         msr_read = Signal(reset=1)
 237         sv_read = Signal(reset=1)
 238
 239         # connect up debug signals
 240         # TODO comb += core.icache_rst_i.eq(dbg.icache_rst_o)
 241         comb += dbg.terminate_i.eq(core.core_terminate_o)
 242         comb += dbg.state.pc.eq(pc)
 243         #comb += dbg.state.pc.eq(cur_state.pc)
 244         comb += dbg.state.msr.eq(cur_state.msr)
 245
 246         # temporaries
 247         core_busy_o = core.busy_o                 # core is busy
 248         core_ivalid_i = core.ivalid_i             # instruction is valid
 249         core_issue_i = core.issue_i               # instruction is issued
 250         dec_opcode_i = pdecode2.dec.raw_opcode_in # raw opcode
 251         insn_type = core.e.do.insn_type           # instruction MicroOp type
 252
 253         # there are *TWO* FSMs, one fetch (32/64-bit) one decode/execute.
 254         # these are the handshake signals between fetch and decode/execute
 255
 256         # fetch FSM can run as soon as the PC is valid
 257         fetch_pc_valid_i = Signal()
 258         fetch_pc_ready_o = Signal()
 259         # when done, deliver the instruction to the next FSM
 260         fetch_insn_valid_o = Signal()
 261         fetch_insn_ready_i = Signal()
 262
 263         # latches copy of raw fetched instruction
 264         fetch_insn_o = Signal(32, reset_less=True)
 265
 266         # actually use a nmigen FSM for the first time (w00t)
 267         # this FSM is perhaps unusual in that it detects conditions
 268         # then "holds" information, combinatorially, for the core
 269         # (as opposed to using sync - which would be on a clock's delay)
 270         # this includes the actual opcode, valid flags and so on.
 271
 272         # this FSM performs fetch of raw instruction data, partial-decodes
 273         # it 32-bit at a time to detect SVP64 prefixes, and will optionally
 274         # read a 2nd 32-bit quantity if that occurs.
 275
 276         with m.FSM(name='fetch_fsm'):
 277
 278             # waiting (zzz)
 279             with m.State("IDLE"):
 280                 with m.If(~dbg.core_stop_o & ~core_rst):
 281                     comb += fetch_pc_ready_o.eq(1)
 282                     with m.If(fetch_pc_valid_i):
 283                         # instruction allowed to go: start by reading the PC
 284                         # capture the PC and also drop it into Insn Memory
 285                         # we have joined a pair of combinatorial memory
 286                         # lookups together.  this is Generally Bad.
 287                         comb += self.imem.a_pc_i.eq(pc)
 288                         comb += self.imem.a_valid_i.eq(1)
 289                         comb += self.imem.f_valid_i.eq(1)
 290                         sync += cur_state.pc.eq(pc)
 291
 292                         # initiate read of MSR/SVSTATE. arrives one clock later
 293                         comb += self.state_r_msr.ren.eq(1 << StateRegs.MSR)
 294                         comb += self.state_r_sv.ren.eq(1 << StateRegs.SVSTATE)
 295                         sync += msr_read.eq(0)
 296                         sync += sv_read.eq(0)
 297
 298                         m.next = "INSN_READ"  # move to "wait for bus" phase
 299                 with m.Else():
 300                     comb += core.core_stopped_i.eq(1)
 301                     comb += dbg.core_stopped_i.eq(1)
 302
 303             # dummy pause to find out why simulation is not keeping up
 304             with m.State("INSN_READ"):
 305                 # one cycle later, msr/sv read arrives.  valid only once.
 306                 with m.If(~msr_read):
 307                     sync += msr_read.eq(1) # yeah don't read it again
 308                     sync += cur_state.msr.eq(self.state_r_msr.data_o)
 309                 with m.If(~sv_read):
 310                     sync += sv_read.eq(1) # yeah don't read it again
 311                     sync += cur_state.svstate.eq(self.state_r_sv.data_o)
 312                 with m.If(self.imem.f_busy_o): # zzz...
 313                     # busy: stay in wait-read
 314                     comb += self.imem.a_valid_i.eq(1)
 315                     comb += self.imem.f_valid_i.eq(1)
 316                 with m.Else():
 317                     # not busy: instruction fetched
 318                     insn = get_insn(self.imem.f_instr_o, cur_state.pc)
 319                     # decode the SVP64 prefix, if any
 320                     comb += svp64.raw_opcode_in.eq(insn)
 321                     comb += svp64.bigendian.eq(self.core_bigendian_i)
 322                     # pass the decoded prefix (if any) to PowerDecoder2
 323                     sync += pdecode2.sv_rm.eq(svp64.svp64_rm)
 324                     # calculate the address of the following instruction
 325                     insn_size = Mux(svp64.is_svp64_mode, 8, 4)
 326                     sync += nia.eq(cur_state.pc + insn_size)
 327                     with m.If(~svp64.is_svp64_mode):
 328                         # with no prefix, store the instruction
 329                         # and hand it directly to the next FSM
 330                         sync += fetch_insn_o.eq(insn)
 331                         m.next = "INSN_READY"
 332                     with m.Else():
 333                         # fetch the rest of the instruction from memory
 334                         comb += self.imem.a_pc_i.eq(cur_state.pc + 4)
 335                         comb += self.imem.a_valid_i.eq(1)
 336                         comb += self.imem.f_valid_i.eq(1)
 337                         m.next = "INSN_READ2"
 338
 339             with m.State("INSN_READ2"):
 340                 with m.If(self.imem.f_busy_o):  # zzz...
 341                     # busy: stay in wait-read
 342                     comb += self.imem.a_valid_i.eq(1)
 343                     comb += self.imem.f_valid_i.eq(1)
 344                 with m.Else():
 345                     # not busy: instruction fetched
 346                     insn = get_insn(self.imem.f_instr_o, cur_state.pc+4)
 347                     sync += fetch_insn_o.eq(insn)
 348                     m.next = "INSN_READY"
 349
 350             with m.State("INSN_READY"):
 351                 # hand over the instruction, to be decoded
 352                 comb += fetch_insn_valid_o.eq(1)
 353                 with m.If(fetch_insn_ready_i):
 354                     m.next = "IDLE"
 355
 356         # decode / issue / execute FSM.  this interacts with the "fetch" FSM
 357         # through fetch_pc_ready/valid (incoming) and fetch_insn_ready/valid
 358         # (outgoing).  SVP64 RM prefixes have already been set up by the
 359         # "fetch" phase, so execute is fairly straightforward.
 360
 361         with m.FSM():
 362
 363             # go fetch the instruction at the current PC
 364             # at this point, there is no instruction running, that
 365             # could inadvertently update the PC.
 366             with m.State("INSN_FETCH"):
 367                 comb += fetch_pc_valid_i.eq(1)
 368                 with m.If(fetch_pc_ready_o):
 369                     m.next = "INSN_WAIT"
 370
 371             # decode the instruction when it arrives
 372             with m.State("INSN_WAIT"):
 373                 comb += fetch_insn_ready_i.eq(1)
 374                 with m.If(fetch_insn_valid_o):
 375                     # decode the instruction
 376                     comb += dec_opcode_i.eq(fetch_insn_o)  # actual opcode
 377                     sync += core.e.eq(pdecode2.e)
 378                     sync += core.state.eq(cur_state)
 379                     sync += core.raw_insn_i.eq(dec_opcode_i)
 380                     sync += core.bigendian_i.eq(self.core_bigendian_i)
 381                     sync += ilatch.eq(insn) # latch current insn
 382                     # also drop PC and MSR into decode "state"
 383                     m.next = "INSN_START" # move to "start"
 384
 385             # waiting for instruction bus (stays there until not busy)
 386             with m.State("INSN_START"):
 387                 comb += core_ivalid_i.eq(1) # instruction is valid
 388                 comb += core_issue_i.eq(1)  # and issued
 389                 sync += pc_changed.eq(0)
 390
 391                 m.next = "INSN_ACTIVE" # move to "wait completion"
 392
 393             # instruction started: must wait till it finishes
 394             with m.State("INSN_ACTIVE"):
 395                 with m.If(insn_type != MicrOp.OP_NOP):
 396                     comb += core_ivalid_i.eq(1) # instruction is valid
 397                 with m.If(self.state_nia.wen & (1<<StateRegs.PC)):
 398                     sync += pc_changed.eq(1)
 399                 with m.If(~core_busy_o): # instruction done!
 400                     # ok here we are not reading the branch unit.  TODO
 401                     # this just blithely overwrites whatever pipeline
 402                     # updated the PC
 403                     with m.If(~pc_changed):
 404                         comb += self.state_w_pc.wen.eq(1<<StateRegs.PC)
 405                         comb += self.state_w_pc.data_i.eq(nia)
 406                     sync += core.e.eq(0)
 407                     sync += core.raw_insn_i.eq(0)
 408                     sync += core.bigendian_i.eq(0)
 409                     m.next = "INSN_FETCH"  # back to fetch
 410
 411         # for updating svstate (things like srcstep etc.)
 412         update_svstate = Signal() # TODO: move this somewhere above
 413         new_svstate = SVSSTATERec("new_svstate") # and move this as well
 414         # check if svstate needs updating: if so, write it to State Regfile
 415         with m.If(update_svstate):
 416             comb += self.state_w_sv.wen.eq(1<<StateRegs.SVSTATE)
 417             comb += self.state_w_sv.data_i.eq(new_svstate)
 418
 419         # this bit doesn't have to be in the FSM: connect up to read
 420         # regfiles on demand from DMI
 421         with m.If(d_reg.req): # request for regfile access being made
 422             # TODO: error-check this
 423             # XXX should this be combinatorial?  sync better?
 424             if intrf.unary:
 425                 comb += self.int_r.ren.eq(1<<d_reg.addr)
 426             else:
 427                 comb += self.int_r.addr.eq(d_reg.addr)
 428                 comb += self.int_r.ren.eq(1)
 429         d_reg_delay  = Signal()
 430         sync += d_reg_delay.eq(d_reg.req)
 431         with m.If(d_reg_delay):
 432             # data arrives one clock later
 433             comb += d_reg.data.eq(self.int_r.data_o)
 434             comb += d_reg.ack.eq(1)
 435
 436         # sigh same thing for CR debug
 437         with m.If(d_cr.req): # request for regfile access being made
 438             comb += self.cr_r.ren.eq(0b11111111) # enable all
 439         d_cr_delay  = Signal()
 440         sync += d_cr_delay.eq(d_cr.req)
 441         with m.If(d_cr_delay):
 442             # data arrives one clock later
 443             comb += d_cr.data.eq(self.cr_r.data_o)
 444             comb += d_cr.ack.eq(1)
 445
 446         # aaand XER...
 447         with m.If(d_xer.req): # request for regfile access being made
 448             comb += self.xer_r.ren.eq(0b111111) # enable all
 449         d_xer_delay  = Signal()
 450         sync += d_xer_delay.eq(d_xer.req)
 451         with m.If(d_xer_delay):
 452             # data arrives one clock later
 453             comb += d_xer.data.eq(self.xer_r.data_o)
 454             comb += d_xer.ack.eq(1)
 455
 456         # DEC and TB inc/dec FSM.  copy of DEC is put into CoreState,
 457         # (which uses that in PowerDecoder2 to raise 0x900 exception)
 458         self.tb_dec_fsm(m, cur_state.dec)
 459
 460         return m
 461
 462     def tb_dec_fsm(self, m, spr_dec):
 463         """tb_dec_fsm
 464
 465         this is a FSM for updating either dec or tb.  it runs alternately
 466         DEC, TB, DEC, TB.  note that SPR pipeline could have written a new
 467         value to DEC, however the regfile has "passthrough" on it so this
 468         *should* be ok.
 469
 470         see v3.0B p1097-1099 for Timeer Resource and p1065 and p1076
 471         """
 472
 473         comb, sync = m.d.comb, m.d.sync
 474         fast_rf = self.core.regs.rf['fast']
 475         fast_r_dectb = fast_rf.r_ports['issue'] # DEC/TB
 476         fast_w_dectb = fast_rf.w_ports['issue'] # DEC/TB
 477
 478         with m.FSM() as fsm:
 479
 480             # initiates read of current DEC
 481             with m.State("DEC_READ"):
 482                 comb += fast_r_dectb.addr.eq(FastRegs.DEC)
 483                 comb += fast_r_dectb.ren.eq(1)
 484                 m.next = "DEC_WRITE"
 485
 486             # waits for DEC read to arrive (1 cycle), updates with new value
 487             with m.State("DEC_WRITE"):
 488                 new_dec = Signal(64)
 489                 # TODO: MSR.LPCR 32-bit decrement mode
 490                 comb += new_dec.eq(fast_r_dectb.data_o - 1)
 491                 comb += fast_w_dectb.addr.eq(FastRegs.DEC)
 492                 comb += fast_w_dectb.wen.eq(1)
 493                 comb += fast_w_dectb.data_i.eq(new_dec)
 494                 sync += spr_dec.eq(new_dec) # copy into cur_state for decoder
 495                 m.next = "TB_READ"
 496
 497             # initiates read of current TB
 498             with m.State("TB_READ"):
 499                 comb += fast_r_dectb.addr.eq(FastRegs.TB)
 500                 comb += fast_r_dectb.ren.eq(1)
 501                 m.next = "TB_WRITE"
 502
 503             # waits for read TB to arrive, initiates write of current TB
 504             with m.State("TB_WRITE"):
 505                 new_tb = Signal(64)
 506                 comb += new_tb.eq(fast_r_dectb.data_o + 1)
 507                 comb += fast_w_dectb.addr.eq(FastRegs.TB)
 508                 comb += fast_w_dectb.wen.eq(1)
 509                 comb += fast_w_dectb.data_i.eq(new_tb)
 510                 m.next = "DEC_READ"
 511
 512         return m
 513
 514     def __iter__(self):
 515         yield from self.pc_i.ports()
 516         yield self.pc_o
 517         yield self.memerr_o
 518         yield from self.core.ports()
 519         yield from self.imem.ports()
 520         yield self.core_bigendian_i
 521         yield self.busy_o
 522
 523     def ports(self):
 524         return list(self)
 525
 526     def external_ports(self):
 527         ports = self.pc_i.ports()
 528         ports += [self.pc_o, self.memerr_o, self.core_bigendian_i, self.busy_o,
 529                 ]
 530
 531         if self.jtag_en:
 532             ports += list(self.jtag.external_ports())
 533         else:
 534             # don't add DMI if JTAG is enabled
 535             ports += list(self.dbg.dmi.ports())
 536
 537         ports += list(self.imem.ibus.fields.values())
 538         ports += list(self.core.l0.cmpi.lsmem.lsi.slavebus.fields.values())
 539
 540         if self.xics:
 541             ports += list(self.xics_icp.bus.fields.values())
 542             ports += list(self.xics_ics.bus.fields.values())
 543             ports.append(self.int_level_i)
 544
 545         if self.gpio:
 546             ports += list(self.simple_gpio.bus.fields.values())
 547             ports.append(self.gpio_o)
 548
 549         return ports
 550
 551     def ports(self):
 552         return list(self)
 553
 554
 555 class TestIssuer(Elaboratable):
 556     def __init__(self, pspec):
 557         self.ti = TestIssuerInternal(pspec)
 558
 559         self.pll = DummyPLL()
 560
 561         # PLL direct clock or not
 562         self.pll_en = hasattr(pspec, "use_pll") and pspec.use_pll
 563         if self.pll_en:
 564             self.pll_18_o = Signal(reset_less=True)
 565
 566     def elaborate(self, platform):
 567         m = Module()
 568         comb = m.d.comb
 569
 570         # TestIssuer runs at direct clock
 571         m.submodules.ti = ti = self.ti
 572         cd_int = ClockDomain("coresync")
 573
 574         if self.pll_en:
 575             # ClockSelect runs at PLL output internal clock rate
 576             m.submodules.pll = pll = self.pll
 577
 578             # add clock domains from PLL
 579             cd_pll = ClockDomain("pllclk")
 580             m.domains += cd_pll
 581
 582             # PLL clock established.  has the side-effect of running clklsel
 583             # at the PLL's speed (see DomainRenamer("pllclk") above)
 584             pllclk = ClockSignal("pllclk")
 585             comb += pllclk.eq(pll.clk_pll_o)
 586
 587             # wire up external 24mhz to PLL
 588             comb += pll.clk_24_i.eq(ClockSignal())
 589
 590             # output 18 mhz PLL test signal
 591             comb += self.pll_18_o.eq(pll.pll_18_o)
 592
 593             # now wire up ResetSignals.  don't mind them being in this domain
 594             pll_rst = ResetSignal("pllclk")
 595             comb += pll_rst.eq(ResetSignal())
 596
 597         # internal clock is set to selector clock-out.  has the side-effect of
 598         # running TestIssuer at this speed (see DomainRenamer("intclk") above)
 599         intclk = ClockSignal("coresync")
 600         if self.pll_en:
 601             comb += intclk.eq(pll.clk_pll_o)
 602         else:
 603             comb += intclk.eq(ClockSignal())
 604
 605         return m
 606
 607     def ports(self):
 608         return list(self.ti.ports()) + list(self.pll.ports()) + \
 609                [ClockSignal(), ResetSignal()]
 610
 611     def external_ports(self):
 612         ports = self.ti.external_ports()
 613         ports.append(ClockSignal())
 614         ports.append(ResetSignal())
 615         if self.pll_en:
 616             ports.append(self.pll.clk_sel_i)
 617             ports.append(self.pll_18_o)
 618             ports.append(self.pll.pll_lck_o)
 619         return ports
 620
 621
 622 if __name__ == '__main__':
 623     units = {'alu': 1, 'cr': 1, 'branch': 1, 'trap': 1, 'logical': 1,
 624              'spr': 1,
 625              'div': 1,
 626              'mul': 1,
 627              'shiftrot': 1
 628             }
 629     pspec = TestMemPspec(ldst_ifacetype='bare_wb',
 630                          imem_ifacetype='bare_wb',
 631                          addr_wid=48,
 632                          mask_wid=8,
 633                          reg_wid=64,
 634                          units=units)
 635     dut = TestIssuer(pspec)
 636     vl = main(dut, ports=dut.ports(), name="test_issuer")
 637
 638     if len(sys.argv) == 1:
 639         vl = rtlil.convert(dut, ports=dut.external_ports(), name="test_issuer")
 640         with open("test_issuer.il", "w") as f:
 641             f.write(vl)