src/soc/simple/issuer.py

   1 """simple core issuer
   2
   3 not in any way intended for production use.  this runs a FSM that:
   4
   5 * reads the Program Counter from StateRegs
   6 * reads an instruction from a fixed-size Test Memory
   7 * issues it to the Simple Core
   8 * waits for it to complete
   9 * increments the PC
  10 * does it all over again
  11
  12 the purpose of this module is to verify the functional correctness
  13 of the Function Units in the absolute simplest and clearest possible
  14 way, and to at provide something that can be further incrementally
  15 improved.
  16 """
  17
  18 from nmigen import (Elaboratable, Module, Signal, ClockSignal, ResetSignal,
  19                     ClockDomain, DomainRenamer, Mux, Const)
  20 from nmigen.cli import rtlil
  21 from nmigen.cli import main
  22 import sys
  23
  24 from soc.decoder.power_decoder import create_pdecode
  25 from soc.decoder.power_decoder2 import PowerDecode2, SVP64PrefixDecoder
  26 from soc.decoder.decode2execute1 import IssuerDecode2ToOperand
  27 from soc.decoder.decode2execute1 import Data
  28 from soc.experiment.testmem import TestMemory # test only for instructions
  29 from soc.regfile.regfiles import StateRegs, FastRegs
  30 from soc.simple.core import NonProductionCore
  31 from soc.config.test.test_loadstore import TestMemPspec
  32 from soc.config.ifetch import ConfigFetchUnit
  33 from soc.decoder.power_enums import MicrOp
  34 from soc.debug.dmi import CoreDebug, DMIInterface
  35 from soc.debug.jtag import JTAG
  36 from soc.config.pinouts import get_pinspecs
  37 from soc.config.state import CoreState
  38 from soc.interrupts.xics import XICS_ICP, XICS_ICS
  39 from soc.bus.simple_gpio import SimpleGPIO
  40 from soc.bus.SPBlock512W64B8W import SPBlock512W64B8W
  41 from soc.clock.select import ClockSelect
  42 from soc.clock.dummypll import DummyPLL
  43 from soc.sv.svstate import SVSTATERec
  44
  45
  46 from nmutil.util import rising_edge
  47
  48 def get_insn(f_instr_o, pc):
  49     if f_instr_o.width == 32:
  50         return f_instr_o
  51     else:
  52         # 64-bit: bit 2 of pc decides which word to select
  53         return f_instr_o.word_select(pc[2], 32)
  54
  55
  56 class TestIssuerInternal(Elaboratable):
  57     """TestIssuer - reads instructions from TestMemory and issues them
  58
  59     efficiency and speed is not the main goal here: functional correctness is.
  60     """
  61     def __init__(self, pspec):
  62
  63         # test is SVP64 is to be enabled
  64         self.svp64_en = hasattr(pspec, "svp64") and (pspec.svp64 == True)
  65
  66         # JTAG interface.  add this right at the start because if it's
  67         # added it *modifies* the pspec, by adding enable/disable signals
  68         # for parts of the rest of the core
  69         self.jtag_en = hasattr(pspec, "debug") and pspec.debug == 'jtag'
  70         if self.jtag_en:
  71             subset = {'uart', 'mtwi', 'eint', 'gpio', 'mspi0', 'mspi1',
  72                       'pwm', 'sd0', 'sdr'}
  73             self.jtag = JTAG(get_pinspecs(subset=subset))
  74             # add signals to pspec to enable/disable icache and dcache
  75             # (or data and intstruction wishbone if icache/dcache not included)
  76             # https://bugs.libre-soc.org/show_bug.cgi?id=520
  77             # TODO: do we actually care if these are not domain-synchronised?
  78             # honestly probably not.
  79             pspec.wb_icache_en = self.jtag.wb_icache_en
  80             pspec.wb_dcache_en = self.jtag.wb_dcache_en
  81             self.wb_sram_en = self.jtag.wb_sram_en
  82         else:
  83             self.wb_sram_en = Const(1)
  84
  85         # add 4k sram blocks?
  86         self.sram4x4k = (hasattr(pspec, "sram4x4kblock") and
  87                          pspec.sram4x4kblock == True)
  88         if self.sram4x4k:
  89             self.sram4k = []
  90             for i in range(4):
  91                 self.sram4k.append(SPBlock512W64B8W(name="sram4k_%d" % i,
  92                                                     features={'err'}))
  93
  94         # add interrupt controller?
  95         self.xics = hasattr(pspec, "xics") and pspec.xics == True
  96         if self.xics:
  97             self.xics_icp = XICS_ICP()
  98             self.xics_ics = XICS_ICS()
  99             self.int_level_i = self.xics_ics.int_level_i
 100
 101         # add GPIO peripheral?
 102         self.gpio = hasattr(pspec, "gpio") and pspec.gpio == True
 103         if self.gpio:
 104             self.simple_gpio = SimpleGPIO()
 105             self.gpio_o = self.simple_gpio.gpio_o
 106
 107         # main instruction core25
 108         self.core = core = NonProductionCore(pspec)
 109
 110         # instruction decoder.  goes into Trap Record
 111         pdecode = create_pdecode()
 112         self.cur_state = CoreState("cur") # current state (MSR/PC/EINT/SVSTATE)
 113         self.pdecode2 = PowerDecode2(pdecode, state=self.cur_state,
 114                                      opkls=IssuerDecode2ToOperand,
 115                                      svp64_en=self.svp64_en)
 116         if self.svp64_en:
 117             self.svp64 = SVP64PrefixDecoder() # for decoding SVP64 prefix
 118
 119         # Test Instruction memory
 120         self.imem = ConfigFetchUnit(pspec).fu
 121         # one-row cache of instruction read
 122         self.iline = Signal(64) # one instruction line
 123         self.iprev_adr = Signal(64) # previous address: if different, do read
 124
 125         # DMI interface
 126         self.dbg = CoreDebug()
 127
 128         # instruction go/monitor
 129         self.pc_o = Signal(64, reset_less=True)
 130         self.pc_i = Data(64, "pc_i") # set "ok" to indicate "please change me"
 131         self.svstate_i = Data(32, "svstate_i") # ditto
 132         self.core_bigendian_i = Signal()
 133         self.busy_o = Signal(reset_less=True)
 134         self.memerr_o = Signal(reset_less=True)
 135
 136         # STATE regfile read /write ports for PC, MSR, SVSTATE
 137         staterf = self.core.regs.rf['state']
 138         self.state_r_pc = staterf.r_ports['cia'] # PC rd
 139         self.state_w_pc = staterf.w_ports['d_wr1'] # PC wr
 140         self.state_r_msr = staterf.r_ports['msr'] # MSR rd
 141         self.state_r_sv = staterf.r_ports['sv'] # SVSTATE rd
 142         self.state_w_sv = staterf.w_ports['sv'] # SVSTATE wr
 143
 144         # DMI interface access
 145         intrf = self.core.regs.rf['int']
 146         crrf = self.core.regs.rf['cr']
 147         xerrf = self.core.regs.rf['xer']
 148         self.int_r = intrf.r_ports['dmi'] # INT read
 149         self.cr_r = crrf.r_ports['full_cr_dbg'] # CR read
 150         self.xer_r = xerrf.r_ports['full_xer'] # XER read
 151
 152         # hack method of keeping an eye on whether branch/trap set the PC
 153         self.state_nia = self.core.regs.rf['state'].w_ports['nia']
 154         self.state_nia.wen.name = 'state_nia_wen'
 155
 156         # pulse to synchronize the simulator at instruction end
 157         self.insn_done = Signal()
 158
 159     def fetch_fsm(self, m, core, pc, svstate, nia,
 160                         fetch_pc_ready_o, fetch_pc_valid_i,
 161                         fetch_insn_valid_o, fetch_insn_ready_i):
 162         """fetch FSM
 163         this FSM performs fetch of raw instruction data, partial-decodes
 164         it 32-bit at a time to detect SVP64 prefixes, and will optionally
 165         read a 2nd 32-bit quantity if that occurs.
 166         """
 167         comb = m.d.comb
 168         sync = m.d.sync
 169         pdecode2 = self.pdecode2
 170         cur_state = self.cur_state
 171         dec_opcode_i = pdecode2.dec.raw_opcode_in # raw opcode
 172
 173         msr_read = Signal(reset=1)
 174
 175         with m.FSM(name='fetch_fsm'):
 176
 177             # waiting (zzz)
 178             with m.State("IDLE"):
 179                 comb += fetch_pc_ready_o.eq(1)
 180                 with m.If(fetch_pc_valid_i):
 181                     # instruction allowed to go: start by reading the PC
 182                     # capture the PC and also drop it into Insn Memory
 183                     # we have joined a pair of combinatorial memory
 184                     # lookups together.  this is Generally Bad.
 185                     comb += self.imem.a_pc_i.eq(pc)
 186                     comb += self.imem.a_valid_i.eq(1)
 187                     comb += self.imem.f_valid_i.eq(1)
 188                     sync += cur_state.pc.eq(pc)
 189                     sync += cur_state.svstate.eq(svstate) # and svstate
 190
 191                     # initiate read of MSR. arrives one clock later
 192                     comb += self.state_r_msr.ren.eq(1 << StateRegs.MSR)
 193                     sync += msr_read.eq(0)
 194
 195                     m.next = "INSN_READ"  # move to "wait for bus" phase
 196
 197             # dummy pause to find out why simulation is not keeping up
 198             with m.State("INSN_READ"):
 199                 # one cycle later, msr/sv read arrives.  valid only once.
 200                 with m.If(~msr_read):
 201                     sync += msr_read.eq(1) # yeah don't read it again
 202                     sync += cur_state.msr.eq(self.state_r_msr.data_o)
 203                 with m.If(self.imem.f_busy_o): # zzz...
 204                     # busy: stay in wait-read
 205                     comb += self.imem.a_valid_i.eq(1)
 206                     comb += self.imem.f_valid_i.eq(1)
 207                 with m.Else():
 208                     # not busy: instruction fetched
 209                     insn = get_insn(self.imem.f_instr_o, cur_state.pc)
 210                     if self.svp64_en:
 211                         svp64 = self.svp64
 212                         # decode the SVP64 prefix, if any
 213                         comb += svp64.raw_opcode_in.eq(insn)
 214                         comb += svp64.bigendian.eq(self.core_bigendian_i)
 215                         # pass the decoded prefix (if any) to PowerDecoder2
 216                         sync += pdecode2.sv_rm.eq(svp64.svp64_rm)
 217                         # calculate the address of the following instruction
 218                         insn_size = Mux(svp64.is_svp64_mode, 8, 4)
 219                         sync += nia.eq(cur_state.pc + insn_size)
 220                         with m.If(~svp64.is_svp64_mode):
 221                             # with no prefix, store the instruction
 222                             # and hand it directly to the next FSM
 223                             sync += dec_opcode_i.eq(insn)
 224                             m.next = "INSN_READY"
 225                         with m.Else():
 226                             # fetch the rest of the instruction from memory
 227                             comb += self.imem.a_pc_i.eq(cur_state.pc + 4)
 228                             comb += self.imem.a_valid_i.eq(1)
 229                             comb += self.imem.f_valid_i.eq(1)
 230                             m.next = "INSN_READ2"
 231                     else:
 232                         # not SVP64 - 32-bit only
 233                         sync += nia.eq(cur_state.pc + 4)
 234                         sync += dec_opcode_i.eq(insn)
 235                         m.next = "INSN_READY"
 236
 237             with m.State("INSN_READ2"):
 238                 with m.If(self.imem.f_busy_o):  # zzz...
 239                     # busy: stay in wait-read
 240                     comb += self.imem.a_valid_i.eq(1)
 241                     comb += self.imem.f_valid_i.eq(1)
 242                 with m.Else():
 243                     # not busy: instruction fetched
 244                     insn = get_insn(self.imem.f_instr_o, cur_state.pc+4)
 245                     sync += dec_opcode_i.eq(insn)
 246                     m.next = "INSN_READY"
 247
 248             with m.State("INSN_READY"):
 249                 # hand over the instruction, to be decoded
 250                 comb += fetch_insn_valid_o.eq(1)
 251                 with m.If(fetch_insn_ready_i):
 252                     m.next = "IDLE"
 253
 254     def issue_fsm(self, m, core, pc_changed, sv_changed, nia,
 255                   dbg, core_rst,
 256                   fetch_pc_ready_o, fetch_pc_valid_i,
 257                   fetch_insn_valid_o, fetch_insn_ready_i,
 258                   exec_insn_valid_i, exec_insn_ready_o,
 259                   exec_pc_valid_o, exec_pc_ready_i):
 260         """issue FSM
 261
 262         decode / issue FSM.  this interacts with the "fetch" FSM
 263         through fetch_insn_ready/valid (incoming) and fetch_pc_ready/valid
 264         (outgoing). also interacts with the "execute" FSM
 265         through exec_insn_ready/valid (outgoing) and exec_pc_ready/valid
 266         (incoming).
 267         SVP64 RM prefixes have already been set up by the
 268         "fetch" phase, so execute is fairly straightforward.
 269         """
 270
 271         comb = m.d.comb
 272         sync = m.d.sync
 273         pdecode2 = self.pdecode2
 274         cur_state = self.cur_state
 275
 276         # temporaries
 277         dec_opcode_i = pdecode2.dec.raw_opcode_in # raw opcode
 278
 279         # for updating svstate (things like srcstep etc.)
 280         update_svstate = Signal() # set this (below) if updating
 281         new_svstate = SVSTATERec("new_svstate")
 282         comb += new_svstate.eq(cur_state.svstate)
 283
 284         with m.FSM(name="issue_fsm"):
 285
 286             # go fetch the instruction at the current PC
 287             # at this point, there is no instruction running, that
 288             # could inadvertently update the PC.
 289             with m.State("INSN_FETCH"):
 290                 # wait on "core stop" release, before next fetch
 291                 # need to do this here, in case we are in a VL==0 loop
 292                 with m.If(~dbg.core_stop_o & ~core_rst):
 293                     comb += fetch_pc_valid_i.eq(1)
 294                     with m.If(fetch_pc_ready_o):
 295                         m.next = "INSN_WAIT"
 296                 with m.Else():
 297                     comb += core.core_stopped_i.eq(1)
 298                     comb += dbg.core_stopped_i.eq(1)
 299                     # while stopped, allow updating the PC and SVSTATE
 300                     with m.If(self.pc_i.ok):
 301                         comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
 302                         comb += self.state_w_pc.data_i.eq(self.pc_i.data)
 303                         sync += pc_changed.eq(1)
 304                     with m.If(self.svstate_i.ok):
 305                         comb += new_svstate.eq(self.svstate_i.data)
 306                         comb += update_svstate.eq(1)
 307                         sync += sv_changed.eq(1)
 308
 309             # decode the instruction when it arrives
 310             with m.State("INSN_WAIT"):
 311                 comb += fetch_insn_ready_i.eq(1)
 312                 with m.If(fetch_insn_valid_o):
 313                     # decode the instruction
 314                     sync += core.e.eq(pdecode2.e)
 315                     sync += core.state.eq(cur_state)
 316                     sync += core.raw_insn_i.eq(dec_opcode_i)
 317                     sync += core.bigendian_i.eq(self.core_bigendian_i)
 318                     # set RA_OR_ZERO detection in satellite decoders
 319                     sync += core.sv_a_nz.eq(pdecode2.sv_a_nz)
 320                     # loop into INSN_FETCH if it's a vector instruction
 321                     # and VL == 0.  this because VL==0 is a for-loop
 322                     # from 0 to 0 i.e. always, always a NOP.
 323                     cur_vl = cur_state.svstate.vl
 324                     with m.If(~pdecode2.no_out_vec & (cur_vl == 0)):
 325                         # update the PC before fetching the next instruction
 326                         # since we are in a VL==0 loop, no instruction was
 327                         # executed that we could be overwriting
 328                         comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
 329                         comb += self.state_w_pc.data_i.eq(nia)
 330                         comb += self.insn_done.eq(1)
 331                         m.next = "INSN_FETCH"
 332                     with m.Else():
 333                         m.next = "INSN_EXECUTE"  # move to "execute"
 334
 335             with m.State("INSN_EXECUTE"):
 336                 comb += exec_insn_valid_i.eq(1)
 337                 with m.If(exec_insn_ready_o):
 338                     m.next = "EXECUTE_WAIT"
 339
 340             with m.State("EXECUTE_WAIT"):
 341                 # wait on "core stop" release, at instruction end
 342                 # need to do this here, in case we are in a VL>1 loop
 343                 with m.If(~dbg.core_stop_o & ~core_rst):
 344                     comb += exec_pc_ready_i.eq(1)
 345                     with m.If(exec_pc_valid_o):
 346                         # precalculate srcstep+1
 347                         next_srcstep = Signal.like(cur_state.svstate.srcstep)
 348                         comb += next_srcstep.eq(cur_state.svstate.srcstep+1)
 349                         # was this the last loop iteration?
 350                         is_last = Signal()
 351                         cur_vl = cur_state.svstate.vl
 352                         comb += is_last.eq(next_srcstep == cur_vl)
 353
 354                         # if either PC or SVSTATE were changed by the previous
 355                         # instruction, go directly back to Fetch, without
 356                         # updating either PC or SVSTATE
 357                         with m.If(pc_changed | sv_changed):
 358                             m.next = "INSN_FETCH"
 359
 360                         # also return to Fetch, when no output was a vector
 361                         # (regardless of SRCSTEP and VL), or when the last
 362                         # instruction was really the last one of the VL loop
 363                         with m.Elif(pdecode2.no_out_vec | is_last):
 364                             # before going back to fetch, update the PC state
 365                             # register with the NIA.
 366                             # ok here we are not reading the branch unit.
 367                             # TODO: this just blithely overwrites whatever
 368                             #       pipeline updated the PC
 369                             comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
 370                             comb += self.state_w_pc.data_i.eq(nia)
 371                             # reset SRCSTEP before returning to Fetch
 372                             with m.If(~pdecode2.no_out_vec):
 373                                 comb += new_svstate.srcstep.eq(0)
 374                                 comb += update_svstate.eq(1)
 375                             m.next = "INSN_FETCH"
 376
 377                         # returning to Execute? then, first update SRCSTEP
 378                         with m.Else():
 379                             comb += new_svstate.srcstep.eq(next_srcstep)
 380                             comb += update_svstate.eq(1)
 381                             m.next = "DECODE_SV"
 382
 383                 with m.Else():
 384                     comb += core.core_stopped_i.eq(1)
 385                     comb += dbg.core_stopped_i.eq(1)
 386                     # while stopped, allow updating the PC and SVSTATE
 387                     with m.If(self.pc_i.ok):
 388                         comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
 389                         comb += self.state_w_pc.data_i.eq(self.pc_i.data)
 390                         sync += pc_changed.eq(1)
 391                     with m.If(self.svstate_i.ok):
 392                         comb += new_svstate.eq(self.svstate_i.data)
 393                         comb += update_svstate.eq(1)
 394                         sync += sv_changed.eq(1)
 395
 396             # need to decode the instruction again, after updating SRCSTEP
 397             # in the previous state.
 398             # mostly a copy of INSN_WAIT, but without the actual wait
 399             with m.State("DECODE_SV"):
 400                 # decode the instruction
 401                 sync += core.e.eq(pdecode2.e)
 402                 sync += core.state.eq(cur_state)
 403                 sync += core.bigendian_i.eq(self.core_bigendian_i)
 404                 sync += core.sv_a_nz.eq(pdecode2.sv_a_nz)
 405                 m.next = "INSN_EXECUTE"  # move to "execute"
 406
 407         # check if svstate needs updating: if so, write it to State Regfile
 408         with m.If(update_svstate):
 409             comb += self.state_w_sv.wen.eq(1<<StateRegs.SVSTATE)
 410             comb += self.state_w_sv.data_i.eq(new_svstate)
 411             sync += cur_state.svstate.eq(new_svstate) # for next clock
 412
 413     def execute_fsm(self, m, core, pc_changed, sv_changed,
 414                     exec_insn_valid_i, exec_insn_ready_o,
 415                     exec_pc_valid_o, exec_pc_ready_i):
 416         """execute FSM
 417
 418         execute FSM. this interacts with the "issue" FSM
 419         through exec_insn_ready/valid (incoming) and exec_pc_ready/valid
 420         (outgoing). SVP64 RM prefixes have already been set up by the
 421         "issue" phase, so execute is fairly straightforward.
 422         """
 423
 424         comb = m.d.comb
 425         sync = m.d.sync
 426         pdecode2 = self.pdecode2
 427
 428         # temporaries
 429         core_busy_o = core.busy_o                 # core is busy
 430         core_ivalid_i = core.ivalid_i             # instruction is valid
 431         core_issue_i = core.issue_i               # instruction is issued
 432         insn_type = core.e.do.insn_type           # instruction MicroOp type
 433
 434         with m.FSM(name="exec_fsm"):
 435
 436             # waiting for instruction bus (stays there until not busy)
 437             with m.State("INSN_START"):
 438                 comb += exec_insn_ready_o.eq(1)
 439                 with m.If(exec_insn_valid_i):
 440                     comb += core_ivalid_i.eq(1)  # instruction is valid
 441                     comb += core_issue_i.eq(1)  # and issued
 442                     sync += sv_changed.eq(0)
 443                     sync += pc_changed.eq(0)
 444                     m.next = "INSN_ACTIVE"  # move to "wait completion"
 445
 446             # instruction started: must wait till it finishes
 447             with m.State("INSN_ACTIVE"):
 448                 with m.If(insn_type != MicrOp.OP_NOP):
 449                     comb += core_ivalid_i.eq(1) # instruction is valid
 450                 # note changes to PC and SVSTATE
 451                 with m.If(self.state_nia.wen & (1<<StateRegs.SVSTATE)):
 452                     sync += sv_changed.eq(1)
 453                 with m.If(self.state_nia.wen & (1<<StateRegs.PC)):
 454                     sync += pc_changed.eq(1)
 455                 with m.If(~core_busy_o): # instruction done!
 456                     comb += exec_pc_valid_o.eq(1)
 457                     with m.If(exec_pc_ready_i):
 458                         comb += self.insn_done.eq(1)
 459                         m.next = "INSN_START"  # back to fetch
 460
 461     def elaborate(self, platform):
 462         m = Module()
 463         comb, sync = m.d.comb, m.d.sync
 464
 465         m.submodules.core = core = DomainRenamer("coresync")(self.core)
 466         m.submodules.imem = imem = self.imem
 467         m.submodules.dbg = dbg = self.dbg
 468         if self.jtag_en:
 469             m.submodules.jtag = jtag = self.jtag
 470             # TODO: UART2GDB mux, here, from external pin
 471             # see https://bugs.libre-soc.org/show_bug.cgi?id=499
 472             sync += dbg.dmi.connect_to(jtag.dmi)
 473
 474         cur_state = self.cur_state
 475
 476         # 4x 4k SRAM blocks.  these simply "exist", they get routed in litex
 477         if self.sram4x4k:
 478             for i, sram in enumerate(self.sram4k):
 479                 m.submodules["sram4k_%d" % i] = sram
 480                 comb += sram.enable.eq(self.wb_sram_en)
 481
 482         # XICS interrupt handler
 483         if self.xics:
 484             m.submodules.xics_icp = icp = self.xics_icp
 485             m.submodules.xics_ics = ics = self.xics_ics
 486             comb += icp.ics_i.eq(ics.icp_o)           # connect ICS to ICP
 487             sync += cur_state.eint.eq(icp.core_irq_o) # connect ICP to core
 488
 489         # GPIO test peripheral
 490         if self.gpio:
 491             m.submodules.simple_gpio = simple_gpio = self.simple_gpio
 492
 493         # connect one GPIO output to ICS bit 15 (like in microwatt soc.vhdl)
 494         # XXX causes litex ECP5 test to get wrong idea about input and output
 495         # (but works with verilator sim *sigh*)
 496         #if self.gpio and self.xics:
 497         #   comb += self.int_level_i[15].eq(simple_gpio.gpio_o[0])
 498
 499         # instruction decoder
 500         pdecode = create_pdecode()
 501         m.submodules.dec2 = pdecode2 = self.pdecode2
 502         if self.svp64_en:
 503             m.submodules.svp64 = svp64 = self.svp64
 504
 505         # convenience
 506         dmi, d_reg, d_cr, d_xer, = dbg.dmi, dbg.d_gpr, dbg.d_cr, dbg.d_xer
 507         intrf = self.core.regs.rf['int']
 508
 509         # clock delay power-on reset
 510         cd_por  = ClockDomain(reset_less=True)
 511         cd_sync = ClockDomain()
 512         core_sync = ClockDomain("coresync")
 513         m.domains += cd_por, cd_sync, core_sync
 514
 515         ti_rst = Signal(reset_less=True)
 516         delay = Signal(range(4), reset=3)
 517         with m.If(delay != 0):
 518             m.d.por += delay.eq(delay - 1)
 519         comb += cd_por.clk.eq(ClockSignal())
 520
 521         # power-on reset delay
 522         core_rst = ResetSignal("coresync")
 523         comb += ti_rst.eq(delay != 0 | dbg.core_rst_o | ResetSignal())
 524         comb += core_rst.eq(ti_rst)
 525
 526         # busy/halted signals from core
 527         comb += self.busy_o.eq(core.busy_o)
 528         comb += pdecode2.dec.bigendian.eq(self.core_bigendian_i)
 529
 530         # temporary hack: says "go" immediately for both address gen and ST
 531         l0 = core.l0
 532         ldst = core.fus.fus['ldst0']
 533         st_go_edge = rising_edge(m, ldst.st.rel_o)
 534         m.d.comb += ldst.ad.go_i.eq(ldst.ad.rel_o) # link addr-go direct to rel
 535         m.d.comb += ldst.st.go_i.eq(st_go_edge) # link store-go to rising rel
 536
 537         # PC and instruction from I-Memory
 538         comb += self.pc_o.eq(cur_state.pc)
 539         pc_changed = Signal() # note write to PC
 540         sv_changed = Signal() # note write to SVSTATE
 541
 542         # read the PC
 543         pc = Signal(64, reset_less=True)
 544         pc_ok_delay = Signal()
 545         sync += pc_ok_delay.eq(~self.pc_i.ok)
 546         with m.If(self.pc_i.ok):
 547             # incoming override (start from pc_i)
 548             comb += pc.eq(self.pc_i.data)
 549         with m.Else():
 550             # otherwise read StateRegs regfile for PC...
 551             comb += self.state_r_pc.ren.eq(1<<StateRegs.PC)
 552         # ... but on a 1-clock delay
 553         with m.If(pc_ok_delay):
 554             comb += pc.eq(self.state_r_pc.data_o)
 555
 556         # read svstate
 557         svstate = Signal(64, reset_less=True)
 558         svstate_ok_delay = Signal()
 559         sync += svstate_ok_delay.eq(~self.svstate_i.ok)
 560         with m.If(self.svstate_i.ok):
 561             # incoming override (start from svstate__i)
 562             comb += svstate.eq(self.svstate_i.data)
 563         with m.Else():
 564             # otherwise read StateRegs regfile for SVSTATE...
 565             comb += self.state_r_sv.ren.eq(1 << StateRegs.SVSTATE)
 566         # ... but on a 1-clock delay
 567         with m.If(svstate_ok_delay):
 568             comb += svstate.eq(self.state_r_sv.data_o)
 569
 570         # don't write pc every cycle
 571         comb += self.state_w_pc.wen.eq(0)
 572         comb += self.state_w_pc.data_i.eq(0)
 573
 574         # don't read msr every cycle
 575         comb += self.state_r_msr.ren.eq(0)
 576
 577         # address of the next instruction, in the absence of a branch
 578         # depends on the instruction size
 579         nia = Signal(64, reset_less=True)
 580
 581         # connect up debug signals
 582         # TODO comb += core.icache_rst_i.eq(dbg.icache_rst_o)
 583         comb += dbg.terminate_i.eq(core.core_terminate_o)
 584         comb += dbg.state.pc.eq(pc)
 585         comb += dbg.state.svstate.eq(svstate)
 586         comb += dbg.state.msr.eq(cur_state.msr)
 587
 588         # there are *THREE* FSMs, fetch (32/64-bit) issue, decode/execute.
 589         # these are the handshake signals between fetch and decode/execute
 590
 591         # fetch FSM can run as soon as the PC is valid
 592         fetch_pc_valid_i = Signal() # Execute tells Fetch "start next read"
 593         fetch_pc_ready_o = Signal() # Fetch Tells SVSTATE "proceed"
 594
 595         # fetch FSM hands over the instruction to be decoded / issued
 596         fetch_insn_valid_o = Signal()
 597         fetch_insn_ready_i = Signal()
 598
 599         # issue FSM delivers the instruction to the be executed
 600         exec_insn_valid_i = Signal()
 601         exec_insn_ready_o = Signal()
 602
 603         # execute FSM, hands over the PC/SVSTATE back to the issue FSM
 604         exec_pc_valid_o = Signal()
 605         exec_pc_ready_i = Signal()
 606
 607         # the FSMs here are perhaps unusual in that they detect conditions
 608         # then "hold" information, combinatorially, for the core
 609         # (as opposed to using sync - which would be on a clock's delay)
 610         # this includes the actual opcode, valid flags and so on.
 611
 612         # Fetch, then Issue, then Execute. Issue is where the VL for-loop
 613         # lives.  the ready/valid signalling is used to communicate between
 614         # the three.
 615
 616         self.fetch_fsm(m, core, pc, svstate, nia,
 617                        fetch_pc_ready_o, fetch_pc_valid_i,
 618                        fetch_insn_valid_o, fetch_insn_ready_i)
 619
 620         self.issue_fsm(m, core, pc_changed, sv_changed, nia,
 621                        dbg, core_rst,
 622                        fetch_pc_ready_o, fetch_pc_valid_i,
 623                        fetch_insn_valid_o, fetch_insn_ready_i,
 624                        exec_insn_valid_i, exec_insn_ready_o,
 625                        exec_pc_valid_o, exec_pc_ready_i)
 626
 627         self.execute_fsm(m, core, pc_changed, sv_changed,
 628                          exec_insn_valid_i, exec_insn_ready_o,
 629                          exec_pc_valid_o, exec_pc_ready_i)
 630
 631         # this bit doesn't have to be in the FSM: connect up to read
 632         # regfiles on demand from DMI
 633         self.do_dmi(m, dbg)
 634
 635         # DEC and TB inc/dec FSM.  copy of DEC is put into CoreState,
 636         # (which uses that in PowerDecoder2 to raise 0x900 exception)
 637         self.tb_dec_fsm(m, cur_state.dec)
 638
 639         return m
 640
 641     def do_dmi(self, m, dbg):
 642         comb = m.d.comb
 643         sync = m.d.sync
 644         dmi, d_reg, d_cr, d_xer, = dbg.dmi, dbg.d_gpr, dbg.d_cr, dbg.d_xer
 645         intrf = self.core.regs.rf['int']
 646
 647         with m.If(d_reg.req): # request for regfile access being made
 648             # TODO: error-check this
 649             # XXX should this be combinatorial?  sync better?
 650             if intrf.unary:
 651                 comb += self.int_r.ren.eq(1<<d_reg.addr)
 652             else:
 653                 comb += self.int_r.addr.eq(d_reg.addr)
 654                 comb += self.int_r.ren.eq(1)
 655         d_reg_delay  = Signal()
 656         sync += d_reg_delay.eq(d_reg.req)
 657         with m.If(d_reg_delay):
 658             # data arrives one clock later
 659             comb += d_reg.data.eq(self.int_r.data_o)
 660             comb += d_reg.ack.eq(1)
 661
 662         # sigh same thing for CR debug
 663         with m.If(d_cr.req): # request for regfile access being made
 664             comb += self.cr_r.ren.eq(0b11111111) # enable all
 665         d_cr_delay  = Signal()
 666         sync += d_cr_delay.eq(d_cr.req)
 667         with m.If(d_cr_delay):
 668             # data arrives one clock later
 669             comb += d_cr.data.eq(self.cr_r.data_o)
 670             comb += d_cr.ack.eq(1)
 671
 672         # aaand XER...
 673         with m.If(d_xer.req): # request for regfile access being made
 674             comb += self.xer_r.ren.eq(0b111111) # enable all
 675         d_xer_delay  = Signal()
 676         sync += d_xer_delay.eq(d_xer.req)
 677         with m.If(d_xer_delay):
 678             # data arrives one clock later
 679             comb += d_xer.data.eq(self.xer_r.data_o)
 680             comb += d_xer.ack.eq(1)
 681
 682     def tb_dec_fsm(self, m, spr_dec):
 683         """tb_dec_fsm
 684
 685         this is a FSM for updating either dec or tb.  it runs alternately
 686         DEC, TB, DEC, TB.  note that SPR pipeline could have written a new
 687         value to DEC, however the regfile has "passthrough" on it so this
 688         *should* be ok.
 689
 690         see v3.0B p1097-1099 for Timeer Resource and p1065 and p1076
 691         """
 692
 693         comb, sync = m.d.comb, m.d.sync
 694         fast_rf = self.core.regs.rf['fast']
 695         fast_r_dectb = fast_rf.r_ports['issue'] # DEC/TB
 696         fast_w_dectb = fast_rf.w_ports['issue'] # DEC/TB
 697
 698         with m.FSM() as fsm:
 699
 700             # initiates read of current DEC
 701             with m.State("DEC_READ"):
 702                 comb += fast_r_dectb.addr.eq(FastRegs.DEC)
 703                 comb += fast_r_dectb.ren.eq(1)
 704                 m.next = "DEC_WRITE"
 705
 706             # waits for DEC read to arrive (1 cycle), updates with new value
 707             with m.State("DEC_WRITE"):
 708                 new_dec = Signal(64)
 709                 # TODO: MSR.LPCR 32-bit decrement mode
 710                 comb += new_dec.eq(fast_r_dectb.data_o - 1)
 711                 comb += fast_w_dectb.addr.eq(FastRegs.DEC)
 712                 comb += fast_w_dectb.wen.eq(1)
 713                 comb += fast_w_dectb.data_i.eq(new_dec)
 714                 sync += spr_dec.eq(new_dec) # copy into cur_state for decoder
 715                 m.next = "TB_READ"
 716
 717             # initiates read of current TB
 718             with m.State("TB_READ"):
 719                 comb += fast_r_dectb.addr.eq(FastRegs.TB)
 720                 comb += fast_r_dectb.ren.eq(1)
 721                 m.next = "TB_WRITE"
 722
 723             # waits for read TB to arrive, initiates write of current TB
 724             with m.State("TB_WRITE"):
 725                 new_tb = Signal(64)
 726                 comb += new_tb.eq(fast_r_dectb.data_o + 1)
 727                 comb += fast_w_dectb.addr.eq(FastRegs.TB)
 728                 comb += fast_w_dectb.wen.eq(1)
 729                 comb += fast_w_dectb.data_i.eq(new_tb)
 730                 m.next = "DEC_READ"
 731
 732         return m
 733
 734     def __iter__(self):
 735         yield from self.pc_i.ports()
 736         yield self.pc_o
 737         yield self.memerr_o
 738         yield from self.core.ports()
 739         yield from self.imem.ports()
 740         yield self.core_bigendian_i
 741         yield self.busy_o
 742
 743     def ports(self):
 744         return list(self)
 745
 746     def external_ports(self):
 747         ports = self.pc_i.ports()
 748         ports += [self.pc_o, self.memerr_o, self.core_bigendian_i, self.busy_o,
 749                 ]
 750
 751         if self.jtag_en:
 752             ports += list(self.jtag.external_ports())
 753         else:
 754             # don't add DMI if JTAG is enabled
 755             ports += list(self.dbg.dmi.ports())
 756
 757         ports += list(self.imem.ibus.fields.values())
 758         ports += list(self.core.l0.cmpi.lsmem.lsi.slavebus.fields.values())
 759
 760         if self.sram4x4k:
 761             for sram in self.sram4k:
 762                 ports += list(sram.bus.fields.values())
 763
 764         if self.xics:
 765             ports += list(self.xics_icp.bus.fields.values())
 766             ports += list(self.xics_ics.bus.fields.values())
 767             ports.append(self.int_level_i)
 768
 769         if self.gpio:
 770             ports += list(self.simple_gpio.bus.fields.values())
 771             ports.append(self.gpio_o)
 772
 773         return ports
 774
 775     def ports(self):
 776         return list(self)
 777
 778
 779 class TestIssuer(Elaboratable):
 780     def __init__(self, pspec):
 781         self.ti = TestIssuerInternal(pspec)
 782
 783         self.pll = DummyPLL()
 784
 785         # PLL direct clock or not
 786         self.pll_en = hasattr(pspec, "use_pll") and pspec.use_pll
 787         if self.pll_en:
 788             self.pll_18_o = Signal(reset_less=True)
 789
 790     def elaborate(self, platform):
 791         m = Module()
 792         comb = m.d.comb
 793
 794         # TestIssuer runs at direct clock
 795         m.submodules.ti = ti = self.ti
 796         cd_int = ClockDomain("coresync")
 797
 798         if self.pll_en:
 799             # ClockSelect runs at PLL output internal clock rate
 800             m.submodules.pll = pll = self.pll
 801
 802             # add clock domains from PLL
 803             cd_pll = ClockDomain("pllclk")
 804             m.domains += cd_pll
 805
 806             # PLL clock established.  has the side-effect of running clklsel
 807             # at the PLL's speed (see DomainRenamer("pllclk") above)
 808             pllclk = ClockSignal("pllclk")
 809             comb += pllclk.eq(pll.clk_pll_o)
 810
 811             # wire up external 24mhz to PLL
 812             comb += pll.clk_24_i.eq(ClockSignal())
 813
 814             # output 18 mhz PLL test signal
 815             comb += self.pll_18_o.eq(pll.pll_18_o)
 816
 817             # now wire up ResetSignals.  don't mind them being in this domain
 818             pll_rst = ResetSignal("pllclk")
 819             comb += pll_rst.eq(ResetSignal())
 820
 821         # internal clock is set to selector clock-out.  has the side-effect of
 822         # running TestIssuer at this speed (see DomainRenamer("intclk") above)
 823         intclk = ClockSignal("coresync")
 824         if self.pll_en:
 825             comb += intclk.eq(pll.clk_pll_o)
 826         else:
 827             comb += intclk.eq(ClockSignal())
 828
 829         return m
 830
 831     def ports(self):
 832         return list(self.ti.ports()) + list(self.pll.ports()) + \
 833                [ClockSignal(), ResetSignal()]
 834
 835     def external_ports(self):
 836         ports = self.ti.external_ports()
 837         ports.append(ClockSignal())
 838         ports.append(ResetSignal())
 839         if self.pll_en:
 840             ports.append(self.pll.clk_sel_i)
 841             ports.append(self.pll_18_o)
 842             ports.append(self.pll.pll_lck_o)
 843         return ports
 844
 845
 846 if __name__ == '__main__':
 847     units = {'alu': 1, 'cr': 1, 'branch': 1, 'trap': 1, 'logical': 1,
 848              'spr': 1,
 849              'div': 1,
 850              'mul': 1,
 851              'shiftrot': 1
 852             }
 853     pspec = TestMemPspec(ldst_ifacetype='bare_wb',
 854                          imem_ifacetype='bare_wb',
 855                          addr_wid=48,
 856                          mask_wid=8,
 857                          reg_wid=64,
 858                          units=units)
 859     dut = TestIssuer(pspec)
 860     vl = main(dut, ports=dut.ports(), name="test_issuer")
 861
 862     if len(sys.argv) == 1:
 863         vl = rtlil.convert(dut, ports=dut.external_ports(), name="test_issuer")
 864         with open("test_issuer.il", "w") as f:
 865             f.write(vl)