1 """simple core issuer verilog generator
5 from nmigen
.cli
import verilog
7 from soc
.config
.test
.test_loadstore
import TestMemPspec
8 from soc
.simple
.issuer
import TestIssuer
11 if __name__
== '__main__':
12 parser
= argparse
.ArgumentParser(description
="Simple core issuer " \
14 parser
.add_argument("output_filename")
15 parser
.add_argument("--enable-xics", dest
='xics', action
="store_true",
16 help="Enable interrupts",
18 parser
.add_argument("--disable-xics", dest
='xics', action
="store_false",
19 help="Disable interrupts",
21 parser
.add_argument("--enable-lessports", dest
='lessports',
23 help="Enable less regfile ports",
25 parser
.add_argument("--disable-lessports", dest
='lessports',
27 help="enable more regfile ports",
29 parser
.add_argument("--enable-core", dest
='core', action
="store_true",
30 help="Enable main core",
32 parser
.add_argument("--disable-core", dest
='core', action
="store_false",
33 help="disable main core",
35 parser
.add_argument("--enable-mmu", dest
='mmu', action
="store_true",
38 parser
.add_argument("--disable-mmu", dest
='mmu', action
="store_false",
41 parser
.add_argument("--enable-pll", dest
='pll', action
="store_true",
44 parser
.add_argument("--disable-pll", dest
='pll', action
="store_false",
47 parser
.add_argument("--enable-testgpio", action
="store_true",
48 help="Disable gpio pins",
50 parser
.add_argument("--enable-sram4x4kblock", action
="store_true",
51 help="Disable sram 4x4k block",
53 parser
.add_argument("--debug", default
="jtag", help="Select debug " \
54 "interface [jtag | dmi] [default jtag]")
55 parser
.add_argument("--enable-svp64", dest
='svp64', action
="store_true",
58 parser
.add_argument("--disable-svp64", dest
='svp64', action
="store_false",
62 args
= parser
.parse_args()
67 'cr': 1, 'branch': 1, 'trap': 1,
75 units
['mmu'] = 1 # enable MMU
77 # decide which memory type to configure
79 ldst_ifacetype
= 'mmu_cache_wb'
81 ldst_ifacetype
= 'bare_wb'
82 imem_ifacetype
= 'bare_wb'
84 pspec
= TestMemPspec(ldst_ifacetype
=ldst_ifacetype
,
85 imem_ifacetype
=imem_ifacetype
,
90 # set to 32 for instruction-memory width=32
92 # set to 32 to make data wishbone bus 32-bit
94 xics
=args
.xics
, # XICS interrupt controller
95 nocore
=not args
.core
, # test coriolis2 ioring
96 regreduce
= args
.lessports
, # less regfile ports
97 use_pll
=args
.pll
, # bypass PLL
98 gpio
=args
.enable_testgpio
, # for test purposes
99 sram4x4kblock
=args
.enable_sram4x4kblock
, # add SRAMs
100 debug
=args
.debug
, # set to jtag or dmi
101 svp64
=args
.svp64
, # enable SVP64
102 mmu
=args
.mmu
, # enable MMU
105 print("mmu", pspec
.__dict
__["mmu"])
106 print("nocore", pspec
.__dict
__["nocore"])
107 print("regreduce", pspec
.__dict
__["regreduce"])
108 print("gpio", pspec
.__dict
__["gpio"])
109 print("sram4x4kblock", pspec
.__dict
__["sram4x4kblock"])
110 print("xics", pspec
.__dict
__["xics"])
111 print("use_pll", pspec
.__dict
__["use_pll"])
112 print("debug", pspec
.__dict
__["debug"])
113 print("SVP64", pspec
.__dict
__["svp64"])
115 dut
= TestIssuer(pspec
)
117 vl
= verilog
.convert(dut
, ports
=dut
.external_ports(), name
="test_issuer")
118 with
open(args
.output_filename
, "w") as f
: