1 """simple core issuer verilog generator
5 from nmigen
.cli
import verilog
7 from soc
.config
.test
.test_loadstore
import TestMemPspec
8 from soc
.simple
.issuer
import TestIssuer
11 if __name__
== '__main__':
12 units
= {'alu': 1, 'cr': 1, 'branch': 1, 'trap': 1, 'logical': 1,
17 pspec
= TestMemPspec(ldst_ifacetype
='bare_wb',
18 imem_ifacetype
='bare_wb',
23 # set to 32 for instruction-memory width=32
26 dut
= TestIssuer(pspec
)
28 vl
= verilog
.convert(dut
, ports
=dut
.external_ports(), name
="test_issuer")
29 with
open(sys
.argv
[1], "w") as f
: