src/soc/simple/issuer_verilog.py

   1 """simple core issuer verilog generator
   2 """
   3
   4 import argparse
   5 from nmigen.cli import verilog
   6
   7 from soc.config.test.test_loadstore import TestMemPspec
   8 from soc.simple.issuer import TestIssuer
   9
  10
  11 if __name__ == '__main__':
  12     parser = argparse.ArgumentParser(description="Simple core issuer " \
  13                                      "verilog generator")
  14     parser.add_argument("output_filename")
  15     parser.add_argument("--enable-xics", dest='xics', action="store_true",
  16                         help="Enable interrupts",
  17                         default=True)
  18     parser.add_argument("--disable-xics", dest='xics', action="store_false",
  19                         help="Disable interrupts",
  20                         default=False)
  21     parser.add_argument("--enable-core", dest='core', action="store_true",
  22                         help="Enable main core",
  23                         default=True)
  24     parser.add_argument("--disable-core", dest='core', action="store_false",
  25                         help="disable main core",
  26                         default=False)
  27     parser.add_argument("--enable-pll", dest='pll', action="store_true",
  28                         help="Enable pll",
  29                         default=False)
  30     parser.add_argument("--disable-pll", dest='pll', action="store_false",
  31                         help="Disable pll",
  32                         default=False)
  33     parser.add_argument("--enable-testgpio", action="store_true",
  34                         help="Disable gpio pins",
  35                         default=False)
  36     parser.add_argument("--debug", default="jtag", help="Select debug " \
  37                         "interface [jtag | dmi] [default jtag]")
  38
  39     args = parser.parse_args()
  40
  41     print(args)
  42
  43     units = {'alu': 1,
  44              'cr': 1, 'branch': 1, 'trap': 1,
  45              'logical': 1,
  46              'spr': 1,
  47              'div': 1,
  48              'mul': 1,
  49              'shiftrot': 1
  50             }
  51
  52     pspec = TestMemPspec(ldst_ifacetype='bare_wb',
  53                          imem_ifacetype='bare_wb',
  54                          addr_wid=48,
  55                          mask_wid=8,
  56                          # must leave at 64
  57                          reg_wid=64,
  58                          # set to 32 for instruction-memory width=32
  59                          imem_reg_wid=64,
  60                          # set to 32 to make data wishbone bus 32-bit
  61                          #wb_data_wid=32,
  62                          xics=args.xics, # XICS interrupt controller
  63                          nocore=not args.core, # test coriolis2 ioring
  64                          use_pll=args.pll,  # bypass PLL
  65                          gpio=args.enable_testgpio, # for test purposes
  66                          debug=args.debug,      # set to jtag or dmi
  67                          units=units)
  68
  69     print("nocore", pspec.__dict__["nocore"])
  70     print("gpio", pspec.__dict__["gpio"])
  71     print("xics", pspec.__dict__["xics"])
  72     print("use_pll", pspec.__dict__["use_pll"])
  73     print("debug", pspec.__dict__["debug"])
  74
  75     dut = TestIssuer(pspec)
  76
  77     vl = verilog.convert(dut, ports=dut.external_ports(), name="test_issuer")
  78     with open(args.output_filename, "w") as f:
  79         f.write(vl)