src/soc/simple/test/test_core.py

   1 """simple core test
   2
   3 related bugs:
   4
   5  * https://bugs.libre-soc.org/show_bug.cgi?id=363
   6 """
   7 from nmigen import Module, Signal, Cat
   8 from nmigen.back.pysim import Simulator, Delay, Settle
   9 from nmutil.formaltest import FHDLTestCase
  10 from nmigen.cli import rtlil
  11 import unittest
  12 from soc.decoder.isa.caller import special_sprs
  13 from soc.decoder.power_decoder import create_pdecode
  14 from soc.decoder.power_decoder2 import PowerDecode2
  15 from soc.decoder.isa.all import ISA
  16 from soc.decoder.power_enums import Function, XER_bits
  17
  18
  19 from soc.simple.core import NonProductionCore
  20 from soc.experiment.compalu_multi import find_ok # hack
  21
  22 from soc.fu.compunits.test.test_compunit import (setup_test_memory,
  23                                                  check_sim_memory)
  24
  25 # test with ALU data and Logical data
  26 from soc.fu.alu.test.test_pipe_caller import ALUTestCase
  27 from soc.fu.logical.test.test_pipe_caller import LogicalTestCase
  28 from soc.fu.shift_rot.test.test_pipe_caller import ShiftRotTestCase
  29 from soc.fu.cr.test.test_pipe_caller import CRTestCase
  30 from soc.fu.branch.test.test_pipe_caller import BranchTestCase
  31 from soc.fu.ldst.test.test_pipe_caller import LDSTTestCase
  32
  33
  34 def set_issue(core, dec2, sim):
  35     yield core.issue_i.eq(1)
  36     yield
  37     yield core.issue_i.eq(0)
  38     while True:
  39         busy_o = yield core.busy_o
  40         if busy_o:
  41             break
  42         print("!busy",)
  43         yield
  44
  45
  46 def wait_for_busy_clear(cu):
  47     while True:
  48         busy_o = yield cu.busy_o
  49         if not busy_o:
  50             break
  51         print("busy",)
  52         yield
  53
  54
  55 class TestRunner(FHDLTestCase):
  56     def __init__(self, tst_data):
  57         super().__init__("run_all")
  58         self.test_data = tst_data
  59
  60     def run_all(self):
  61         m = Module()
  62         comb = m.d.comb
  63         instruction = Signal(32)
  64         ivalid_i = Signal()
  65
  66         m.submodules.core = core = NonProductionCore()
  67         pdecode = core.pdecode
  68         pdecode2 = core.pdecode2
  69         l0 = core.l0
  70
  71         comb += core.raw_opcode_i.eq(instruction)
  72         comb += core.ivalid_i.eq(ivalid_i)
  73
  74         # temporary hack: says "go" immediately for both address gen and ST
  75         ldst = core.fus.fus['ldst0']
  76         m.d.comb += ldst.ad.go.eq(ldst.ad.rel) # link addr-go direct to rel
  77         m.d.comb += ldst.st.go.eq(ldst.st.rel) # link store-go direct to rel
  78
  79         # nmigen Simulation
  80         sim = Simulator(m)
  81         sim.add_clock(1e-6)
  82
  83         def process():
  84             yield core.issue_i.eq(0)
  85             yield
  86
  87             for test in self.test_data:
  88                 print(test.name)
  89                 program = test.program
  90                 self.subTest(test.name)
  91                 sim = ISA(pdecode2, test.regs, test.sprs, test.cr, test.mem,
  92                           test.msr)
  93                 gen = program.generate_instructions()
  94                 instructions = list(zip(gen, program.assembly.splitlines()))
  95
  96                 yield from setup_test_memory(l0, sim)
  97
  98                 # set up INT regfile, "direct" write (bypass rd/write ports)
  99                 for i in range(32):
 100                     yield core.regs.int.regs[i].reg.eq(test.regs[i])
 101
 102                 # set up CR regfile, "direct" write across all CRs
 103                 cr = test.cr
 104                 #cr = int('{:32b}'.format(cr)[::-1], 2)
 105                 print ("cr reg", hex(cr))
 106                 for i in range(8):
 107                     #j = 7-i
 108                     cri = (cr>>(i*4)) & 0xf
 109                     #cri = int('{:04b}'.format(cri)[::-1], 2)
 110                     print ("cr reg", hex(cri), i,
 111                             core.regs.cr.regs[i].reg.shape())
 112                     yield core.regs.cr.regs[i].reg.eq(cri)
 113
 114                 # set up XER.  "direct" write (bypass rd/write ports)
 115                 xregs = core.regs.xer
 116                 print ("sprs", test.sprs)
 117                 if special_sprs['XER'] in test.sprs:
 118                     xer = test.sprs[special_sprs['XER']]
 119                     sobit = xer[XER_bits['SO']].value
 120                     yield xregs.regs[xregs.SO].reg.eq(sobit)
 121                     cabit = xer[XER_bits['CA']].value
 122                     ca32bit = xer[XER_bits['CA32']].value
 123                     yield xregs.regs[xregs.CA].reg.eq(Cat(cabit, ca32bit))
 124                     ovbit = xer[XER_bits['OV']].value
 125                     ov32bit = xer[XER_bits['OV32']].value
 126                     yield xregs.regs[xregs.OV].reg.eq(Cat(ovbit, ov32bit))
 127                 else:
 128                     yield xregs.regs[xregs.SO].reg.eq(0)
 129                     yield xregs.regs[xregs.OV].reg.eq(0)
 130                     yield xregs.regs[xregs.CA].reg.eq(0)
 131
 132                 index = sim.pc.CIA.value//4
 133                 while index < len(instructions):
 134                     ins, code = instructions[index]
 135
 136                     print("instruction: 0x{:X}".format(ins & 0xffffffff))
 137                     print(code)
 138
 139                     # ask the decoder to decode this binary data (endian'd)
 140                     yield core.bigendian_i.eq(0)  # little / big?
 141                     yield instruction.eq(ins)          # raw binary instr.
 142                     yield ivalid_i.eq(1)
 143                     yield Settle()
 144                     #fn_unit = yield pdecode2.e.fn_unit
 145                     #fuval = self.funit.value
 146                     #self.assertEqual(fn_unit & fuval, fuval)
 147
 148                     # XER
 149                     so = yield xregs.regs[xregs.SO].reg
 150                     ov = yield xregs.regs[xregs.OV].reg
 151                     ca = yield xregs.regs[xregs.CA].reg
 152                     oe = yield pdecode2.e.oe.oe
 153                     oe_ok = yield pdecode2.e.oe.oe_ok
 154
 155                     print ("before: so/ov-32/ca-32", so, bin(ov), bin(ca))
 156                     print ("oe:", oe, oe_ok)
 157
 158                     # set operand and get inputs
 159                     yield from set_issue(core, pdecode2, sim)
 160                     yield Settle()
 161
 162                     yield from wait_for_busy_clear(core)
 163                     yield ivalid_i.eq(0)
 164                     yield
 165
 166                     print ("sim", code)
 167                     # call simulated operation
 168                     opname = code.split(' ')[0]
 169                     yield from sim.call(opname)
 170                     index = sim.pc.CIA.value//4
 171
 172                     # int regs
 173                     intregs = []
 174                     for i in range(32):
 175                         rval = yield core.regs.int.regs[i].reg
 176                         intregs.append(rval)
 177                     print ("int regs", list(map(hex, intregs)))
 178                     for i in range(32):
 179                         simregval = sim.gpr[i].asint()
 180                         self.assertEqual(simregval, intregs[i],
 181                             "int reg %d not equal %s" % (i, repr(code)))
 182
 183                     # CRs
 184                     crregs = []
 185                     for i in range(8):
 186                         rval = yield core.regs.cr.regs[i].reg
 187                         crregs.append(rval)
 188                     print ("cr regs", list(map(hex, crregs)))
 189                     print ("sim cr reg", hex(cr))
 190                     for i in range(8):
 191                         rval = crregs[i]
 192                         cri = sim.crl[7-i].get_range().value
 193                         print ("cr reg", i, hex(cri), i, hex(rval))
 194                         # XXX https://bugs.libre-soc.org/show_bug.cgi?id=363
 195                         self.assertEqual(cri, rval,
 196                             "cr reg %d not equal %s" % (i, repr(code)))
 197
 198                     # XER
 199                     so = yield xregs.regs[xregs.SO].reg
 200                     ov = yield xregs.regs[xregs.OV].reg
 201                     ca = yield xregs.regs[xregs.CA].reg
 202
 203                     print ("sim SO", sim.spr['XER'][XER_bits['SO']])
 204                     e_so = sim.spr['XER'][XER_bits['SO']].value
 205                     e_ov = sim.spr['XER'][XER_bits['OV']].value
 206                     e_ov32 = sim.spr['XER'][XER_bits['OV32']].value
 207                     e_ca = sim.spr['XER'][XER_bits['CA']].value
 208                     e_ca32 = sim.spr['XER'][XER_bits['CA32']].value
 209
 210                     e_ov = e_ov | (e_ov32<<1)
 211                     e_ca = e_ca | (e_ca32<<1)
 212
 213                     print ("after: so/ov-32/ca-32", so, bin(ov), bin(ca))
 214                     self.assertEqual(e_so, so, "so mismatch %s" % (repr(code)))
 215                     self.assertEqual(e_ov, ov, "ov mismatch %s" % (repr(code)))
 216                     self.assertEqual(e_ca, ca, "ca mismatch %s" % (repr(code)))
 217
 218                     # Memory check
 219                     yield from check_sim_memory(self, l0, sim, code)
 220
 221         sim.add_sync_process(process)
 222         with sim.write_vcd("core_simulator.vcd", "core_simulator.gtkw",
 223                             traces=[]):
 224             sim.run()
 225
 226
 227 if __name__ == "__main__":
 228     unittest.main(exit=False)
 229     suite = unittest.TestSuite()
 230     suite.addTest(TestRunner(LDSTTestCase.test_data))
 231     suite.addTest(TestRunner(CRTestCase.test_data))
 232     suite.addTest(TestRunner(ShiftRotTestCase.test_data))
 233     suite.addTest(TestRunner(LogicalTestCase.test_data))
 234     suite.addTest(TestRunner(ALUTestCase.test_data))
 235     suite.addTest(TestRunner(BranchTestCase.test_data))
 236
 237     runner = unittest.TextTestRunner()
 238     runner.run(suite)
 239