src/soc/simple/test/test_core.py

   1 """simple core test
   2
   3 related bugs:
   4
   5  * https://bugs.libre-soc.org/show_bug.cgi?id=363
   6 """
   7 from nmigen import Module, Signal, Cat
   8 from nmigen.back.pysim import Simulator, Delay, Settle
   9 from nmutil.formaltest import FHDLTestCase
  10 from nmigen.cli import rtlil
  11 import unittest
  12 from soc.decoder.isa.caller import special_sprs
  13 from soc.decoder.power_decoder import create_pdecode
  14 from soc.decoder.power_decoder2 import PowerDecode2
  15 from soc.decoder.selectable_int import SelectableInt
  16 from soc.decoder.isa.all import ISA
  17 from soc.decoder.power_enums import SPR, spr_dict, Function, XER_bits
  18 from soc.config.test.test_loadstore import TestMemPspec
  19 from soc.config.endian import bigendian
  20
  21 from soc.simple.core import NonProductionCore
  22 from soc.experiment.compalu_multi import find_ok  # hack
  23
  24 from soc.fu.compunits.test.test_compunit import (setup_test_memory,
  25                                                  check_sim_memory)
  26
  27 # test with ALU data and Logical data
  28 from soc.fu.alu.test.test_pipe_caller import ALUTestCase
  29 from soc.fu.logical.test.test_pipe_caller import LogicalTestCase
  30 from soc.fu.shift_rot.test.test_pipe_caller import ShiftRotTestCase
  31 from soc.fu.cr.test.test_pipe_caller import CRTestCase
  32 from soc.fu.branch.test.test_pipe_caller import BranchTestCase
  33 from soc.fu.ldst.test.test_pipe_caller import LDSTTestCase
  34 from soc.regfile.util import spr_to_fast_reg
  35
  36
  37 def setup_regs(core, test):
  38
  39     # set up INT regfile, "direct" write (bypass rd/write ports)
  40     intregs = core.regs.int
  41     for i in range(32):
  42         if intregs.unary:
  43             yield intregs.regs[i].reg.eq(test.regs[i])
  44         else:
  45             yield intregs.memory._array[i].eq(test.regs[i])
  46     yield Settle()
  47
  48     # set up CR regfile, "direct" write across all CRs
  49     cr = test.cr
  50     crregs = core.regs.cr
  51     #cr = int('{:32b}'.format(cr)[::-1], 2)
  52     print("cr reg", hex(cr))
  53     for i in range(8):
  54         #j = 7-i
  55         cri = (cr >> (i*4)) & 0xf
  56         #cri = int('{:04b}'.format(cri)[::-1], 2)
  57         print("cr reg", hex(cri), i,
  58               crregs.regs[i].reg.shape())
  59         yield crregs.regs[i].reg.eq(cri)
  60
  61     # set up XER.  "direct" write (bypass rd/write ports)
  62     xregs = core.regs.xer
  63     print("sprs", test.sprs)
  64     xer = None
  65     if 'XER' in test.sprs:
  66         xer = test.sprs['XER']
  67     if 1 in test.sprs:
  68         xer = test.sprs[1]
  69     if xer is not None:
  70         if isinstance(xer, int):
  71             xer = SelectableInt(xer, 64)
  72         sobit = xer[XER_bits['SO']].value
  73         yield xregs.regs[xregs.SO].reg.eq(sobit)
  74         cabit = xer[XER_bits['CA']].value
  75         ca32bit = xer[XER_bits['CA32']].value
  76         yield xregs.regs[xregs.CA].reg.eq(Cat(cabit, ca32bit))
  77         ovbit = xer[XER_bits['OV']].value
  78         ov32bit = xer[XER_bits['OV32']].value
  79         yield xregs.regs[xregs.OV].reg.eq(Cat(ovbit, ov32bit))
  80         print("setting XER so %d ca %d ca32 %d ov %d ov32 %d" %
  81               (sobit, cabit, ca32bit, ovbit, ov32bit))
  82     else:
  83         yield xregs.regs[xregs.SO].reg.eq(0)
  84         yield xregs.regs[xregs.OV].reg.eq(0)
  85         yield xregs.regs[xregs.CA].reg.eq(0)
  86
  87     # setting both fast and slow SPRs from test data
  88
  89     fregs = core.regs.fast
  90     sregs = core.regs.spr
  91     for sprname, val in test.sprs.items():
  92         if isinstance(val, SelectableInt):
  93             val = val.value
  94         if isinstance(sprname, int):
  95             sprname = spr_dict[sprname].SPR
  96         if sprname == 'XER':
  97             continue
  98         fast = spr_to_fast_reg(sprname)
  99         if fast is None:
 100             # match behaviour of SPRMap in power_decoder2.py
 101             for i, x in enumerate(SPR):
 102                 if sprname == x.name:
 103                     yield sregs[i].reg.eq(val)
 104                     print("setting slow SPR %d (%s) to %x" %
 105                           (i, sprname, val))
 106         else:
 107             yield fregs.regs[fast].reg.eq(val)
 108             print("setting fast reg %d (%s) to %x" %
 109                   (fast, sprname, val))
 110
 111     # allow changes to settle before reporting on XER
 112     yield Settle()
 113
 114     # XER
 115     pdecode2 = core.pdecode2
 116     so = yield xregs.regs[xregs.SO].reg
 117     ov = yield xregs.regs[xregs.OV].reg
 118     ca = yield xregs.regs[xregs.CA].reg
 119     oe = yield pdecode2.e.do.oe.oe
 120     oe_ok = yield pdecode2.e.do.oe.oe_ok
 121
 122     print("before: so/ov-32/ca-32", so, bin(ov), bin(ca))
 123     print("oe:", oe, oe_ok)
 124
 125
 126 def check_regs(dut, sim, core, test, code):
 127     # int regs
 128     intregs = []
 129     for i in range(32):
 130         if core.regs.int.unary:
 131             rval = yield core.regs.int.regs[i].reg
 132         else:
 133             rval = yield core.regs.int.memory._array[i]
 134         intregs.append(rval)
 135     print("int regs", list(map(hex, intregs)))
 136     for i in range(32):
 137         simregval = sim.gpr[i].asint()
 138         dut.assertEqual(simregval, intregs[i],
 139                         "int reg %d not equal %s" % (i, repr(code)))
 140
 141     # CRs
 142     crregs = []
 143     for i in range(8):
 144         rval = yield core.regs.cr.regs[i].reg
 145         crregs.append(rval)
 146     print("cr regs", list(map(hex, crregs)))
 147     for i in range(8):
 148         rval = crregs[i]
 149         cri = sim.crl[7-i].get_range().value
 150         print("cr reg", i, hex(cri), i, hex(rval))
 151         # XXX https://bugs.libre-soc.org/show_bug.cgi?id=363
 152         dut.assertEqual(cri, rval,
 153                         "cr reg %d not equal %s" % (i, repr(code)))
 154
 155     # XER
 156     xregs = core.regs.xer
 157     so = yield xregs.regs[xregs.SO].reg
 158     ov = yield xregs.regs[xregs.OV].reg
 159     ca = yield xregs.regs[xregs.CA].reg
 160
 161     print("sim SO", sim.spr['XER'][XER_bits['SO']])
 162     e_so = sim.spr['XER'][XER_bits['SO']].value
 163     e_ov = sim.spr['XER'][XER_bits['OV']].value
 164     e_ov32 = sim.spr['XER'][XER_bits['OV32']].value
 165     e_ca = sim.spr['XER'][XER_bits['CA']].value
 166     e_ca32 = sim.spr['XER'][XER_bits['CA32']].value
 167
 168     e_ov = e_ov | (e_ov32 << 1)
 169     e_ca = e_ca | (e_ca32 << 1)
 170
 171     print("after: so/ov-32/ca-32", so, bin(ov), bin(ca))
 172     dut.assertEqual(e_so, so, "so mismatch %s" % (repr(code)))
 173     dut.assertEqual(e_ov, ov, "ov mismatch %s" % (repr(code)))
 174     dut.assertEqual(e_ca, ca, "ca mismatch %s" % (repr(code)))
 175
 176
 177 def wait_for_busy_hi(cu):
 178     while True:
 179         busy_o = yield cu.busy_o
 180         terminate_o = yield cu.core_terminate_o
 181         if busy_o:
 182             print("busy/terminate:", busy_o, terminate_o)
 183             break
 184         print("!busy", busy_o, terminate_o)
 185         yield
 186
 187
 188 def set_issue(core, dec2, sim):
 189     yield core.issue_i.eq(1)
 190     yield
 191     yield core.issue_i.eq(0)
 192     yield from wait_for_busy_hi(core)
 193
 194
 195 def wait_for_busy_clear(cu):
 196     while True:
 197         busy_o = yield cu.busy_o
 198         terminate_o = yield cu.core_terminate_o
 199         if not busy_o:
 200             print("busy/terminate:", busy_o, terminate_o)
 201             break
 202         print("busy",)
 203         yield
 204
 205
 206 class TestRunner(FHDLTestCase):
 207     def __init__(self, tst_data):
 208         super().__init__("run_all")
 209         self.test_data = tst_data
 210
 211     def run_all(self):
 212         m = Module()
 213         comb = m.d.comb
 214         instruction = Signal(32)
 215         ivalid_i = Signal()
 216
 217         pspec = TestMemPspec(ldst_ifacetype='testpi',
 218                              imem_ifacetype='',
 219                              addr_wid=48,
 220                              mask_wid=8,
 221                              reg_wid=64)
 222
 223         m.submodules.core = core = NonProductionCore(pspec)
 224         pdecode2 = core.pdecode2
 225         l0 = core.l0
 226
 227         comb += core.raw_opcode_i.eq(instruction)
 228         comb += core.ivalid_i.eq(ivalid_i)
 229
 230         # temporary hack: says "go" immediately for both address gen and ST
 231         ldst = core.fus.fus['ldst0']
 232         m.d.comb += ldst.ad.go.eq(ldst.ad.rel)  # link addr-go direct to rel
 233         m.d.comb += ldst.st.go.eq(ldst.st.rel)  # link store-go direct to rel
 234
 235         # nmigen Simulation
 236         sim = Simulator(m)
 237         sim.add_clock(1e-6)
 238
 239         def process():
 240             yield core.issue_i.eq(0)
 241             yield
 242
 243             for test in self.test_data:
 244                 print(test.name)
 245                 program = test.program
 246                 self.subTest(test.name)
 247                 sim = ISA(pdecode2, test.regs, test.sprs, test.cr, test.mem,
 248                           test.msr,
 249                           bigendian=bigendian)
 250                 gen = program.generate_instructions()
 251                 instructions = list(zip(gen, program.assembly.splitlines()))
 252
 253                 yield from setup_test_memory(l0, sim)
 254                 yield from setup_regs(core, test)
 255
 256                 index = sim.pc.CIA.value//4
 257                 while index < len(instructions):
 258                     ins, code = instructions[index]
 259
 260                     print("instruction: 0x{:X}".format(ins & 0xffffffff))
 261                     print(code)
 262
 263                     # ask the decoder to decode this binary data (endian'd)
 264                     yield core.bigendian_i.eq(bigendian)  # little / big?
 265                     yield instruction.eq(ins)          # raw binary instr.
 266                     yield ivalid_i.eq(1)
 267                     yield Settle()
 268                     # fn_unit = yield pdecode2.e.fn_unit
 269                     #fuval = self.funit.value
 270                     #self.assertEqual(fn_unit & fuval, fuval)
 271
 272                     # set operand and get inputs
 273                     yield from set_issue(core, pdecode2, sim)
 274                     yield Settle()
 275
 276                     yield from wait_for_busy_clear(core)
 277                     yield ivalid_i.eq(0)
 278                     yield
 279
 280                     print("sim", code)
 281                     # call simulated operation
 282                     opname = code.split(' ')[0]
 283                     yield from sim.call(opname)
 284                     index = sim.pc.CIA.value//4
 285
 286                     # register check
 287                     yield from check_regs(self, sim, core, test, code)
 288
 289                     # Memory check
 290                     yield from check_sim_memory(self, l0, sim, code)
 291
 292         sim.add_sync_process(process)
 293         with sim.write_vcd("core_simulator.vcd", "core_simulator.gtkw",
 294                            traces=[]):
 295             sim.run()
 296
 297
 298 if __name__ == "__main__":
 299     unittest.main(exit=False)
 300     suite = unittest.TestSuite()
 301     suite.addTest(TestRunner(LDSTTestCase.test_data))
 302     suite.addTest(TestRunner(CRTestCase.test_data))
 303     suite.addTest(TestRunner(ShiftRotTestCase.test_data))
 304     suite.addTest(TestRunner(LogicalTestCase.test_data))
 305     suite.addTest(TestRunner(ALUTestCase.test_data))
 306     suite.addTest(TestRunner(BranchTestCase.test_data))
 307
 308     runner = unittest.TextTestRunner()
 309     runner.run(suite)