src/soc/simple/test/test_issuer_mmu_ifetch.py

   1 """simple core test, runs instructions from a TestMemory
   2
   3 related bugs:
   4
   5  * https://bugs.libre-soc.org/show_bug.cgi?id=363
   6 """
   7
   8 # NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell
   9 # Also, check out the cxxsim nmigen branch, and latest yosys from git
  10
  11 import unittest
  12 import sys
  13
  14 # here is the logic which takes test cases and "executes" them.
  15 # in this instance (TestRunner) its job is to instantiate both
  16 # a Libre-SOC nmigen-based HDL instance and an ISACaller python
  17 # simulator.  it's also responsible for performing the single
  18 # step and comparison.
  19 from soc.simple.test.test_runner import TestRunner
  20
  21 #@platen:bookmarks
  22 #src/openpower/test/runner.py:class TestRunnerBase(FHDLTestCase):
  23
  24 # test with MMU
  25 from openpower.test.mmu.mmu_cases import MMUTestCase
  26 from openpower.test.mmu.mmu_rom_cases import MMUTestCaseROM, default_mem
  27 from openpower.test.ldst.ldst_cases import LDSTTestCase
  28 from openpower.test.ldst.ldst_exc_cases import LDSTExceptionTestCase
  29 #from openpower.simulator.test_sim import (GeneralTestCases, AttnTestCase)
  30
  31 from openpower.simulator.program import Program
  32 from openpower.endian import bigendian
  33 from openpower.test.common import TestAccumulatorBase
  34
  35 from openpower.consts import MSR
  36
  37 from soc.experiment.test import pagetables
  38
  39
  40 class MMUTestCase(TestAccumulatorBase):
  41
  42     # MMUTEST: initial_msr= 16384
  43     # msr 16384
  44     # ISACaller initial_msr 16384
  45     # FIXME msr does not get passed to LoadStore1
  46     def case_5_ldst_exception(self):
  47         lst = [#"mtspr 720,1", # mtspr PRTBL,r1
  48                "stb 10,0(2)",
  49                "addi 10,0, 2",
  50                "lbz 6,0(2)",
  51               ]
  52         initial_regs = [0] * 32
  53         initial_regs[1] = 0x1000000
  54         initial_regs[2] = 0x3456
  55         initial_regs[3] = 0x4321
  56         initial_regs[4] = 0x6543
  57         initial_regs[10] = 0xfe
  58         initial_mem = {}
  59         initial_msr = 0 << MSR.PR # must set "problem" state
  60         initial_msr |= 1 << MSR.DR # set "virtual" state
  61         initial_sprs = {720: 0x1000000} # PRTBL
  62         print("MMUTEST: initial_msr=",initial_msr)
  63         self.add_case(Program(lst, bigendian), initial_regs,
  64                              initial_mem=initial_mem,
  65                              initial_sprs=initial_sprs,
  66                              initial_msr=initial_msr)
  67
  68 if __name__ == "__main__":
  69     svp64 = True
  70     if len(sys.argv) == 2:
  71         if sys.argv[1] == 'nosvp64':
  72             svp64 = False
  73         sys.argv.pop()
  74
  75     print ("SVP64 test mode enabled", svp64)
  76
  77     unittest.main(exit=False)
  78     suite = unittest.TestSuite()
  79
  80     # MMU/DCache integration tests
  81     suite.addTest(TestRunner(MMUTestCase().test_data, svp64=svp64,
  82                               microwatt_mmu=True,
  83                               rom=pagetables.test1))
  84
  85     runner = unittest.TextTestRunner()
  86     runner.run(suite)