Create a new signal for the Simulator to wait on
[soc.git] / src / soc / simple / test / test_issuer_svp64.py
1 """test of SVP64 operations.
2
3 related bugs:
4
5 * https://bugs.libre-soc.org/show_bug.cgi?id=363
6 """
7
8 # NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell
9 # Also, check out the cxxsim nmigen branch, and latest yosys from git
10
11 import unittest
12 from soc.simple.test.test_runner import TestRunner
13
14 # test with ALU data and Logical data
15 from soc.fu.alu.test.svp64_cases import SVP64ALUTestCase
16
17
18 if __name__ == "__main__":
19 unittest.main(exit=False)
20 suite = unittest.TestSuite()
21 suite.addTest(TestRunner(SVP64ALUTestCase().test_data))
22
23 runner = unittest.TextTestRunner()
24 runner.run(suite)