src/soc/simple/test/test_runner.py

   1 """TestRunner class, runs TestIssuer instructions
   2
   3 related bugs:
   4
   5  * https://bugs.libre-soc.org/show_bug.cgi?id=363
   6 """
   7 from nmigen import Module, Signal, Cat, ClockSignal
   8
   9 # NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell
  10 # Also, check out the cxxsim nmigen branch, and latest yosys from git
  11 from nmutil.sim_tmp_alternative import Simulator, Settle
  12
  13 from nmutil.formaltest import FHDLTestCase
  14 from nmutil.gtkw import write_gtkw
  15 from nmigen.cli import rtlil
  16 from openpower.decoder.isa.caller import special_sprs, SVP64State
  17 from openpower.decoder.isa.all import ISA
  18 from openpower.endian import bigendian
  19
  20 from openpower.decoder.power_decoder import create_pdecode
  21 from openpower.decoder.power_decoder2 import PowerDecode2
  22 from soc.regfile.regfiles import StateRegs
  23
  24 from soc.simple.issuer import TestIssuerInternal
  25
  26 from soc.config.test.test_loadstore import TestMemPspec
  27 from soc.simple.test.test_core import (setup_regs, check_regs,
  28                                        wait_for_busy_clear,
  29                                        wait_for_busy_hi)
  30 from soc.fu.compunits.test.test_compunit import (setup_test_memory,
  31                                                  check_sim_memory)
  32 from soc.debug.dmi import DBGCore, DBGCtrl, DBGStat
  33 from nmutil.util import wrap
  34 from soc.experiment.test.test_mmu_dcache import wb_get
  35
  36
  37 def setup_i_memory(imem, startaddr, instructions):
  38     mem = imem
  39     print("insn before, init mem", mem.depth, mem.width, mem,
  40           len(instructions))
  41     for i in range(mem.depth):
  42         yield mem._array[i].eq(0)
  43     yield Settle()
  44     startaddr //= 4  # instructions are 32-bit
  45     if mem.width == 32:
  46         mask = ((1 << 32)-1)
  47         for ins in instructions:
  48             if isinstance(ins, tuple):
  49                 insn, code = ins
  50             else:
  51                 insn, code = ins, ''
  52             insn = insn & 0xffffffff
  53             yield mem._array[startaddr].eq(insn)
  54             yield Settle()
  55             if insn != 0:
  56                 print("instr: %06x 0x%x %s" % (4*startaddr, insn, code))
  57             startaddr += 1
  58             startaddr = startaddr & mask
  59         return
  60
  61     # 64 bit
  62     mask = ((1 << 64)-1)
  63     for ins in instructions:
  64         if isinstance(ins, tuple):
  65             insn, code = ins
  66         else:
  67             insn, code = ins, ''
  68         insn = insn & 0xffffffff
  69         msbs = (startaddr >> 1) & mask
  70         val = yield mem._array[msbs]
  71         if insn != 0:
  72             print("before set", hex(4*startaddr),
  73                   hex(msbs), hex(val), hex(insn))
  74         lsb = 1 if (startaddr & 1) else 0
  75         val = (val | (insn << (lsb*32)))
  76         val = val & mask
  77         yield mem._array[msbs].eq(val)
  78         yield Settle()
  79         if insn != 0:
  80             print("after  set", hex(4*startaddr), hex(msbs), hex(val))
  81             print("instr: %06x 0x%x %s %08x" % (4*startaddr, insn, code, val))
  82         startaddr += 1
  83         startaddr = startaddr & mask
  84
  85
  86 def set_dmi(dmi, addr, data):
  87     yield dmi.req_i.eq(1)
  88     yield dmi.addr_i.eq(addr)
  89     yield dmi.din.eq(data)
  90     yield dmi.we_i.eq(1)
  91     while True:
  92         ack = yield dmi.ack_o
  93         if ack:
  94             break
  95         yield
  96     yield
  97     yield dmi.req_i.eq(0)
  98     yield dmi.addr_i.eq(0)
  99     yield dmi.din.eq(0)
 100     yield dmi.we_i.eq(0)
 101     yield
 102
 103
 104 def get_dmi(dmi, addr):
 105     yield dmi.req_i.eq(1)
 106     yield dmi.addr_i.eq(addr)
 107     yield dmi.din.eq(0)
 108     yield dmi.we_i.eq(0)
 109     while True:
 110         ack = yield dmi.ack_o
 111         if ack:
 112             break
 113         yield
 114     yield  # wait one
 115     data = yield dmi.dout  # get data after ack valid for 1 cycle
 116     yield dmi.req_i.eq(0)
 117     yield dmi.addr_i.eq(0)
 118     yield dmi.we_i.eq(0)
 119     yield
 120     return data
 121
 122
 123 class TestRunner(FHDLTestCase):
 124     def __init__(self, tst_data, microwatt_mmu=False, rom=None,
 125                         svp64=True):
 126         super().__init__("run_all")
 127         self.test_data = tst_data
 128         self.microwatt_mmu = microwatt_mmu
 129         self.rom = rom
 130         self.svp64 = svp64
 131
 132     def run_all(self):
 133         m = Module()
 134         comb = m.d.comb
 135         pc_i = Signal(32)
 136         svstate_i = Signal(32)
 137
 138         pspec = TestMemPspec(ldst_ifacetype='test_bare_wb',
 139                              imem_ifacetype='test_bare_wb',
 140                              addr_wid=48,
 141                              mask_wid=8,
 142                              imem_reg_wid=64,
 143                              # wb_data_width=32,
 144                              use_pll=False,
 145                              nocore=False,
 146                              xics=False,
 147                              gpio=False,
 148                              regreduce=True,
 149                              svp64=self.svp64,
 150                              mmu=self.microwatt_mmu,
 151                              reg_wid=64)
 152         m.submodules.issuer = issuer = TestIssuerInternal(pspec)
 153         imem = issuer.imem._get_memory()
 154         core = issuer.core
 155         dmi = issuer.dbg.dmi
 156         pdecode2 = issuer.pdecode2
 157         l0 = core.l0
 158         regreduce_en = pspec.regreduce_en == True
 159
 160         # copy of the decoder for simulator
 161         simdec = create_pdecode()
 162         simdec2 = PowerDecode2(simdec, regreduce_en=regreduce_en)
 163         m.submodules.simdec2 = simdec2  # pain in the neck
 164
 165         # run core clock at same rate as test clock
 166         intclk = ClockSignal("coresync")
 167         comb += intclk.eq(ClockSignal())
 168
 169         comb += issuer.pc_i.data.eq(pc_i)
 170         comb += issuer.svstate_i.data.eq(svstate_i)
 171
 172         # nmigen Simulation
 173         sim = Simulator(m)
 174         sim.add_clock(1e-6)
 175
 176         def process():
 177
 178             # start in stopped
 179             yield from set_dmi(dmi, DBGCore.CTRL, 1<<DBGCtrl.STOP)
 180             yield
 181             yield
 182
 183             # get each test, completely reset the core, and run it
 184
 185             for test in self.test_data:
 186
 187                 # pull a reset
 188                 # yield from set_dmi(dmi, DBGCore.CTRL, 1<<DBGCtrl.RESET)
 189
 190                 # set up bigendian (TODO: don't do this, use MSR)
 191                 yield issuer.core_bigendian_i.eq(bigendian)
 192                 yield Settle()
 193
 194                 yield
 195                 yield
 196                 yield
 197                 yield
 198
 199                 print(test.name)
 200                 program = test.program
 201                 self.subTest(test.name)
 202                 print("regs", test.regs)
 203                 print("sprs", test.sprs)
 204                 print("cr", test.cr)
 205                 print("mem", test.mem)
 206                 print("msr", test.msr)
 207                 print("assem", program.assembly)
 208                 gen = list(program.generate_instructions())
 209                 insncode = program.assembly.splitlines()
 210                 instructions = list(zip(gen, insncode))
 211
 212                 # set up the Simulator (which must track TestIssuer exactly)
 213                 sim = ISA(simdec2, test.regs, test.sprs, test.cr, test.mem,
 214                           test.msr,
 215                           initial_insns=gen, respect_pc=True,
 216                           disassembly=insncode,
 217                           bigendian=bigendian,
 218                           initial_svstate=test.svstate)
 219
 220                 # establish the TestIssuer context (mem, regs etc)
 221
 222                 pc = 0  # start address
 223                 counter = 0  # test to pause/start
 224
 225                 yield from setup_i_memory(imem, pc, instructions)
 226                 yield from setup_test_memory(l0, sim)
 227                 yield from setup_regs(pdecode2, core, test)
 228
 229                 # set PC and SVSTATE
 230                 yield pc_i.eq(pc)
 231                 yield issuer.pc_i.ok.eq(1)
 232
 233                 initial_svstate = test.svstate
 234                 if isinstance(initial_svstate, int):
 235                     initial_svstate = SVP64State(initial_svstate)
 236                 yield svstate_i.eq(initial_svstate.spr.value)
 237                 yield issuer.svstate_i.ok.eq(1)
 238                 yield
 239
 240                 print("instructions", instructions)
 241
 242                 # run the loop of the instructions on the current test
 243                 index = sim.pc.CIA.value//4
 244                 while index < len(instructions):
 245                     ins, code = instructions[index]
 246
 247                     print("instruction: 0x{:X}".format(ins & 0xffffffff))
 248                     print(index, code)
 249
 250                     if counter == 0:
 251                         # start the core
 252                         yield
 253                         yield from set_dmi(dmi, DBGCore.CTRL, 1<<DBGCtrl.START)
 254                         yield issuer.pc_i.ok.eq(0)  # no change PC after this
 255                         yield issuer.svstate_i.ok.eq(0) # ditto
 256                         yield
 257                         yield
 258
 259                     counter = counter + 1
 260
 261                     # wait until executed
 262                     while not (yield issuer.insn_done):
 263                         yield
 264
 265                     # set up simulated instruction (in simdec2)
 266                     try:
 267                         yield from sim.setup_one()
 268                     except KeyError:  # indicates instruction not in imem: stop
 269                         break
 270                     yield Settle()
 271
 272                     # call simulated operation
 273                     print("sim", code)
 274                     yield from sim.execute_one()
 275                     yield Settle()
 276                     index = sim.pc.CIA.value//4
 277
 278                     terminated = yield issuer.dbg.terminated_o
 279                     print("terminated", terminated)
 280
 281                     if index >= len(instructions):
 282                         print ("index over, send dmi stop")
 283                         # stop at end
 284                         yield from set_dmi(dmi, DBGCore.CTRL, 1<<DBGCtrl.STOP)
 285                         yield
 286                         yield
 287
 288                     # register check
 289                     yield from check_regs(self, sim, core, test, code)
 290
 291                     # Memory check
 292                     yield from check_sim_memory(self, l0, sim, code)
 293
 294                     terminated = yield issuer.dbg.terminated_o
 295                     print("terminated(2)", terminated)
 296                     if terminated:
 297                         break
 298
 299                 # stop at end
 300                 yield from set_dmi(dmi, DBGCore.CTRL, 1<<DBGCtrl.STOP)
 301                 yield
 302                 yield
 303
 304                 # get CR
 305                 cr = yield from get_dmi(dmi, DBGCore.CR)
 306                 print("after test %s cr value %x" % (test.name, cr))
 307
 308                 # get XER
 309                 xer = yield from get_dmi(dmi, DBGCore.XER)
 310                 print("after test %s XER value %x" % (test.name, xer))
 311
 312                 # test of dmi reg get
 313                 for int_reg in range(32):
 314                     yield from set_dmi(dmi, DBGCore.GSPR_IDX, int_reg)
 315                     value = yield from get_dmi(dmi, DBGCore.GSPR_DATA)
 316
 317                     print("after test %s reg %2d value %x" %
 318                           (test.name, int_reg, value))
 319
 320         styles = {
 321             'dec': {'base': 'dec'},
 322             'bin': {'base': 'bin'},
 323             'closed': {'closed': True}
 324         }
 325
 326         traces = [
 327             'clk',
 328             ('state machines', 'closed', [
 329                 'fetch_pc_valid_i', 'fetch_pc_ready_o',
 330                 'fetch_fsm_state',
 331                 'fetch_insn_valid_o', 'fetch_insn_ready_i',
 332                 'pred_insn_valid_i', 'pred_insn_ready_o',
 333                 'fetch_predicate_state',
 334                 'pred_mask_valid_o', 'pred_mask_ready_i',
 335                 'issue_fsm_state',
 336                 'exec_insn_valid_i', 'exec_insn_ready_o',
 337                 'exec_fsm_state',
 338                 'exec_pc_valid_o', 'exec_pc_ready_i',
 339                 'insn_done', 'core_stop_o', 'pc_i_ok', 'pc_changed',
 340                 'is_last', 'dec2.no_out_vec']),
 341             {'comment': 'fetch and decode'},
 342             (None, 'dec', [
 343                 'cia[63:0]', 'nia[63:0]', 'pc[63:0]',
 344                 'cur_pc[63:0]', 'core_core_cia[63:0]']),
 345             'raw_insn_i[31:0]',
 346             'raw_opcode_in[31:0]', 'insn_type',
 347             ('svp64 decoding', 'closed', [
 348                 'svp64_rm[23:0]', ('dec2.extra[8:0]', 'bin'),
 349                 'dec2.sv_rm_dec.mode', 'dec2.sv_rm_dec.predmode',
 350                 'dec2.sv_rm_dec.ptype_in',
 351                 'dec2.sv_rm_dec.dstpred[2:0]', 'dec2.sv_rm_dec.srcpred[2:0]',
 352                 'dstmask[63:0]', 'srcmask[63:0]',
 353                 'dregread[4:0]', 'dinvert',
 354                 'sregread[4:0]', 'sinvert',
 355                 'core.int.pred__addr[4:0]', 'core.int.pred__data_o[63:0]',
 356                 'core.int.pred__ren']),
 357             ('register augmentation', 'dec', 'closed', [
 358                 {'comment': 'v3.0b registers'},
 359                 'dec2.dec_o.RT[4:0]',
 360                 'dec2.dec_a.RA[4:0]',
 361                 'dec2.dec_b.RB[4:0]',
 362                 ('Rdest', [
 363                     'dec2.o_svdec.reg_in[4:0]',
 364                     ('dec2.o_svdec.spec[2:0]', 'bin'),
 365                     'dec2.o_svdec.reg_out[6:0]']),
 366                 ('Rsrc1', [
 367                     'dec2.in1_svdec.reg_in[4:0]',
 368                     ('dec2.in1_svdec.spec[2:0]', 'bin'),
 369                     'dec2.in1_svdec.reg_out[6:0]']),
 370                 ('Rsrc1', [
 371                     'dec2.in2_svdec.reg_in[4:0]',
 372                     ('dec2.in2_svdec.spec[2:0]', 'bin'),
 373                     'dec2.in2_svdec.reg_out[6:0]']),
 374                 {'comment': 'SVP64 registers'},
 375                 'dec2.rego[6:0]', 'dec2.reg1[6:0]', 'dec2.reg2[6:0]'
 376             ]),
 377             {'comment': 'svp64 context'},
 378             'core_core_vl[6:0]', 'core_core_maxvl[6:0]',
 379             'core_core_srcstep[6:0]', 'next_srcstep[6:0]',
 380             'core_core_dststep[6:0]',
 381             {'comment': 'issue and execute'},
 382             'core.core_core_insn_type',
 383             (None, 'dec', [
 384                 'core_rego[6:0]', 'core_reg1[6:0]', 'core_reg2[6:0]']),
 385             'issue_i', 'busy_o',
 386             {'comment': 'dmi'},
 387             'dbg.dmi_req_i', 'dbg.dmi_ack_o',
 388             {'comment': 'instruction memory'},
 389             'imem.sram.rdport.memory(0)[63:0]',
 390             {'comment': 'registers'},
 391             # match with soc.regfile.regfiles.IntRegs port names
 392             'core.int.rp_src1.memory(0)[63:0]',
 393             'core.int.rp_src1.memory(1)[63:0]',
 394             'core.int.rp_src1.memory(2)[63:0]',
 395             'core.int.rp_src1.memory(3)[63:0]',
 396             'core.int.rp_src1.memory(4)[63:0]',
 397             'core.int.rp_src1.memory(5)[63:0]',
 398             'core.int.rp_src1.memory(6)[63:0]',
 399             'core.int.rp_src1.memory(7)[63:0]',
 400             'core.int.rp_src1.memory(9)[63:0]',
 401             'core.int.rp_src1.memory(10)[63:0]',
 402             'core.int.rp_src1.memory(13)[63:0]',
 403         ]
 404
 405         if self.microwatt_mmu:
 406             traces += [
 407                 {'comment': 'microwatt_mmu'},
 408                 'core.fus.mmu0.alu_mmu0.illegal',
 409                 'core.fus.mmu0.alu_mmu0.debug0[3:0]',
 410                 'core.fus.mmu0.alu_mmu0.mmu.state',
 411                 'core.fus.mmu0.alu_mmu0.mmu.pid[31:0]',
 412                 'core.fus.mmu0.alu_mmu0.mmu.prtbl[63:0]',
 413                 {'comment': 'wishbone_memory'},
 414                 'core.fus.mmu0.alu_mmu0.dcache.stb',
 415                 'core.fus.mmu0.alu_mmu0.dcache.cyc',
 416                 'core.fus.mmu0.alu_mmu0.dcache.we',
 417                 'core.fus.mmu0.alu_mmu0.dcache.ack',
 418                 'core.fus.mmu0.alu_mmu0.dcache.stall,'
 419             ]
 420
 421         write_gtkw("issuer_simulator.gtkw",
 422                    "issuer_simulator.vcd",
 423                    traces, styles, module='top.issuer')
 424
 425         # add run of instructions
 426         sim.add_sync_process(process)
 427
 428         # optionally, if a wishbone-based ROM is passed in, run that as an
 429         # extra emulated process
 430         if self.rom is not None:
 431             dcache = core.fus.fus["mmu0"].alu.dcache
 432             default_mem = self.rom
 433             sim.add_sync_process(wrap(wb_get(dcache, default_mem, "DCACHE")))
 434
 435         with sim.write_vcd("issuer_simulator.vcd"):
 436             sim.run()