src/soc/simple/test/test_runner.py

   1 """TestRunner class, runs TestIssuer instructions
   2
   3 related bugs:
   4
   5  * https://bugs.libre-soc.org/show_bug.cgi?id=363
   6  * https://bugs.libre-soc.org/show_bug.cgi?id=686#c51
   7 """
   8 from nmigen import Module, Signal, Cat, ClockSignal
   9 from nmigen.hdl.xfrm import ResetInserter
  10
  11 # NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell
  12 # Also, check out the cxxsim nmigen branch, and latest yosys from git
  13 from nmutil.sim_tmp_alternative import Simulator, Settle
  14
  15 from nmutil.formaltest import FHDLTestCase
  16 from nmutil.gtkw import write_gtkw
  17 from nmigen.cli import rtlil
  18 from openpower.decoder.isa.caller import special_sprs, SVP64State
  19 from openpower.decoder.isa.all import ISA
  20 from openpower.endian import bigendian
  21
  22 from openpower.decoder.power_decoder import create_pdecode
  23 from openpower.decoder.power_decoder2 import PowerDecode2
  24 from soc.regfile.regfiles import StateRegs
  25
  26 from soc.simple.issuer import TestIssuerInternal
  27
  28 from soc.config.test.test_loadstore import TestMemPspec
  29 from soc.simple.test.test_core import (setup_regs, check_regs, check_mem,
  30                                        wait_for_busy_clear,
  31                                        wait_for_busy_hi)
  32 from soc.fu.compunits.test.test_compunit import (setup_tst_memory,
  33                                                  check_sim_memory)
  34 from soc.debug.dmi import DBGCore, DBGCtrl, DBGStat
  35 from nmutil.util import wrap
  36 from soc.experiment.test.test_mmu_dcache import wb_get
  37
  38
  39 def setup_i_memory(imem, startaddr, instructions):
  40     mem = imem
  41     print("insn before, init mem", mem.depth, mem.width, mem,
  42           len(instructions))
  43     for i in range(mem.depth):
  44         yield mem._array[i].eq(0)
  45     yield Settle()
  46     startaddr //= 4  # instructions are 32-bit
  47     if mem.width == 32:
  48         mask = ((1 << 32)-1)
  49         for ins in instructions:
  50             if isinstance(ins, tuple):
  51                 insn, code = ins
  52             else:
  53                 insn, code = ins, ''
  54             insn = insn & 0xffffffff
  55             yield mem._array[startaddr].eq(insn)
  56             yield Settle()
  57             if insn != 0:
  58                 print("instr: %06x 0x%x %s" % (4*startaddr, insn, code))
  59             startaddr += 1
  60             startaddr = startaddr & mask
  61         return
  62
  63     # 64 bit
  64     mask = ((1 << 64)-1)
  65     for ins in instructions:
  66         if isinstance(ins, tuple):
  67             insn, code = ins
  68         else:
  69             insn, code = ins, ''
  70         insn = insn & 0xffffffff
  71         msbs = (startaddr >> 1) & mask
  72         val = yield mem._array[msbs]
  73         if insn != 0:
  74             print("before set", hex(4*startaddr),
  75                   hex(msbs), hex(val), hex(insn))
  76         lsb = 1 if (startaddr & 1) else 0
  77         val = (val | (insn << (lsb*32)))
  78         val = val & mask
  79         yield mem._array[msbs].eq(val)
  80         yield Settle()
  81         if insn != 0:
  82             print("after  set", hex(4*startaddr), hex(msbs), hex(val))
  83             print("instr: %06x 0x%x %s %08x" % (4*startaddr, insn, code, val))
  84         startaddr += 1
  85         startaddr = startaddr & mask
  86
  87
  88 def set_dmi(dmi, addr, data):
  89     yield dmi.req_i.eq(1)
  90     yield dmi.addr_i.eq(addr)
  91     yield dmi.din.eq(data)
  92     yield dmi.we_i.eq(1)
  93     while True:
  94         ack = yield dmi.ack_o
  95         if ack:
  96             break
  97         yield
  98     yield
  99     yield dmi.req_i.eq(0)
 100     yield dmi.addr_i.eq(0)
 101     yield dmi.din.eq(0)
 102     yield dmi.we_i.eq(0)
 103     yield
 104
 105
 106 def get_dmi(dmi, addr):
 107     yield dmi.req_i.eq(1)
 108     yield dmi.addr_i.eq(addr)
 109     yield dmi.din.eq(0)
 110     yield dmi.we_i.eq(0)
 111     while True:
 112         ack = yield dmi.ack_o
 113         if ack:
 114             break
 115         yield
 116     yield  # wait one
 117     data = yield dmi.dout  # get data after ack valid for 1 cycle
 118     yield dmi.req_i.eq(0)
 119     yield dmi.addr_i.eq(0)
 120     yield dmi.we_i.eq(0)
 121     yield
 122     return data
 123
 124
 125 class TestRunner(FHDLTestCase):
 126     def __init__(self, tst_data, microwatt_mmu=False, rom=None,
 127                         svp64=True):
 128         super().__init__("run_all")
 129         self.test_data = tst_data
 130         self.microwatt_mmu = microwatt_mmu
 131         self.rom = rom
 132         self.svp64 = svp64
 133
 134     def run_all(self):
 135         m = Module()
 136         comb = m.d.comb
 137         pc_i = Signal(32)
 138         svstate_i = Signal(64)
 139
 140         if self.microwatt_mmu:
 141             ldst_ifacetype = 'test_mmu_cache_wb'
 142         else:
 143             ldst_ifacetype = 'test_bare_wb'
 144         imem_ifacetype = 'test_bare_wb'
 145
 146         pspec = TestMemPspec(ldst_ifacetype=ldst_ifacetype,
 147                              imem_ifacetype=imem_ifacetype,
 148                              addr_wid=48,
 149                              mask_wid=8,
 150                              imem_reg_wid=64,
 151                              # wb_data_width=32,
 152                              use_pll=False,
 153                              nocore=False,
 154                              xics=False,
 155                              gpio=False,
 156                              regreduce=True,
 157                              svp64=self.svp64,
 158                              mmu=self.microwatt_mmu,
 159                              reg_wid=64)
 160         #hard_reset = Signal(reset_less=True)
 161         issuer = TestIssuerInternal(pspec)
 162         # use DMI RESET command instead, this does actually work though
 163         #issuer = ResetInserter({'coresync': hard_reset,
 164         #                        'sync': hard_reset})(issuer)
 165         m.submodules.issuer = issuer
 166         imem = issuer.imem._get_memory()
 167         core = issuer.core
 168         dmi = issuer.dbg.dmi
 169         pdecode2 = issuer.pdecode2
 170         l0 = core.l0
 171         regreduce_en = pspec.regreduce_en == True
 172
 173         #simdec = create_pdecode()
 174         simdec2 = PowerDecode2(None, regreduce_en=regreduce_en)
 175         m.submodules.simdec2 = simdec2  # pain in the neck
 176
 177         # run core clock at same rate as test clock
 178         intclk = ClockSignal("coresync")
 179         comb += intclk.eq(ClockSignal())
 180
 181         comb += issuer.pc_i.data.eq(pc_i)
 182         comb += issuer.svstate_i.data.eq(svstate_i)
 183
 184         # nmigen Simulation
 185         sim = Simulator(m)
 186         sim.add_clock(1e-6)
 187
 188         def process():
 189
 190             # start in stopped
 191             yield from set_dmi(dmi, DBGCore.CTRL, 1<<DBGCtrl.STOP)
 192             yield
 193
 194             # get each test, completely reset the core, and run it
 195
 196             for test in self.test_data:
 197
 198                 # set up bigendian (TODO: don't do this, use MSR)
 199                 yield issuer.core_bigendian_i.eq(bigendian)
 200                 yield Settle()
 201
 202                 yield
 203                 yield
 204                 yield
 205                 yield
 206
 207                 print(test.name)
 208                 program = test.program
 209                 with self.subTest(test.name):
 210                     print("regs", test.regs)
 211                     print("sprs", test.sprs)
 212                     print("cr", test.cr)
 213                     print("mem", test.mem)
 214                     print("msr", test.msr)
 215                     print("assem", program.assembly)
 216                     gen = list(program.generate_instructions())
 217                     insncode = program.assembly.splitlines()
 218                     instructions = list(zip(gen, insncode))
 219
 220                     # set up the Simulator (which must track TestIssuer exactly)
 221                     sim = ISA(simdec2, test.regs, test.sprs, test.cr, test.mem,
 222                               test.msr,
 223                               initial_insns=gen, respect_pc=True,
 224                               disassembly=insncode,
 225                               bigendian=bigendian,
 226                               initial_svstate=test.svstate)
 227
 228                     # establish the TestIssuer context (mem, regs etc)
 229
 230                     pc = 0  # start address
 231                     counter = 0  # test to pause/start
 232
 233                     yield from setup_i_memory(imem, pc, instructions)
 234                     yield from setup_tst_memory(l0, test.mem)
 235                     yield from setup_regs(pdecode2, core, test)
 236
 237                     # set PC and SVSTATE
 238                     yield pc_i.eq(pc)
 239                     yield issuer.pc_i.ok.eq(1)
 240
 241                     initial_svstate = test.svstate
 242                     if isinstance(initial_svstate, int):
 243                         initial_svstate = SVP64State(initial_svstate)
 244                     yield svstate_i.eq(initial_svstate.value)
 245                     yield issuer.svstate_i.ok.eq(1)
 246                     yield
 247
 248                     print("instructions", instructions)
 249
 250                     # run the loop of the instructions on the current test
 251                     index = sim.pc.CIA.value//4
 252                     while index < len(instructions):
 253                         ins, code = instructions[index]
 254
 255                         print("instruction: 0x{:X}".format(ins & 0xffffffff))
 256                         print(index, code)
 257
 258                         if counter == 0:
 259                             # start the core
 260                             yield
 261                             yield from set_dmi(dmi, DBGCore.CTRL,
 262                                                1<<DBGCtrl.START)
 263                             yield issuer.pc_i.ok.eq(0) # no change PC after this
 264                             yield issuer.svstate_i.ok.eq(0) # ditto
 265                             yield
 266                             yield
 267
 268                         counter = counter + 1
 269
 270                         # wait until executed
 271                         while not (yield issuer.insn_done):
 272                             yield
 273
 274                         # set up simulated instruction (in simdec2)
 275                         try:
 276                             yield from sim.setup_one()
 277                         except KeyError:  # instruction not in imem: stop
 278                             break
 279                         yield Settle()
 280
 281                         # call simulated operation
 282                         print("sim", code)
 283                         yield from sim.execute_one()
 284                         yield Settle()
 285                         index = sim.pc.CIA.value//4
 286
 287                         terminated = yield issuer.dbg.terminated_o
 288                         print("terminated", terminated)
 289
 290                         if index >= len(instructions):
 291                             print ("index over, send dmi stop")
 292                             # stop at end
 293                             yield from set_dmi(dmi, DBGCore.CTRL,
 294                                                1<<DBGCtrl.STOP)
 295                             yield
 296                             yield
 297
 298                         # register check
 299                         yield from check_regs(self, sim, core, test, code)
 300
 301                         # Memory check
 302                         yield from check_mem(self, sim, core, test, code)
 303
 304                         terminated = yield issuer.dbg.terminated_o
 305                         print("terminated(2)", terminated)
 306                         if terminated:
 307                             break
 308
 309                 # stop at end
 310                 yield from set_dmi(dmi, DBGCore.CTRL, 1<<DBGCtrl.STOP)
 311                 yield
 312                 yield
 313
 314                 # TODO, here is where the static (expected) results
 315                 # can be checked: register check (TODO, memory check)
 316                 # see https://bugs.libre-soc.org/show_bug.cgi?id=686#c51
 317                 # yield from check_regs(self, sim, core, test, code,
 318                 #                       >>>expected_data<<<)
 319
 320                 # get CR
 321                 cr = yield from get_dmi(dmi, DBGCore.CR)
 322                 print("after test %s cr value %x" % (test.name, cr))
 323
 324                 # get XER
 325                 xer = yield from get_dmi(dmi, DBGCore.XER)
 326                 print("after test %s XER value %x" % (test.name, xer))
 327
 328                 # test of dmi reg get
 329                 for int_reg in range(32):
 330                     yield from set_dmi(dmi, DBGCore.GSPR_IDX, int_reg)
 331                     value = yield from get_dmi(dmi, DBGCore.GSPR_DATA)
 332
 333                     print("after test %s reg %2d value %x" %
 334                           (test.name, int_reg, value))
 335
 336                 # pull a reset
 337                 yield from set_dmi(dmi, DBGCore.CTRL, 1<<DBGCtrl.RESET)
 338                 yield
 339
 340         styles = {
 341             'dec': {'base': 'dec'},
 342             'bin': {'base': 'bin'},
 343             'closed': {'closed': True}
 344         }
 345
 346         traces = [
 347             'clk',
 348             ('state machines', 'closed', [
 349                 'fetch_pc_i_valid', 'fetch_pc_o_ready',
 350                 'fetch_fsm_state',
 351                 'fetch_insn_o_valid', 'fetch_insn_i_ready',
 352                 'pred_insn_i_valid', 'pred_insn_o_ready',
 353                 'fetch_predicate_state',
 354                 'pred_mask_o_valid', 'pred_mask_i_ready',
 355                 'issue_fsm_state',
 356                 'exec_insn_i_valid', 'exec_insn_o_ready',
 357                 'exec_fsm_state',
 358                 'exec_pc_o_valid', 'exec_pc_i_ready',
 359                 'insn_done', 'core_stop_o', 'pc_i_ok', 'pc_changed',
 360                 'is_last', 'dec2.no_out_vec']),
 361             {'comment': 'fetch and decode'},
 362             (None, 'dec', [
 363                 'cia[63:0]', 'nia[63:0]', 'pc[63:0]',
 364                 'cur_pc[63:0]', 'core_core_cia[63:0]']),
 365             'raw_insn_i[31:0]',
 366             'raw_opcode_in[31:0]', 'insn_type', 'dec2.dec2_exc_happened',
 367             ('svp64 decoding', 'closed', [
 368                 'svp64_rm[23:0]', ('dec2.extra[8:0]', 'bin'),
 369                 'dec2.sv_rm_dec.mode', 'dec2.sv_rm_dec.predmode',
 370                 'dec2.sv_rm_dec.ptype_in',
 371                 'dec2.sv_rm_dec.dstpred[2:0]', 'dec2.sv_rm_dec.srcpred[2:0]',
 372                 'dstmask[63:0]', 'srcmask[63:0]',
 373                 'dregread[4:0]', 'dinvert',
 374                 'sregread[4:0]', 'sinvert',
 375                 'core.int.pred__addr[4:0]', 'core.int.pred__data_o[63:0]',
 376                 'core.int.pred__ren']),
 377             ('register augmentation', 'dec', 'closed', [
 378                 {'comment': 'v3.0b registers'},
 379                 'dec2.dec_o.RT[4:0]',
 380                 'dec2.dec_a.RA[4:0]',
 381                 'dec2.dec_b.RB[4:0]',
 382                 ('Rdest', [
 383                     'dec2.o_svdec.reg_in[4:0]',
 384                     ('dec2.o_svdec.spec[2:0]', 'bin'),
 385                     'dec2.o_svdec.reg_out[6:0]']),
 386                 ('Rsrc1', [
 387                     'dec2.in1_svdec.reg_in[4:0]',
 388                     ('dec2.in1_svdec.spec[2:0]', 'bin'),
 389                     'dec2.in1_svdec.reg_out[6:0]']),
 390                 ('Rsrc1', [
 391                     'dec2.in2_svdec.reg_in[4:0]',
 392                     ('dec2.in2_svdec.spec[2:0]', 'bin'),
 393                     'dec2.in2_svdec.reg_out[6:0]']),
 394                 {'comment': 'SVP64 registers'},
 395                 'dec2.rego[6:0]', 'dec2.reg1[6:0]', 'dec2.reg2[6:0]'
 396             ]),
 397             {'comment': 'svp64 context'},
 398             'core_core_vl[6:0]', 'core_core_maxvl[6:0]',
 399             'core_core_srcstep[6:0]', 'next_srcstep[6:0]',
 400             'core_core_dststep[6:0]',
 401             {'comment': 'issue and execute'},
 402             'core.core_core_insn_type',
 403             (None, 'dec', [
 404                 'core_rego[6:0]', 'core_reg1[6:0]', 'core_reg2[6:0]']),
 405             'issue_i', 'busy_o',
 406             {'comment': 'dmi'},
 407             'dbg.dmi_req_i', 'dbg.dmi_ack_o',
 408             {'comment': 'instruction memory'},
 409             'imem.sram.rdport.memory(0)[63:0]',
 410             {'comment': 'registers'},
 411             # match with soc.regfile.regfiles.IntRegs port names
 412             'core.int.rp_src1.memory(0)[63:0]',
 413             'core.int.rp_src1.memory(1)[63:0]',
 414             'core.int.rp_src1.memory(2)[63:0]',
 415             'core.int.rp_src1.memory(3)[63:0]',
 416             'core.int.rp_src1.memory(4)[63:0]',
 417             'core.int.rp_src1.memory(5)[63:0]',
 418             'core.int.rp_src1.memory(6)[63:0]',
 419             'core.int.rp_src1.memory(7)[63:0]',
 420             'core.int.rp_src1.memory(9)[63:0]',
 421             'core.int.rp_src1.memory(10)[63:0]',
 422             'core.int.rp_src1.memory(13)[63:0]'
 423         ]
 424
 425         # PortInterface module path varies depending on MMU option
 426         if self.microwatt_mmu:
 427             pi_module = 'core.ldst0'
 428         else:
 429             pi_module = 'core.fus.ldst0'
 430
 431         traces += [('ld/st port interface', {'submodule': pi_module}, [
 432             'oper_r__insn_type',
 433             'ldst_port0_is_ld_i',
 434             'ldst_port0_is_st_i',
 435             'ldst_port0_busy_o',
 436             'ldst_port0_addr_i[47:0]',
 437             'ldst_port0_addr_i_ok',
 438             'ldst_port0_addr_ok_o',
 439             'ldst_port0_exc_happened',
 440             'ldst_port0_st_data_i[63:0]',
 441             'ldst_port0_st_data_i_ok',
 442             'ldst_port0_ld_data_o[63:0]',
 443             'ldst_port0_ld_data_o_ok',
 444             'exc_o_happened',
 445             'cancel'
 446         ])]
 447
 448         if self.microwatt_mmu:
 449             traces += [
 450                 {'comment': 'microwatt_mmu'},
 451                 'core.fus.mmu0.alu_mmu0.illegal',
 452                 'core.fus.mmu0.alu_mmu0.debug0[3:0]',
 453                 'core.fus.mmu0.alu_mmu0.mmu.state',
 454                 'core.fus.mmu0.alu_mmu0.mmu.pid[31:0]',
 455                 'core.fus.mmu0.alu_mmu0.mmu.prtbl[63:0]',
 456                 {'comment': 'wishbone_memory'},
 457                 'core.fus.mmu0.alu_mmu0.dcache.stb',
 458                 'core.fus.mmu0.alu_mmu0.dcache.cyc',
 459                 'core.fus.mmu0.alu_mmu0.dcache.we',
 460                 'core.fus.mmu0.alu_mmu0.dcache.ack',
 461                 'core.fus.mmu0.alu_mmu0.dcache.stall,'
 462             ]
 463
 464         write_gtkw("issuer_simulator.gtkw",
 465                    "issuer_simulator.vcd",
 466                    traces, styles, module='top.issuer')
 467
 468         # add run of instructions
 469         sim.add_sync_process(process)
 470
 471         # optionally, if a wishbone-based ROM is passed in, run that as an
 472         # extra emulated process
 473         if self.rom is not None:
 474             dcache = core.fus.fus["mmu0"].alu.dcache
 475             default_mem = self.rom
 476             sim.add_sync_process(wrap(wb_get(dcache, default_mem, "DCACHE")))
 477
 478         with sim.write_vcd("issuer_simulator.vcd"):
 479             sim.run()