1 """TestRunner class, runs TestIssuer instructions
5 * https://bugs.libre-soc.org/show_bug.cgi?id=363
6 * https://bugs.libre-soc.org/show_bug.cgi?id=686#c51
8 from nmigen
import Module
, Signal
, Cat
, ClockSignal
9 from nmigen
.hdl
.xfrm
import ResetInserter
12 # NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell
13 # Also, check out the cxxsim nmigen branch, and latest yosys from git
14 from nmutil
.sim_tmp_alternative
import Simulator
, Settle
16 from nmutil
.formaltest
import FHDLTestCase
17 from nmutil
.gtkw
import write_gtkw
18 from nmigen
.cli
import rtlil
19 from openpower
.decoder
.isa
.caller
import special_sprs
, SVP64State
20 from openpower
.decoder
.isa
.all
import ISA
21 from openpower
.endian
import bigendian
23 from openpower
.decoder
.power_decoder
import create_pdecode
24 from openpower
.decoder
.power_decoder2
import PowerDecode2
25 from soc
.regfile
.regfiles
import StateRegs
27 from soc
.simple
.issuer
import TestIssuerInternal
29 from soc
.config
.test
.test_loadstore
import TestMemPspec
30 from soc
.simple
.test
.test_core
import (setup_regs
, check_regs
, check_mem
,
33 from soc
.fu
.compunits
.test
.test_compunit
import (setup_tst_memory
,
35 from soc
.debug
.dmi
import DBGCore
, DBGCtrl
, DBGStat
36 from nmutil
.util
import wrap
37 from soc
.experiment
.test
.test_mmu_dcache
import wb_get
38 from openpower
.test
.state
import TestState
, StateRunner
41 def setup_i_memory(imem
, startaddr
, instructions
):
43 print("insn before, init mem", mem
.depth
, mem
.width
, mem
,
45 for i
in range(mem
.depth
):
46 yield mem
._array
[i
].eq(0)
48 startaddr
//= 4 # instructions are 32-bit
51 for ins
in instructions
:
52 if isinstance(ins
, tuple):
56 insn
= insn
& 0xffffffff
57 yield mem
._array
[startaddr
].eq(insn
)
60 print("instr: %06x 0x%x %s" % (4*startaddr
, insn
, code
))
62 startaddr
= startaddr
& mask
67 for ins
in instructions
:
68 if isinstance(ins
, tuple):
72 insn
= insn
& 0xffffffff
73 msbs
= (startaddr
>> 1) & mask
74 val
= yield mem
._array
[msbs
]
76 print("before set", hex(4*startaddr
),
77 hex(msbs
), hex(val
), hex(insn
))
78 lsb
= 1 if (startaddr
& 1) else 0
79 val
= (val |
(insn
<< (lsb
*32)))
81 yield mem
._array
[msbs
].eq(val
)
84 print("after set", hex(4*startaddr
), hex(msbs
), hex(val
))
85 print("instr: %06x 0x%x %s %08x" % (4*startaddr
, insn
, code
, val
))
87 startaddr
= startaddr
& mask
90 def set_dmi(dmi
, addr
, data
):
92 yield dmi
.addr_i
.eq(addr
)
93 yield dmi
.din
.eq(data
)
101 yield dmi
.req_i
.eq(0)
102 yield dmi
.addr_i
.eq(0)
108 def get_dmi(dmi
, addr
):
109 yield dmi
.req_i
.eq(1)
110 yield dmi
.addr_i
.eq(addr
)
114 ack
= yield dmi
.ack_o
119 data
= yield dmi
.dout
# get data after ack valid for 1 cycle
120 yield dmi
.req_i
.eq(0)
121 yield dmi
.addr_i
.eq(0)
127 class SimRunner(StateRunner
):
128 def __init__(self
, dut
, m
, pspec
):
131 regreduce_en
= pspec
.regreduce_en
== True
132 self
.simdec2
= simdec2
= PowerDecode2(None, regreduce_en
=regreduce_en
)
133 m
.submodules
.simdec2
= simdec2
# pain in the neck
135 def prepare_for_test(self
, test
):
138 def run_test(self
, instructions
, gen
, insncode
):
139 """run_sim_state - runs an ISACaller simulation
142 dut
, test
, simdec2
= self
.dut
, self
.test
, self
.simdec2
145 # set up the Simulator (which must track TestIssuer exactly)
146 sim
= ISA(simdec2
, test
.regs
, test
.sprs
, test
.cr
, test
.mem
,
148 initial_insns
=gen
, respect_pc
=True,
149 disassembly
=insncode
,
151 initial_svstate
=test
.svstate
)
153 # run the loop of the instructions on the current test
154 index
= sim
.pc
.CIA
.value
//4
155 while index
< len(instructions
):
156 ins
, code
= instructions
[index
]
158 print("sim instr: 0x{:X}".format(ins
& 0xffffffff))
161 # set up simulated instruction (in simdec2)
163 yield from sim
.setup_one()
164 except KeyError: # instruction not in imem: stop
168 # call simulated operation
170 yield from sim
.execute_one()
172 index
= sim
.pc
.CIA
.value
//4
174 # get sim register and memory TestState, add to list
175 state
= yield from TestState("sim", sim
, dut
, code
)
176 sim_states
.append(state
)
181 class HDLRunner(StateRunner
):
182 def __init__(self
, dut
, m
, pspec
):
184 self
.pc_i
= Signal(32)
185 self
.svstate_i
= Signal(64)
187 #hard_reset = Signal(reset_less=True)
188 self
.issuer
= TestIssuerInternal(pspec
)
189 # use DMI RESET command instead, this does actually work though
190 #issuer = ResetInserter({'coresync': hard_reset,
191 # 'sync': hard_reset})(issuer)
192 m
.submodules
.issuer
= self
.issuer
193 self
.dmi
= self
.issuer
.dbg
.dmi
196 comb
+= self
.issuer
.pc_i
.data
.eq(self
.pc_i
)
197 comb
+= self
.issuer
.svstate_i
.data
.eq(self
.svstate_i
)
199 def prepare_for_test(self
, test
):
202 # set up bigendian (TODO: don't do this, use MSR)
203 yield self
.issuer
.core_bigendian_i
.eq(bigendian
)
211 def setup_during_test(self
):
212 yield from set_dmi(self
.dmi
, DBGCore
.CTRL
, 1<<DBGCtrl
.STOP
)
215 def run_test(self
, instructions
):
216 """run_hdl_state - runs a TestIssuer nmigen HDL simulation
219 imem
= self
.issuer
.imem
._get
_memory
()
220 core
= self
.issuer
.core
221 dmi
= self
.issuer
.dbg
.dmi
222 pdecode2
= self
.issuer
.pdecode2
226 # establish the TestIssuer context (mem, regs etc)
228 pc
= 0 # start address
229 counter
= 0 # test to pause/start
231 yield from setup_i_memory(imem
, pc
, instructions
)
232 #yield from setup_tst_memory(l0, self.test.mem)
233 yield from setup_regs(pdecode2
, core
, self
.test
)
236 yield self
.pc_i
.eq(pc
)
237 yield self
.issuer
.pc_i
.ok
.eq(1)
239 # copy initial SVSTATE
240 initial_svstate
= copy(self
.test
.svstate
)
241 if isinstance(initial_svstate
, int):
242 initial_svstate
= SVP64State(initial_svstate
)
243 yield self
.svstate_i
.eq(initial_svstate
.value
)
244 yield self
.issuer
.svstate_i
.ok
.eq(1)
247 print("instructions", instructions
)
249 # run the loop of the instructions on the current test
250 index
= (yield self
.issuer
.cur_state
.pc
) // 4
251 while index
< len(instructions
):
252 ins
, code
= instructions
[index
]
254 print("hdl instr: 0x{:X}".format(ins
& 0xffffffff))
260 yield from set_dmi(dmi
, DBGCore
.CTRL
,
262 yield self
.issuer
.pc_i
.ok
.eq(0) # no change PC after this
263 yield self
.issuer
.svstate_i
.ok
.eq(0) # ditto
267 counter
= counter
+ 1
269 # wait until executed
270 while not (yield self
.issuer
.insn_done
):
275 index
= (yield self
.issuer
.cur_state
.pc
) // 4
277 terminated
= yield self
.issuer
.dbg
.terminated_o
278 print("terminated", terminated
)
280 if index
< len(instructions
):
281 # Get HDL mem and state
282 state
= yield from TestState("hdl", core
, self
.dut
,
284 hdl_states
.append(state
)
286 if index
>= len(instructions
):
287 print ("index over, send dmi stop")
289 yield from set_dmi(dmi
, DBGCore
.CTRL
,
294 terminated
= yield self
.issuer
.dbg
.terminated_o
295 print("terminated(2)", terminated
)
302 yield from set_dmi(self
.dmi
, DBGCore
.CTRL
, 1<<DBGCtrl
.STOP
)
306 # TODO, here is where the static (expected) results
307 # can be checked: register check (TODO, memory check)
308 # see https://bugs.libre-soc.org/show_bug.cgi?id=686#c51
309 # yield from check_regs(self, sim, core, test, code,
310 # >>>expected_data<<<)
313 cr
= yield from get_dmi(self
.dmi
, DBGCore
.CR
)
314 print("after test %s cr value %x" % (self
.test
.name
, cr
))
317 xer
= yield from get_dmi(self
.dmi
, DBGCore
.XER
)
318 print("after test %s XER value %x" % (self
.test
.name
, xer
))
320 # test of dmi reg get
321 for int_reg
in range(32):
322 yield from set_dmi(self
.dmi
, DBGCore
.GSPR_IDX
, int_reg
)
323 value
= yield from get_dmi(self
.dmi
, DBGCore
.GSPR_DATA
)
325 print("after test %s reg %2d value %x" %
326 (self
.test
.name
, int_reg
, value
))
329 yield from set_dmi(self
.dmi
, DBGCore
.CTRL
, 1<<DBGCtrl
.RESET
)
333 class TestRunner(FHDLTestCase
):
334 def __init__(self
, tst_data
, microwatt_mmu
=False, rom
=None,
335 svp64
=True, run_hdl
=True, run_sim
=True):
336 super().__init
__("run_all")
337 self
.test_data
= tst_data
338 self
.microwatt_mmu
= microwatt_mmu
341 self
.run_hdl
= run_hdl
342 self
.run_sim
= run_sim
347 if self
.microwatt_mmu
:
348 ldst_ifacetype
= 'test_mmu_cache_wb'
350 ldst_ifacetype
= 'test_bare_wb'
351 imem_ifacetype
= 'test_bare_wb'
353 pspec
= TestMemPspec(ldst_ifacetype
=ldst_ifacetype
,
354 imem_ifacetype
=imem_ifacetype
,
365 mmu
=self
.microwatt_mmu
,
368 ###### SETUP PHASE #######
369 # StateRunner.setup_for_test()
372 hdlrun
= HDLRunner(self
, m
, pspec
)
375 simrun
= SimRunner(self
, m
, pspec
)
377 # run core clock at same rate as test clock
378 intclk
= ClockSignal("coresync")
379 comb
+= intclk
.eq(ClockSignal())
381 # nmigen Simulation - everything runs around this, so it
382 # still has to be created.
388 ###### PREPARATION PHASE AT START OF RUNNING #######
389 # StateRunner.setup_during_test()
392 simrun
.setup_during_test() # TODO, some arguments?
395 yield from hdlrun
.setup_during_test()
397 # get each test, completely reset the core, and run it
399 for test
in self
.test_data
:
401 with self
.subTest(test
.name
):
403 ###### PREPARATION PHASE AT START OF TEST #######
404 # StateRunner.prepare_for_test()
407 simrun
.prepare_for_test(test
)
410 yield from hdlrun
.prepare_for_test(test
)
413 program
= test
.program
414 print("regs", test
.regs
)
415 print("sprs", test
.sprs
)
417 print("mem", test
.mem
)
418 print("msr", test
.msr
)
419 print("assem", program
.assembly
)
420 gen
= list(program
.generate_instructions())
421 insncode
= program
.assembly
.splitlines()
422 instructions
= list(zip(gen
, insncode
))
424 ###### RUNNING OF EACH TEST #######
425 # StateRunner.step_test()
427 # Run two tests (TODO, move these to functions)
428 # * first the Simulator, collate a batch of results
429 # * then the HDL, likewise
430 # (actually, the other way round because running
431 # Simulator somehow modifies the test state!)
432 # * finally, compare all the results
438 hdl_states
= yield from hdlrun
.run_test(instructions
)
445 sim_states
= yield from simrun
.run_test(
449 ###### COMPARING THE TESTS #######
456 last_sim
= copy(sim_states
[-1])
458 last_sim
= copy(hdl_states
[-1])
460 last_sim
= None # err what are you doing??
462 if self
.run_hdl
and self
.run_sim
:
463 for simstate
, hdlstate
in zip(sim_states
, hdl_states
):
464 simstate
.compare(hdlstate
) # register check
465 simstate
.compare_mem(hdlstate
) # memory check
469 for state
in hdl_states
:
474 for state
in sim_states
:
477 # compare against expected results
478 if test
.expected
is not None:
479 # have to put these in manually
480 test
.expected
.to_test
= test
.expected
481 test
.expected
.dut
= self
482 test
.expected
.state_type
= "expected"
483 test
.expected
.code
= 0
484 # do actual comparison, against last item
485 last_sim
.compare(test
.expected
)
487 if self
.run_hdl
and self
.run_sim
:
488 self
.assertTrue(len(hdl_states
) == len(sim_states
),
489 "number of instructions run not the same")
491 ###### END OF A TEST #######
492 # StateRunner.end_test()
495 simrun
.end_test() # TODO, some arguments?
498 yield from hdlrun
.end_test()
500 yield from set_dmi(hdlrun.dmi, DBGCore.CTRL, 1<<DBGCtrl.STOP)
504 # TODO, here is where the static (expected) results
505 # can be checked: register check (TODO, memory check)
506 # see https://bugs.libre-soc.org/show_bug.cgi?id=686#c51
507 # yield from check_regs(self, sim, core, test, code,
508 # >>>expected_data<<<)
511 cr = yield from get_dmi(hdlrun.dmi, DBGCore.CR)
512 print("after test %s cr value %x" % (test.name, cr))
515 xer = yield from get_dmi(hdlrun.dmi, DBGCore.XER)
516 print("after test %s XER value %x" % (test.name, xer))
518 # test of dmi reg get
519 for int_reg in range(32):
520 yield from set_dmi(hdlrun.dmi, DBGCore.GSPR_IDX, int_reg)
521 value = yield from get_dmi(hdlrun.dmi, DBGCore.GSPR_DATA)
523 print("after test %s reg %2d value %x" %
524 (test.name, int_reg, value))
527 yield from set_dmi(hdlrun.dmi, DBGCore.CTRL, 1<<DBGCtrl.RESET)
530 ###### END OF EVERYTHING (but none needs doing, still call fn) #######
531 # StateRunner.cleanup()
534 simrun
.cleanup() # TODO, some arguments?
540 'dec': {'base': 'dec'},
541 'bin': {'base': 'bin'},
542 'closed': {'closed': True}
547 ('state machines', 'closed', [
548 'fetch_pc_i_valid', 'fetch_pc_o_ready',
550 'fetch_insn_o_valid', 'fetch_insn_i_ready',
551 'pred_insn_i_valid', 'pred_insn_o_ready',
552 'fetch_predicate_state',
553 'pred_mask_o_valid', 'pred_mask_i_ready',
555 'exec_insn_i_valid', 'exec_insn_o_ready',
557 'exec_pc_o_valid', 'exec_pc_i_ready',
558 'insn_done', 'core_stop_o', 'pc_i_ok', 'pc_changed',
559 'is_last', 'dec2.no_out_vec']),
560 {'comment': 'fetch and decode'},
562 'cia[63:0]', 'nia[63:0]', 'pc[63:0]',
563 'cur_pc[63:0]', 'core_core_cia[63:0]']),
565 'raw_opcode_in[31:0]', 'insn_type', 'dec2.dec2_exc_happened',
566 ('svp64 decoding', 'closed', [
567 'svp64_rm[23:0]', ('dec2.extra[8:0]', 'bin'),
568 'dec2.sv_rm_dec.mode', 'dec2.sv_rm_dec.predmode',
569 'dec2.sv_rm_dec.ptype_in',
570 'dec2.sv_rm_dec.dstpred[2:0]', 'dec2.sv_rm_dec.srcpred[2:0]',
571 'dstmask[63:0]', 'srcmask[63:0]',
572 'dregread[4:0]', 'dinvert',
573 'sregread[4:0]', 'sinvert',
574 'core.int.pred__addr[4:0]', 'core.int.pred__data_o[63:0]',
575 'core.int.pred__ren']),
576 ('register augmentation', 'dec', 'closed', [
577 {'comment': 'v3.0b registers'},
578 'dec2.dec_o.RT[4:0]',
579 'dec2.dec_a.RA[4:0]',
580 'dec2.dec_b.RB[4:0]',
582 'dec2.o_svdec.reg_in[4:0]',
583 ('dec2.o_svdec.spec[2:0]', 'bin'),
584 'dec2.o_svdec.reg_out[6:0]']),
586 'dec2.in1_svdec.reg_in[4:0]',
587 ('dec2.in1_svdec.spec[2:0]', 'bin'),
588 'dec2.in1_svdec.reg_out[6:0]']),
590 'dec2.in2_svdec.reg_in[4:0]',
591 ('dec2.in2_svdec.spec[2:0]', 'bin'),
592 'dec2.in2_svdec.reg_out[6:0]']),
593 {'comment': 'SVP64 registers'},
594 'dec2.rego[6:0]', 'dec2.reg1[6:0]', 'dec2.reg2[6:0]'
596 {'comment': 'svp64 context'},
597 'core_core_vl[6:0]', 'core_core_maxvl[6:0]',
598 'core_core_srcstep[6:0]', 'next_srcstep[6:0]',
599 'core_core_dststep[6:0]',
600 {'comment': 'issue and execute'},
601 'core.core_core_insn_type',
603 'core_rego[6:0]', 'core_reg1[6:0]', 'core_reg2[6:0]']),
606 'dbg.dmi_req_i', 'dbg.dmi_ack_o',
607 {'comment': 'instruction memory'},
608 'imem.sram.rdport.memory(0)[63:0]',
609 {'comment': 'registers'},
610 # match with soc.regfile.regfiles.IntRegs port names
611 'core.int.rp_src1.memory(0)[63:0]',
612 'core.int.rp_src1.memory(1)[63:0]',
613 'core.int.rp_src1.memory(2)[63:0]',
614 'core.int.rp_src1.memory(3)[63:0]',
615 'core.int.rp_src1.memory(4)[63:0]',
616 'core.int.rp_src1.memory(5)[63:0]',
617 'core.int.rp_src1.memory(6)[63:0]',
618 'core.int.rp_src1.memory(7)[63:0]',
619 'core.int.rp_src1.memory(9)[63:0]',
620 'core.int.rp_src1.memory(10)[63:0]',
621 'core.int.rp_src1.memory(13)[63:0]'
624 # PortInterface module path varies depending on MMU option
625 if self
.microwatt_mmu
:
626 pi_module
= 'core.ldst0'
628 pi_module
= 'core.fus.ldst0'
630 traces
+= [('ld/st port interface', {'submodule': pi_module
}, [
632 'ldst_port0_is_ld_i',
633 'ldst_port0_is_st_i',
635 'ldst_port0_addr_i[47:0]',
636 'ldst_port0_addr_i_ok',
637 'ldst_port0_addr_ok_o',
638 'ldst_port0_exc_happened',
639 'ldst_port0_st_data_i[63:0]',
640 'ldst_port0_st_data_i_ok',
641 'ldst_port0_ld_data_o[63:0]',
642 'ldst_port0_ld_data_o_ok',
647 if self
.microwatt_mmu
:
649 {'comment': 'microwatt_mmu'},
650 'core.fus.mmu0.alu_mmu0.illegal',
651 'core.fus.mmu0.alu_mmu0.debug0[3:0]',
652 'core.fus.mmu0.alu_mmu0.mmu.state',
653 'core.fus.mmu0.alu_mmu0.mmu.pid[31:0]',
654 'core.fus.mmu0.alu_mmu0.mmu.prtbl[63:0]',
655 {'comment': 'wishbone_memory'},
656 'core.fus.mmu0.alu_mmu0.dcache.stb',
657 'core.fus.mmu0.alu_mmu0.dcache.cyc',
658 'core.fus.mmu0.alu_mmu0.dcache.we',
659 'core.fus.mmu0.alu_mmu0.dcache.ack',
660 'core.fus.mmu0.alu_mmu0.dcache.stall,'
663 write_gtkw("issuer_simulator.gtkw",
664 "issuer_simulator.vcd",
665 traces
, styles
, module
='top.issuer')
667 # add run of instructions
668 sim
.add_sync_process(process
)
670 # optionally, if a wishbone-based ROM is passed in, run that as an
671 # extra emulated process
672 if self
.rom
is not None:
673 dcache
= core
.fus
.fus
["mmu0"].alu
.dcache
674 default_mem
= self
.rom
675 sim
.add_sync_process(wrap(wb_get(dcache
, default_mem
, "DCACHE")))
677 with sim
.write_vcd("issuer_simulator.vcd"):