1 """TestRunner class, runs TestIssuer instructions
5 * https://bugs.libre-soc.org/show_bug.cgi?id=363
7 from nmigen
import Module
, Signal
, Cat
, ClockSignal
8 from nmigen
.hdl
.xfrm
import ResetInserter
10 # NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell
11 # Also, check out the cxxsim nmigen branch, and latest yosys from git
12 from nmutil
.sim_tmp_alternative
import Simulator
, Settle
14 from nmutil
.formaltest
import FHDLTestCase
15 from nmutil
.gtkw
import write_gtkw
16 from nmigen
.cli
import rtlil
17 from openpower
.decoder
.isa
.caller
import special_sprs
, SVP64State
18 from openpower
.decoder
.isa
.all
import ISA
19 from openpower
.endian
import bigendian
21 from openpower
.decoder
.power_decoder
import create_pdecode
22 from openpower
.decoder
.power_decoder2
import PowerDecode2
23 from soc
.regfile
.regfiles
import StateRegs
25 from soc
.simple
.issuer
import TestIssuerInternal
27 from soc
.config
.test
.test_loadstore
import TestMemPspec
28 from soc
.simple
.test
.test_core
import (setup_regs
, check_regs
,
31 from soc
.fu
.compunits
.test
.test_compunit
import (setup_test_memory
,
33 from soc
.debug
.dmi
import DBGCore
, DBGCtrl
, DBGStat
34 from nmutil
.util
import wrap
35 from soc
.experiment
.test
.test_mmu_dcache
import wb_get
38 def setup_i_memory(imem
, startaddr
, instructions
):
40 print("insn before, init mem", mem
.depth
, mem
.width
, mem
,
42 for i
in range(mem
.depth
):
43 yield mem
._array
[i
].eq(0)
45 startaddr
//= 4 # instructions are 32-bit
48 for ins
in instructions
:
49 if isinstance(ins
, tuple):
53 insn
= insn
& 0xffffffff
54 yield mem
._array
[startaddr
].eq(insn
)
57 print("instr: %06x 0x%x %s" % (4*startaddr
, insn
, code
))
59 startaddr
= startaddr
& mask
64 for ins
in instructions
:
65 if isinstance(ins
, tuple):
69 insn
= insn
& 0xffffffff
70 msbs
= (startaddr
>> 1) & mask
71 val
= yield mem
._array
[msbs
]
73 print("before set", hex(4*startaddr
),
74 hex(msbs
), hex(val
), hex(insn
))
75 lsb
= 1 if (startaddr
& 1) else 0
76 val
= (val |
(insn
<< (lsb
*32)))
78 yield mem
._array
[msbs
].eq(val
)
81 print("after set", hex(4*startaddr
), hex(msbs
), hex(val
))
82 print("instr: %06x 0x%x %s %08x" % (4*startaddr
, insn
, code
, val
))
84 startaddr
= startaddr
& mask
87 def set_dmi(dmi
, addr
, data
):
89 yield dmi
.addr_i
.eq(addr
)
90 yield dmi
.din
.eq(data
)
99 yield dmi
.addr_i
.eq(0)
105 def get_dmi(dmi
, addr
):
106 yield dmi
.req_i
.eq(1)
107 yield dmi
.addr_i
.eq(addr
)
111 ack
= yield dmi
.ack_o
116 data
= yield dmi
.dout
# get data after ack valid for 1 cycle
117 yield dmi
.req_i
.eq(0)
118 yield dmi
.addr_i
.eq(0)
124 class TestRunner(FHDLTestCase
):
125 def __init__(self
, tst_data
, microwatt_mmu
=False, rom
=None,
127 super().__init
__("run_all")
128 self
.test_data
= tst_data
129 self
.microwatt_mmu
= microwatt_mmu
137 svstate_i
= Signal(32)
139 if self
.microwatt_mmu
:
140 ldst_ifacetype
= 'test_mmu_cache_wb'
142 ldst_ifacetype
= 'test_bare_wb'
143 imem_ifacetype
= 'test_bare_wb'
145 pspec
= TestMemPspec(ldst_ifacetype
=ldst_ifacetype
,
146 imem_ifacetype
=imem_ifacetype
,
157 mmu
=self
.microwatt_mmu
,
159 #hard_reset = Signal(reset_less=True)
160 issuer
= TestIssuerInternal(pspec
)
161 # use DMI RESET command instead, this does actually work though
162 #issuer = ResetInserter({'coresync': hard_reset,
163 # 'sync': hard_reset})(issuer)
164 m
.submodules
.issuer
= issuer
165 imem
= issuer
.imem
._get
_memory
()
168 pdecode2
= issuer
.pdecode2
170 regreduce_en
= pspec
.regreduce_en
== True
172 # copy of the decoder for simulator
173 simdec
= create_pdecode()
174 simdec2
= PowerDecode2(simdec
, regreduce_en
=regreduce_en
)
175 m
.submodules
.simdec2
= simdec2
# pain in the neck
177 # run core clock at same rate as test clock
178 intclk
= ClockSignal("coresync")
179 comb
+= intclk
.eq(ClockSignal())
181 comb
+= issuer
.pc_i
.data
.eq(pc_i
)
182 comb
+= issuer
.svstate_i
.data
.eq(svstate_i
)
191 yield from set_dmi(dmi
, DBGCore
.CTRL
, 1<<DBGCtrl
.STOP
)
194 # get each test, completely reset the core, and run it
196 for test
in self
.test_data
:
198 # set up bigendian (TODO: don't do this, use MSR)
199 yield issuer
.core_bigendian_i
.eq(bigendian
)
208 program
= test
.program
209 self
.subTest(test
.name
)
210 print("regs", test
.regs
)
211 print("sprs", test
.sprs
)
213 print("mem", test
.mem
)
214 print("msr", test
.msr
)
215 print("assem", program
.assembly
)
216 gen
= list(program
.generate_instructions())
217 insncode
= program
.assembly
.splitlines()
218 instructions
= list(zip(gen
, insncode
))
220 # set up the Simulator (which must track TestIssuer exactly)
221 sim
= ISA(simdec2
, test
.regs
, test
.sprs
, test
.cr
, test
.mem
,
223 initial_insns
=gen
, respect_pc
=True,
224 disassembly
=insncode
,
226 initial_svstate
=test
.svstate
)
228 # establish the TestIssuer context (mem, regs etc)
230 pc
= 0 # start address
231 counter
= 0 # test to pause/start
233 yield from setup_i_memory(imem
, pc
, instructions
)
234 yield from setup_test_memory(l0
, sim
)
235 yield from setup_regs(pdecode2
, core
, test
)
239 yield issuer
.pc_i
.ok
.eq(1)
241 initial_svstate
= test
.svstate
242 if isinstance(initial_svstate
, int):
243 initial_svstate
= SVP64State(initial_svstate
)
244 yield svstate_i
.eq(initial_svstate
.spr
.value
)
245 yield issuer
.svstate_i
.ok
.eq(1)
248 print("instructions", instructions
)
250 # run the loop of the instructions on the current test
251 index
= sim
.pc
.CIA
.value
//4
252 while index
< len(instructions
):
253 ins
, code
= instructions
[index
]
255 print("instruction: 0x{:X}".format(ins
& 0xffffffff))
261 yield from set_dmi(dmi
, DBGCore
.CTRL
, 1<<DBGCtrl
.START
)
262 yield issuer
.pc_i
.ok
.eq(0) # no change PC after this
263 yield issuer
.svstate_i
.ok
.eq(0) # ditto
267 counter
= counter
+ 1
269 # wait until executed
270 while not (yield issuer
.insn_done
):
273 # set up simulated instruction (in simdec2)
275 yield from sim
.setup_one()
276 except KeyError: # indicates instruction not in imem: stop
280 # call simulated operation
282 yield from sim
.execute_one()
284 index
= sim
.pc
.CIA
.value
//4
286 terminated
= yield issuer
.dbg
.terminated_o
287 print("terminated", terminated
)
289 if index
>= len(instructions
):
290 print ("index over, send dmi stop")
292 yield from set_dmi(dmi
, DBGCore
.CTRL
, 1<<DBGCtrl
.STOP
)
297 yield from check_regs(self
, sim
, core
, test
, code
)
300 yield from check_sim_memory(self
, l0
, sim
, code
)
302 terminated
= yield issuer
.dbg
.terminated_o
303 print("terminated(2)", terminated
)
308 yield from set_dmi(dmi
, DBGCore
.CTRL
, 1<<DBGCtrl
.STOP
)
313 cr
= yield from get_dmi(dmi
, DBGCore
.CR
)
314 print("after test %s cr value %x" % (test
.name
, cr
))
317 xer
= yield from get_dmi(dmi
, DBGCore
.XER
)
318 print("after test %s XER value %x" % (test
.name
, xer
))
320 # test of dmi reg get
321 for int_reg
in range(32):
322 yield from set_dmi(dmi
, DBGCore
.GSPR_IDX
, int_reg
)
323 value
= yield from get_dmi(dmi
, DBGCore
.GSPR_DATA
)
325 print("after test %s reg %2d value %x" %
326 (test
.name
, int_reg
, value
))
329 yield from set_dmi(dmi
, DBGCore
.CTRL
, 1<<DBGCtrl
.RESET
)
333 'dec': {'base': 'dec'},
334 'bin': {'base': 'bin'},
335 'closed': {'closed': True}
340 ('state machines', 'closed', [
341 'fetch_pc_valid_i', 'fetch_pc_ready_o',
343 'fetch_insn_valid_o', 'fetch_insn_ready_i',
344 'pred_insn_valid_i', 'pred_insn_ready_o',
345 'fetch_predicate_state',
346 'pred_mask_valid_o', 'pred_mask_ready_i',
348 'exec_insn_valid_i', 'exec_insn_ready_o',
350 'exec_pc_valid_o', 'exec_pc_ready_i',
351 'insn_done', 'core_stop_o', 'pc_i_ok', 'pc_changed',
352 'is_last', 'dec2.no_out_vec']),
353 {'comment': 'fetch and decode'},
355 'cia[63:0]', 'nia[63:0]', 'pc[63:0]',
356 'cur_pc[63:0]', 'core_core_cia[63:0]']),
358 'raw_opcode_in[31:0]', 'insn_type',
359 ('svp64 decoding', 'closed', [
360 'svp64_rm[23:0]', ('dec2.extra[8:0]', 'bin'),
361 'dec2.sv_rm_dec.mode', 'dec2.sv_rm_dec.predmode',
362 'dec2.sv_rm_dec.ptype_in',
363 'dec2.sv_rm_dec.dstpred[2:0]', 'dec2.sv_rm_dec.srcpred[2:0]',
364 'dstmask[63:0]', 'srcmask[63:0]',
365 'dregread[4:0]', 'dinvert',
366 'sregread[4:0]', 'sinvert',
367 'core.int.pred__addr[4:0]', 'core.int.pred__data_o[63:0]',
368 'core.int.pred__ren']),
369 ('register augmentation', 'dec', 'closed', [
370 {'comment': 'v3.0b registers'},
371 'dec2.dec_o.RT[4:0]',
372 'dec2.dec_a.RA[4:0]',
373 'dec2.dec_b.RB[4:0]',
375 'dec2.o_svdec.reg_in[4:0]',
376 ('dec2.o_svdec.spec[2:0]', 'bin'),
377 'dec2.o_svdec.reg_out[6:0]']),
379 'dec2.in1_svdec.reg_in[4:0]',
380 ('dec2.in1_svdec.spec[2:0]', 'bin'),
381 'dec2.in1_svdec.reg_out[6:0]']),
383 'dec2.in2_svdec.reg_in[4:0]',
384 ('dec2.in2_svdec.spec[2:0]', 'bin'),
385 'dec2.in2_svdec.reg_out[6:0]']),
386 {'comment': 'SVP64 registers'},
387 'dec2.rego[6:0]', 'dec2.reg1[6:0]', 'dec2.reg2[6:0]'
389 {'comment': 'svp64 context'},
390 'core_core_vl[6:0]', 'core_core_maxvl[6:0]',
391 'core_core_srcstep[6:0]', 'next_srcstep[6:0]',
392 'core_core_dststep[6:0]',
393 {'comment': 'issue and execute'},
394 'core.core_core_insn_type',
396 'core_rego[6:0]', 'core_reg1[6:0]', 'core_reg2[6:0]']),
399 'dbg.dmi_req_i', 'dbg.dmi_ack_o',
400 {'comment': 'instruction memory'},
401 'imem.sram.rdport.memory(0)[63:0]',
402 {'comment': 'registers'},
403 # match with soc.regfile.regfiles.IntRegs port names
404 'core.int.rp_src1.memory(0)[63:0]',
405 'core.int.rp_src1.memory(1)[63:0]',
406 'core.int.rp_src1.memory(2)[63:0]',
407 'core.int.rp_src1.memory(3)[63:0]',
408 'core.int.rp_src1.memory(4)[63:0]',
409 'core.int.rp_src1.memory(5)[63:0]',
410 'core.int.rp_src1.memory(6)[63:0]',
411 'core.int.rp_src1.memory(7)[63:0]',
412 'core.int.rp_src1.memory(9)[63:0]',
413 'core.int.rp_src1.memory(10)[63:0]',
414 'core.int.rp_src1.memory(13)[63:0]',
417 if self
.microwatt_mmu
:
419 {'comment': 'microwatt_mmu'},
420 'core.fus.mmu0.alu_mmu0.illegal',
421 'core.fus.mmu0.alu_mmu0.debug0[3:0]',
422 'core.fus.mmu0.alu_mmu0.mmu.state',
423 'core.fus.mmu0.alu_mmu0.mmu.pid[31:0]',
424 'core.fus.mmu0.alu_mmu0.mmu.prtbl[63:0]',
425 {'comment': 'wishbone_memory'},
426 'core.fus.mmu0.alu_mmu0.dcache.stb',
427 'core.fus.mmu0.alu_mmu0.dcache.cyc',
428 'core.fus.mmu0.alu_mmu0.dcache.we',
429 'core.fus.mmu0.alu_mmu0.dcache.ack',
430 'core.fus.mmu0.alu_mmu0.dcache.stall,'
433 write_gtkw("issuer_simulator.gtkw",
434 "issuer_simulator.vcd",
435 traces
, styles
, module
='top.issuer')
437 # add run of instructions
438 sim
.add_sync_process(process
)
440 # optionally, if a wishbone-based ROM is passed in, run that as an
441 # extra emulated process
442 if self
.rom
is not None:
443 dcache
= core
.fus
.fus
["mmu0"].alu
.dcache
444 default_mem
= self
.rom
445 sim
.add_sync_process(wrap(wb_get(dcache
, default_mem
, "DCACHE")))
447 with sim
.write_vcd("issuer_simulator.vcd"):