1 """TestRunner class, runs TestIssuer instructions
5 * https://bugs.libre-soc.org/show_bug.cgi?id=363
6 * https://bugs.libre-soc.org/show_bug.cgi?id=686#c51
8 from nmigen
import Module
, Signal
, Cat
, ClockSignal
9 from nmigen
.hdl
.xfrm
import ResetInserter
12 # NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell
13 # Also, check out the cxxsim nmigen branch, and latest yosys from git
14 from nmutil
.sim_tmp_alternative
import Simulator
, Settle
16 from nmutil
.formaltest
import FHDLTestCase
17 from nmutil
.gtkw
import write_gtkw
18 from nmigen
.cli
import rtlil
19 from openpower
.decoder
.isa
.caller
import special_sprs
, SVP64State
20 from openpower
.decoder
.isa
.all
import ISA
21 from openpower
.endian
import bigendian
23 from openpower
.decoder
.power_decoder
import create_pdecode
24 from openpower
.decoder
.power_decoder2
import PowerDecode2
25 from soc
.regfile
.regfiles
import StateRegs
27 from soc
.simple
.issuer
import TestIssuerInternal
29 from soc
.config
.test
.test_loadstore
import TestMemPspec
30 from soc
.simple
.test
.test_core
import (setup_regs
, check_regs
, check_mem
,
33 from soc
.fu
.compunits
.test
.test_compunit
import (setup_tst_memory
,
35 from soc
.debug
.dmi
import DBGCore
, DBGCtrl
, DBGStat
36 from nmutil
.util
import wrap
37 from soc
.experiment
.test
.test_mmu_dcache
import wb_get
38 from openpower
.test
.state
import TestState
, StateRunner
41 def setup_i_memory(imem
, startaddr
, instructions
):
43 print("insn before, init mem", mem
.depth
, mem
.width
, mem
,
45 for i
in range(mem
.depth
):
46 yield mem
._array
[i
].eq(0)
48 startaddr
//= 4 # instructions are 32-bit
51 for ins
in instructions
:
52 if isinstance(ins
, tuple):
56 insn
= insn
& 0xffffffff
57 yield mem
._array
[startaddr
].eq(insn
)
60 print("instr: %06x 0x%x %s" % (4*startaddr
, insn
, code
))
62 startaddr
= startaddr
& mask
67 for ins
in instructions
:
68 if isinstance(ins
, tuple):
72 insn
= insn
& 0xffffffff
73 msbs
= (startaddr
>> 1) & mask
74 val
= yield mem
._array
[msbs
]
76 print("before set", hex(4*startaddr
),
77 hex(msbs
), hex(val
), hex(insn
))
78 lsb
= 1 if (startaddr
& 1) else 0
79 val
= (val |
(insn
<< (lsb
*32)))
81 yield mem
._array
[msbs
].eq(val
)
84 print("after set", hex(4*startaddr
), hex(msbs
), hex(val
))
85 print("instr: %06x 0x%x %s %08x" % (4*startaddr
, insn
, code
, val
))
87 startaddr
= startaddr
& mask
90 def set_dmi(dmi
, addr
, data
):
92 yield dmi
.addr_i
.eq(addr
)
93 yield dmi
.din
.eq(data
)
101 yield dmi
.req_i
.eq(0)
102 yield dmi
.addr_i
.eq(0)
108 def get_dmi(dmi
, addr
):
109 yield dmi
.req_i
.eq(1)
110 yield dmi
.addr_i
.eq(addr
)
114 ack
= yield dmi
.ack_o
119 data
= yield dmi
.dout
# get data after ack valid for 1 cycle
120 yield dmi
.req_i
.eq(0)
121 yield dmi
.addr_i
.eq(0)
127 class SimRunner(StateRunner
):
128 def __init__(self
, dut
, m
, pspec
):
129 super().__init
__("sim", SimRunner
)
132 regreduce_en
= pspec
.regreduce_en
== True
133 self
.simdec2
= simdec2
= PowerDecode2(None, regreduce_en
=regreduce_en
)
134 m
.submodules
.simdec2
= simdec2
# pain in the neck
136 def prepare_for_test(self
, test
):
141 def run_test(self
, instructions
, gen
, insncode
):
142 """run_sim_state - runs an ISACaller simulation
145 dut
, test
, simdec2
= self
.dut
, self
.test
, self
.simdec2
148 # set up the Simulator (which must track TestIssuer exactly)
149 sim
= ISA(simdec2
, test
.regs
, test
.sprs
, test
.cr
, test
.mem
,
151 initial_insns
=gen
, respect_pc
=True,
152 disassembly
=insncode
,
154 initial_svstate
=test
.svstate
)
156 # run the loop of the instructions on the current test
157 index
= sim
.pc
.CIA
.value
//4
158 while index
< len(instructions
):
159 ins
, code
= instructions
[index
]
161 print("sim instr: 0x{:X}".format(ins
& 0xffffffff))
164 # set up simulated instruction (in simdec2)
166 yield from sim
.setup_one()
167 except KeyError: # instruction not in imem: stop
171 # call simulated operation
173 yield from sim
.execute_one()
175 index
= sim
.pc
.CIA
.value
//4
177 # get sim register and memory TestState, add to list
178 state
= yield from TestState("sim", sim
, dut
, code
)
179 sim_states
.append(state
)
184 class HDLRunner(StateRunner
):
185 def __init__(self
, dut
, m
, pspec
):
186 super().__init
__("hdl", HDLRunner
)
189 self
.pc_i
= Signal(32)
190 self
.svstate_i
= Signal(64)
192 #hard_reset = Signal(reset_less=True)
193 self
.issuer
= TestIssuerInternal(pspec
)
194 # use DMI RESET command instead, this does actually work though
195 #issuer = ResetInserter({'coresync': hard_reset,
196 # 'sync': hard_reset})(issuer)
197 m
.submodules
.issuer
= self
.issuer
198 self
.dmi
= self
.issuer
.dbg
.dmi
201 comb
+= self
.issuer
.pc_i
.data
.eq(self
.pc_i
)
202 comb
+= self
.issuer
.svstate_i
.data
.eq(self
.svstate_i
)
204 # run core clock at same rate as test clock
205 intclk
= ClockSignal("coresync")
206 comb
+= intclk
.eq(ClockSignal())
208 def prepare_for_test(self
, test
):
211 # set up bigendian (TODO: don't do this, use MSR)
212 yield self
.issuer
.core_bigendian_i
.eq(bigendian
)
220 def setup_during_test(self
):
221 yield from set_dmi(self
.dmi
, DBGCore
.CTRL
, 1<<DBGCtrl
.STOP
)
224 def run_test(self
, instructions
):
225 """run_hdl_state - runs a TestIssuer nmigen HDL simulation
228 imem
= self
.issuer
.imem
._get
_memory
()
229 core
= self
.issuer
.core
230 dmi
= self
.issuer
.dbg
.dmi
231 pdecode2
= self
.issuer
.pdecode2
235 # establish the TestIssuer context (mem, regs etc)
237 pc
= 0 # start address
238 counter
= 0 # test to pause/start
240 yield from setup_i_memory(imem
, pc
, instructions
)
241 #yield from setup_tst_memory(l0, self.test.mem)
242 yield from setup_regs(pdecode2
, core
, self
.test
)
245 yield self
.pc_i
.eq(pc
)
246 yield self
.issuer
.pc_i
.ok
.eq(1)
248 # copy initial SVSTATE
249 initial_svstate
= copy(self
.test
.svstate
)
250 if isinstance(initial_svstate
, int):
251 initial_svstate
= SVP64State(initial_svstate
)
252 yield self
.svstate_i
.eq(initial_svstate
.value
)
253 yield self
.issuer
.svstate_i
.ok
.eq(1)
256 print("instructions", instructions
)
258 # run the loop of the instructions on the current test
259 index
= (yield self
.issuer
.cur_state
.pc
) // 4
260 while index
< len(instructions
):
261 ins
, code
= instructions
[index
]
263 print("hdl instr: 0x{:X}".format(ins
& 0xffffffff))
269 yield from set_dmi(dmi
, DBGCore
.CTRL
,
271 yield self
.issuer
.pc_i
.ok
.eq(0) # no change PC after this
272 yield self
.issuer
.svstate_i
.ok
.eq(0) # ditto
276 counter
= counter
+ 1
278 # wait until executed
279 while not (yield self
.issuer
.insn_done
):
284 index
= (yield self
.issuer
.cur_state
.pc
) // 4
286 terminated
= yield self
.issuer
.dbg
.terminated_o
287 print("terminated", terminated
)
289 if index
< len(instructions
):
290 # Get HDL mem and state
291 state
= yield from TestState("hdl", core
, self
.dut
,
293 hdl_states
.append(state
)
295 if index
>= len(instructions
):
296 print ("index over, send dmi stop")
298 yield from set_dmi(dmi
, DBGCore
.CTRL
,
303 terminated
= yield self
.issuer
.dbg
.terminated_o
304 print("terminated(2)", terminated
)
311 yield from set_dmi(self
.dmi
, DBGCore
.CTRL
, 1<<DBGCtrl
.STOP
)
315 # TODO, here is where the static (expected) results
316 # can be checked: register check (TODO, memory check)
317 # see https://bugs.libre-soc.org/show_bug.cgi?id=686#c51
318 # yield from check_regs(self, sim, core, test, code,
319 # >>>expected_data<<<)
322 cr
= yield from get_dmi(self
.dmi
, DBGCore
.CR
)
323 print("after test %s cr value %x" % (self
.test
.name
, cr
))
326 xer
= yield from get_dmi(self
.dmi
, DBGCore
.XER
)
327 print("after test %s XER value %x" % (self
.test
.name
, xer
))
329 # test of dmi reg get
330 for int_reg
in range(32):
331 yield from set_dmi(self
.dmi
, DBGCore
.GSPR_IDX
, int_reg
)
332 value
= yield from get_dmi(self
.dmi
, DBGCore
.GSPR_DATA
)
334 print("after test %s reg %2d value %x" %
335 (self
.test
.name
, int_reg
, value
))
338 yield from set_dmi(self
.dmi
, DBGCore
.CTRL
, 1<<DBGCtrl
.RESET
)
342 class TestRunner(FHDLTestCase
):
343 def __init__(self
, tst_data
, microwatt_mmu
=False, rom
=None,
344 svp64
=True, run_hdl
=True, run_sim
=True):
345 super().__init
__("run_all")
346 self
.test_data
= tst_data
347 self
.microwatt_mmu
= microwatt_mmu
350 self
.run_hdl
= run_hdl
351 self
.run_sim
= run_sim
356 if self
.microwatt_mmu
:
357 ldst_ifacetype
= 'test_mmu_cache_wb'
359 ldst_ifacetype
= 'test_bare_wb'
360 imem_ifacetype
= 'test_bare_wb'
362 pspec
= TestMemPspec(ldst_ifacetype
=ldst_ifacetype
,
363 imem_ifacetype
=imem_ifacetype
,
374 mmu
=self
.microwatt_mmu
,
377 ###### SETUP PHASE #######
378 # StateRunner.setup_for_test()
380 # TODO https://bugs.libre-soc.org/show_bug.cgi?id=686#c73
382 hdlrun
= HDLRunner(self
, m
, pspec
)
385 simrun
= SimRunner(self
, m
, pspec
)
387 # nmigen Simulation - everything runs around this, so it
388 # still has to be created.
394 ###### PREPARATION PHASE AT START OF RUNNING #######
395 # StateRunner.setup_during_test()
396 # TODO https://bugs.libre-soc.org/show_bug.cgi?id=686#c73
397 # but "normalise" the APIs, make openpower-isa StateRunner
398 # dummy "yield" functions so if they're not provided at least
399 # there is a fallback which can be "yielded".
402 yield from simrun
.setup_during_test() # TODO, some arguments?
405 yield from hdlrun
.setup_during_test()
407 # get each test, completely reset the core, and run it
409 for test
in self
.test_data
:
411 with self
.subTest(test
.name
):
413 ###### PREPARATION PHASE AT START OF TEST #######
414 # StateRunner.prepare_for_test()
415 # TODO https://bugs.libre-soc.org/show_bug.cgi?id=686#c73
418 yield from simrun
.prepare_for_test(test
)
421 yield from hdlrun
.prepare_for_test(test
)
424 program
= test
.program
425 print("regs", test
.regs
)
426 print("sprs", test
.sprs
)
428 print("mem", test
.mem
)
429 print("msr", test
.msr
)
430 print("assem", program
.assembly
)
431 gen
= list(program
.generate_instructions())
432 insncode
= program
.assembly
.splitlines()
433 instructions
= list(zip(gen
, insncode
))
435 ###### RUNNING OF EACH TEST #######
436 # StateRunner.step_test()
438 # Run two tests (TODO, move these to functions)
439 # * first the Simulator, collate a batch of results
440 # * then the HDL, likewise
441 # (actually, the other way round because running
442 # Simulator somehow modifies the test state!)
443 # * finally, compare all the results
445 # TODO https://bugs.libre-soc.org/show_bug.cgi?id=686#c73
451 hdl_states
= yield from hdlrun
.run_test(instructions
)
458 sim_states
= yield from simrun
.run_test(
462 ###### COMPARING THE TESTS #######
468 # TODO: here just grab one entry from list_of_sim_runners
469 # (doesn't matter which one, honestly)
470 # TODO https://bugs.libre-soc.org/show_bug.cgi?id=686#c73
473 last_sim
= copy(sim_states
[-1])
475 last_sim
= copy(hdl_states
[-1])
477 last_sim
= None # err what are you doing??
479 if self
.run_hdl
and self
.run_sim
:
480 for simstate
, hdlstate
in zip(sim_states
, hdl_states
):
481 simstate
.compare(hdlstate
) # register check
482 simstate
.compare_mem(hdlstate
) # memory check
486 for state
in hdl_states
:
491 for state
in sim_states
:
494 # compare against expected results
495 if test
.expected
is not None:
496 # have to put these in manually
497 test
.expected
.to_test
= test
.expected
498 test
.expected
.dut
= self
499 test
.expected
.state_type
= "expected"
500 test
.expected
.code
= 0
501 # do actual comparison, against last item
502 last_sim
.compare(test
.expected
)
504 if self
.run_hdl
and self
.run_sim
:
505 self
.assertTrue(len(hdl_states
) == len(sim_states
),
506 "number of instructions run not the same")
508 ###### END OF A TEST #######
509 # StateRunner.end_test()
510 # TODO https://bugs.libre-soc.org/show_bug.cgi?id=686#c73
513 yield from simrun
.end_test() # TODO, some arguments?
516 yield from hdlrun
.end_test()
518 ###### END OF EVERYTHING (but none needs doing, still call fn) ####
519 # StateRunner.cleanup()
520 # TODO https://bugs.libre-soc.org/show_bug.cgi?id=686#c73
523 yield from simrun
.cleanup() # TODO, some arguments?
526 yield from hdlrun
.cleanup()
529 'dec': {'base': 'dec'},
530 'bin': {'base': 'bin'},
531 'closed': {'closed': True}
536 ('state machines', 'closed', [
537 'fetch_pc_i_valid', 'fetch_pc_o_ready',
539 'fetch_insn_o_valid', 'fetch_insn_i_ready',
540 'pred_insn_i_valid', 'pred_insn_o_ready',
541 'fetch_predicate_state',
542 'pred_mask_o_valid', 'pred_mask_i_ready',
544 'exec_insn_i_valid', 'exec_insn_o_ready',
546 'exec_pc_o_valid', 'exec_pc_i_ready',
547 'insn_done', 'core_stop_o', 'pc_i_ok', 'pc_changed',
548 'is_last', 'dec2.no_out_vec']),
549 {'comment': 'fetch and decode'},
551 'cia[63:0]', 'nia[63:0]', 'pc[63:0]',
552 'cur_pc[63:0]', 'core_core_cia[63:0]']),
554 'raw_opcode_in[31:0]', 'insn_type', 'dec2.dec2_exc_happened',
555 ('svp64 decoding', 'closed', [
556 'svp64_rm[23:0]', ('dec2.extra[8:0]', 'bin'),
557 'dec2.sv_rm_dec.mode', 'dec2.sv_rm_dec.predmode',
558 'dec2.sv_rm_dec.ptype_in',
559 'dec2.sv_rm_dec.dstpred[2:0]', 'dec2.sv_rm_dec.srcpred[2:0]',
560 'dstmask[63:0]', 'srcmask[63:0]',
561 'dregread[4:0]', 'dinvert',
562 'sregread[4:0]', 'sinvert',
563 'core.int.pred__addr[4:0]', 'core.int.pred__data_o[63:0]',
564 'core.int.pred__ren']),
565 ('register augmentation', 'dec', 'closed', [
566 {'comment': 'v3.0b registers'},
567 'dec2.dec_o.RT[4:0]',
568 'dec2.dec_a.RA[4:0]',
569 'dec2.dec_b.RB[4:0]',
571 'dec2.o_svdec.reg_in[4:0]',
572 ('dec2.o_svdec.spec[2:0]', 'bin'),
573 'dec2.o_svdec.reg_out[6:0]']),
575 'dec2.in1_svdec.reg_in[4:0]',
576 ('dec2.in1_svdec.spec[2:0]', 'bin'),
577 'dec2.in1_svdec.reg_out[6:0]']),
579 'dec2.in2_svdec.reg_in[4:0]',
580 ('dec2.in2_svdec.spec[2:0]', 'bin'),
581 'dec2.in2_svdec.reg_out[6:0]']),
582 {'comment': 'SVP64 registers'},
583 'dec2.rego[6:0]', 'dec2.reg1[6:0]', 'dec2.reg2[6:0]'
585 {'comment': 'svp64 context'},
586 'core_core_vl[6:0]', 'core_core_maxvl[6:0]',
587 'core_core_srcstep[6:0]', 'next_srcstep[6:0]',
588 'core_core_dststep[6:0]',
589 {'comment': 'issue and execute'},
590 'core.core_core_insn_type',
592 'core_rego[6:0]', 'core_reg1[6:0]', 'core_reg2[6:0]']),
595 'dbg.dmi_req_i', 'dbg.dmi_ack_o',
596 {'comment': 'instruction memory'},
597 'imem.sram.rdport.memory(0)[63:0]',
598 {'comment': 'registers'},
599 # match with soc.regfile.regfiles.IntRegs port names
600 'core.int.rp_src1.memory(0)[63:0]',
601 'core.int.rp_src1.memory(1)[63:0]',
602 'core.int.rp_src1.memory(2)[63:0]',
603 'core.int.rp_src1.memory(3)[63:0]',
604 'core.int.rp_src1.memory(4)[63:0]',
605 'core.int.rp_src1.memory(5)[63:0]',
606 'core.int.rp_src1.memory(6)[63:0]',
607 'core.int.rp_src1.memory(7)[63:0]',
608 'core.int.rp_src1.memory(9)[63:0]',
609 'core.int.rp_src1.memory(10)[63:0]',
610 'core.int.rp_src1.memory(13)[63:0]'
613 # PortInterface module path varies depending on MMU option
614 if self
.microwatt_mmu
:
615 pi_module
= 'core.ldst0'
617 pi_module
= 'core.fus.ldst0'
619 traces
+= [('ld/st port interface', {'submodule': pi_module
}, [
621 'ldst_port0_is_ld_i',
622 'ldst_port0_is_st_i',
624 'ldst_port0_addr_i[47:0]',
625 'ldst_port0_addr_i_ok',
626 'ldst_port0_addr_ok_o',
627 'ldst_port0_exc_happened',
628 'ldst_port0_st_data_i[63:0]',
629 'ldst_port0_st_data_i_ok',
630 'ldst_port0_ld_data_o[63:0]',
631 'ldst_port0_ld_data_o_ok',
636 if self
.microwatt_mmu
:
638 {'comment': 'microwatt_mmu'},
639 'core.fus.mmu0.alu_mmu0.illegal',
640 'core.fus.mmu0.alu_mmu0.debug0[3:0]',
641 'core.fus.mmu0.alu_mmu0.mmu.state',
642 'core.fus.mmu0.alu_mmu0.mmu.pid[31:0]',
643 'core.fus.mmu0.alu_mmu0.mmu.prtbl[63:0]',
644 {'comment': 'wishbone_memory'},
645 'core.fus.mmu0.alu_mmu0.dcache.stb',
646 'core.fus.mmu0.alu_mmu0.dcache.cyc',
647 'core.fus.mmu0.alu_mmu0.dcache.we',
648 'core.fus.mmu0.alu_mmu0.dcache.ack',
649 'core.fus.mmu0.alu_mmu0.dcache.stall,'
652 write_gtkw("issuer_simulator.gtkw",
653 "issuer_simulator.vcd",
654 traces
, styles
, module
='top.issuer')
656 # add run of instructions
657 sim
.add_sync_process(process
)
659 # optionally, if a wishbone-based ROM is passed in, run that as an
660 # extra emulated process
661 if self
.rom
is not None:
662 dcache
= core
.fus
.fus
["mmu0"].alu
.dcache
663 default_mem
= self
.rom
664 sim
.add_sync_process(wrap(wb_get(dcache
, default_mem
, "DCACHE")))
666 with sim
.write_vcd("issuer_simulator.vcd"):