src/soc/simple/test/test_runner.py

   1 """TestRunner class, runs TestIssuer instructions
   2
   3 related bugs:
   4
   5  * https://bugs.libre-soc.org/show_bug.cgi?id=363
   6 """
   7 from nmigen import Module, Signal, Cat, ClockSignal
   8
   9 # NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell
  10 # Also, check out the cxxsim nmigen branch, and latest yosys from git
  11 from nmutil.sim_tmp_alternative import Simulator, Settle
  12
  13 from nmutil.formaltest import FHDLTestCase
  14 from nmutil.gtkw import write_gtkw
  15 from nmigen.cli import rtlil
  16 from soc.decoder.isa.caller import special_sprs, SVP64State
  17 from soc.decoder.isa.all import ISA
  18 from soc.config.endian import bigendian
  19
  20 from soc.decoder.power_decoder import create_pdecode
  21 from soc.decoder.power_decoder2 import PowerDecode2
  22 from soc.regfile.regfiles import StateRegs
  23
  24 from soc.simple.issuer import TestIssuerInternal
  25
  26 from soc.config.test.test_loadstore import TestMemPspec
  27 from soc.simple.test.test_core import (setup_regs, check_regs,
  28                                        wait_for_busy_clear,
  29                                        wait_for_busy_hi)
  30 from soc.fu.compunits.test.test_compunit import (setup_test_memory,
  31                                                  check_sim_memory)
  32 from soc.debug.dmi import DBGCore, DBGCtrl, DBGStat
  33
  34
  35 def setup_i_memory(imem, startaddr, instructions):
  36     mem = imem
  37     print("insn before, init mem", mem.depth, mem.width, mem,
  38           len(instructions))
  39     for i in range(mem.depth):
  40         yield mem._array[i].eq(0)
  41     yield Settle()
  42     startaddr //= 4  # instructions are 32-bit
  43     if mem.width == 32:
  44         mask = ((1 << 32)-1)
  45         for ins in instructions:
  46             if isinstance(ins, tuple):
  47                 insn, code = ins
  48             else:
  49                 insn, code = ins, ''
  50             insn = insn & 0xffffffff
  51             yield mem._array[startaddr].eq(insn)
  52             yield Settle()
  53             if insn != 0:
  54                 print("instr: %06x 0x%x %s" % (4*startaddr, insn, code))
  55             startaddr += 1
  56             startaddr = startaddr & mask
  57         return
  58
  59     # 64 bit
  60     mask = ((1 << 64)-1)
  61     for ins in instructions:
  62         if isinstance(ins, tuple):
  63             insn, code = ins
  64         else:
  65             insn, code = ins, ''
  66         insn = insn & 0xffffffff
  67         msbs = (startaddr >> 1) & mask
  68         val = yield mem._array[msbs]
  69         if insn != 0:
  70             print("before set", hex(4*startaddr),
  71                   hex(msbs), hex(val), hex(insn))
  72         lsb = 1 if (startaddr & 1) else 0
  73         val = (val | (insn << (lsb*32)))
  74         val = val & mask
  75         yield mem._array[msbs].eq(val)
  76         yield Settle()
  77         if insn != 0:
  78             print("after  set", hex(4*startaddr), hex(msbs), hex(val))
  79             print("instr: %06x 0x%x %s %08x" % (4*startaddr, insn, code, val))
  80         startaddr += 1
  81         startaddr = startaddr & mask
  82
  83
  84 def set_dmi(dmi, addr, data):
  85     yield dmi.req_i.eq(1)
  86     yield dmi.addr_i.eq(addr)
  87     yield dmi.din.eq(data)
  88     yield dmi.we_i.eq(1)
  89     while True:
  90         ack = yield dmi.ack_o
  91         if ack:
  92             break
  93         yield
  94     yield
  95     yield dmi.req_i.eq(0)
  96     yield dmi.addr_i.eq(0)
  97     yield dmi.din.eq(0)
  98     yield dmi.we_i.eq(0)
  99     yield
 100
 101
 102 def get_dmi(dmi, addr):
 103     yield dmi.req_i.eq(1)
 104     yield dmi.addr_i.eq(addr)
 105     yield dmi.din.eq(0)
 106     yield dmi.we_i.eq(0)
 107     while True:
 108         ack = yield dmi.ack_o
 109         if ack:
 110             break
 111         yield
 112     yield  # wait one
 113     data = yield dmi.dout  # get data after ack valid for 1 cycle
 114     yield dmi.req_i.eq(0)
 115     yield dmi.addr_i.eq(0)
 116     yield dmi.we_i.eq(0)
 117     yield
 118     return data
 119
 120
 121 class TestRunner(FHDLTestCase):
 122     def __init__(self, tst_data, microwatt_mmu=False):
 123         super().__init__("run_all")
 124         self.test_data = tst_data
 125         self.microwatt_mmu = microwatt_mmu
 126
 127     def run_all(self):
 128         m = Module()
 129         comb = m.d.comb
 130         pc_i = Signal(32)
 131
 132         pspec = TestMemPspec(ldst_ifacetype='test_bare_wb',
 133                              imem_ifacetype='test_bare_wb',
 134                              addr_wid=48,
 135                              mask_wid=8,
 136                              imem_reg_wid=64,
 137                              # wb_data_width=32,
 138                              use_pll=False,
 139                              nocore=False,
 140                              xics=False,
 141                              gpio=False,
 142                              mmu=self.microwatt_mmu,
 143                              reg_wid=64)
 144         m.submodules.issuer = issuer = TestIssuerInternal(pspec)
 145         imem = issuer.imem._get_memory()
 146         core = issuer.core
 147         dmi = issuer.dbg.dmi
 148         pdecode2 = issuer.pdecode2
 149         l0 = core.l0
 150
 151         # copy of the decoder for simulator
 152         simdec = create_pdecode()
 153         simdec2 = PowerDecode2(simdec)
 154         m.submodules.simdec2 = simdec2  # pain in the neck
 155
 156         # run core clock at same rate as test clock
 157         intclk = ClockSignal("coresync")
 158         comb += intclk.eq(ClockSignal())
 159
 160         comb += issuer.pc_i.data.eq(pc_i)
 161
 162         # nmigen Simulation
 163         sim = Simulator(m)
 164         sim.add_clock(1e-6)
 165
 166         def process():
 167
 168             # start in stopped
 169             yield from set_dmi(dmi, DBGCore.CTRL, 1<<DBGCtrl.STOP)
 170             yield
 171             yield
 172
 173             # get each test, completely reset the core, and run it
 174
 175             for test in self.test_data:
 176
 177                 # pull a reset
 178                 # yield from set_dmi(dmi, DBGCore.CTRL, 1<<DBGCtrl.RESET)
 179
 180                 # set up bigendian (TODO: don't do this, use MSR)
 181                 yield issuer.core_bigendian_i.eq(bigendian)
 182                 yield Settle()
 183
 184                 yield
 185                 yield
 186                 yield
 187                 yield
 188
 189                 print(test.name)
 190                 program = test.program
 191                 self.subTest(test.name)
 192                 print("regs", test.regs)
 193                 print("sprs", test.sprs)
 194                 print("cr", test.cr)
 195                 print("mem", test.mem)
 196                 print("msr", test.msr)
 197                 print("assem", program.assembly)
 198                 gen = list(program.generate_instructions())
 199                 insncode = program.assembly.splitlines()
 200                 instructions = list(zip(gen, insncode))
 201
 202                 # set up the Simulator (which must track TestIssuer exactly)
 203                 sim = ISA(simdec2, test.regs, test.sprs, test.cr, test.mem,
 204                           test.msr,
 205                           initial_insns=gen, respect_pc=True,
 206                           disassembly=insncode,
 207                           bigendian=bigendian,
 208                           initial_svstate=test.svstate)
 209
 210                 # establish the TestIssuer context (mem, regs etc)
 211
 212                 pc = 0  # start address
 213                 counter = 0  # test to pause/start
 214
 215                 yield from setup_i_memory(imem, pc, instructions)
 216                 yield from setup_test_memory(l0, sim)
 217                 yield from setup_regs(pdecode2, core, test)
 218                 # TODO, setup svstate here in core.regs.state regfile
 219                 # https://bugs.libre-soc.org/show_bug.cgi?id=583#c35
 220                 # setup of SVSTATE
 221                 initial_svstate = test.svstate
 222                 if isinstance(initial_svstate, int):
 223                     initial_svstate = SVP64State(initial_svstate)
 224                 svstate_reg = core.regs.state.regs[StateRegs.SVSTATE].reg
 225                 yield svstate_reg.eq(initial_svstate.spr.value)
 226
 227                 yield pc_i.eq(pc)
 228                 yield issuer.pc_i.ok.eq(1)
 229                 yield
 230
 231                 print("instructions", instructions)
 232
 233                 # run the loop of the instructions on the current test
 234                 index = sim.pc.CIA.value//4
 235                 while index < len(instructions):
 236                     ins, code = instructions[index]
 237
 238                     print("instruction: 0x{:X}".format(ins & 0xffffffff))
 239                     print(index, code)
 240
 241                     if counter == 0:
 242                         # start the core
 243                         yield
 244                         yield from set_dmi(dmi, DBGCore.CTRL, 1<<DBGCtrl.START)
 245                         yield issuer.pc_i.ok.eq(0)  # no change PC after this
 246                         yield
 247                         yield
 248
 249                     counter = counter + 1
 250
 251                     # wait until executed
 252                     yield from wait_for_busy_hi(core)
 253                     yield from wait_for_busy_clear(core)
 254
 255                     # set up simulated instruction (in simdec2)
 256                     try:
 257                         yield from sim.setup_one()
 258                     except KeyError:  # indicates instruction not in imem: stop
 259                         break
 260                     yield Settle()
 261
 262                     # call simulated operation
 263                     print("sim", code)
 264                     yield from sim.execute_one()
 265                     yield Settle()
 266                     index = sim.pc.CIA.value//4
 267
 268                     terminated = yield issuer.dbg.terminated_o
 269                     print("terminated", terminated)
 270
 271                     if index >= len(instructions):
 272                         print ("index over, send dmi stop")
 273                         # stop at end
 274                         yield from set_dmi(dmi, DBGCore.CTRL, 1<<DBGCtrl.STOP)
 275                         yield
 276                         yield
 277
 278                     # wait one cycle for registers to settle
 279                     yield
 280
 281                     # register check
 282                     yield from check_regs(self, sim, core, test, code)
 283
 284                     # Memory check
 285                     yield from check_sim_memory(self, l0, sim, code)
 286
 287                     terminated = yield issuer.dbg.terminated_o
 288                     print("terminated(2)", terminated)
 289                     if terminated:
 290                         break
 291
 292                 # stop at end
 293                 yield from set_dmi(dmi, DBGCore.CTRL, 1<<DBGCtrl.STOP)
 294                 yield
 295                 yield
 296
 297                 # get CR
 298                 cr = yield from get_dmi(dmi, DBGCore.CR)
 299                 print("after test %s cr value %x" % (test.name, cr))
 300
 301                 # get XER
 302                 xer = yield from get_dmi(dmi, DBGCore.XER)
 303                 print("after test %s XER value %x" % (test.name, xer))
 304
 305                 # test of dmi reg get
 306                 for int_reg in range(32):
 307                     yield from set_dmi(dmi, DBGCore.GSPR_IDX, int_reg)
 308                     value = yield from get_dmi(dmi, DBGCore.GSPR_DATA)
 309
 310                     print("after test %s reg %2d value %x" %
 311                           (test.name, int_reg, value))
 312
 313         styles = {
 314             'dec': {'base': 'dec'},
 315             'bin': {'base': 'bin'}
 316         }
 317
 318         traces = [
 319             'clk',
 320             {'comment': 'state machines'},
 321             'fetch_pc_valid_i', 'fetch_pc_ready_o', 'fetch_fsm_state',
 322             'fetch_insn_valid_o', 'fetch_insn_ready_i', 'fsm_state',
 323             {'comment': 'fetch and decode'},
 324             'cia[63:0]', 'nia[63:0]', 'pc[63:0]', 'raw_insn_i[31:0]',
 325             'raw_opcode_in[31:0]', 'insn_type',
 326             {'comment': 'svp64 decoding'},
 327             'svp64_rm[23:0]',
 328             ('dec2.extra[8:0]', 'bin'),
 329             ('register augmentation', 'dec', [
 330                 {'comment': 'v3.0b registers'},
 331                 'dec2.dec_o.RT[4:0]',
 332                 'dec2.dec_a.RA[4:0]',
 333                 'dec2.dec_b.RB[4:0]',
 334                 ('Rdest', [
 335                     'dec2.o_svdec.reg_in[4:0]',
 336                     ('dec2.o_svdec.spec[2:0]', 'bin'),
 337                     'dec2.o_svdec.reg_out[6:0]']),
 338                 ('Rsrc1', [
 339                     'dec2.in1_svdec.reg_in[4:0]',
 340                     ('dec2.in1_svdec.spec[2:0]', 'bin'),
 341                     'dec2.in1_svdec.reg_out[6:0]']),
 342                 ('Rsrc1', [
 343                     'dec2.in2_svdec.reg_in[4:0]',
 344                     ('dec2.in2_svdec.spec[2:0]', 'bin'),
 345                     'dec2.in2_svdec.reg_out[6:0]']),
 346                 {'comment': 'SVP64 registers'},
 347                 'dec2.rego[6:0]', 'dec2.reg1[6:0]', 'dec2.reg2[6:0]'
 348             ]),
 349             {'comment': 'svp64 context'},
 350             'core_core_vl[6:0]', 'core_core_maxvl[6:0]',
 351             'core_core_srcstep[6:0]', 'core_core_dststep[6:0]',
 352             {'comment': 'issue and execute'},
 353             'core.core_core_insn_type',
 354             (None, 'dec', [
 355                 'core_rego[6:0]', 'core_reg1[6:0]', 'core_reg2[6:0]']),
 356             'issue_i', 'busy_o',
 357             {'comment': 'dmi'},
 358             'dbg.dmi_req_i', 'dbg.dmi_ack_o',
 359             {'comment': 'instruction memory'},
 360             'imem.sram.rdport.memory(0)[63:0]',
 361             {'comment': 'registers'},
 362             'core.int.rp_src1.memory(0)[63:0]',
 363             'core.int.rp_src1.memory(1)[63:0]',
 364             'core.int.rp_src1.memory(2)[63:0]',
 365             'core.int.rp_src1.memory(3)[63:0]',
 366             'core.int.rp_src1.memory(4)[63:0]',
 367             'core.int.rp_src1.memory(5)[63:0]',
 368             'core.int.rp_src1.memory(6)[63:0]',
 369             'core.int.rp_src1.memory(7)[63:0]',
 370             'core.int.rp_src1.memory(9)[63:0]',
 371             'core.int.rp_src1.memory(10)[63:0]',
 372             'core.int.rp_src1.memory(13)[63:0]',
 373         ]
 374
 375         if self.microwatt_mmu:
 376             traces += [
 377                 {'comment': 'microwatt_mmu'},
 378                 'core.fus.mmu0.alu_mmu0.illegal',
 379                 'core.fus.mmu0.alu_mmu0.debug0[3:0]',
 380                 'core.fus.mmu0.alu_mmu0.mmu.state',
 381                 'core.fus.mmu0.alu_mmu0.mmu.pid[31:0]',
 382                 'core.fus.mmu0.alu_mmu0.mmu.prtbl[63:0]',
 383                 {'comment': 'wishbone_memory'},
 384                 'core.fus.mmu0.alu_mmu0.dcache.stb',
 385                 'core.fus.mmu0.alu_mmu0.dcache.cyc',
 386                 'core.fus.mmu0.alu_mmu0.dcache.we',
 387                 'core.fus.mmu0.alu_mmu0.dcache.ack',
 388                 'core.fus.mmu0.alu_mmu0.dcache.stall,'
 389             ]
 390
 391         write_gtkw("issuer_simulator.gtkw",
 392                    "issuer_simulator.vcd",
 393                    traces, styles, module='top.issuer')
 394
 395         sim.add_sync_process(process)
 396         with sim.write_vcd("issuer_simulator.vcd"):
 397             sim.run()