1 """TestRunner class, runs TestIssuer instructions
5 * https://bugs.libre-soc.org/show_bug.cgi?id=363
7 from nmigen
import Module
, Signal
, Cat
, ClockSignal
9 # NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell
10 # Also, check out the cxxsim nmigen branch, and latest yosys from git
11 from nmutil
.sim_tmp_alternative
import Simulator
, Settle
13 from nmutil
.formaltest
import FHDLTestCase
14 from nmutil
.gtkw
import write_gtkw
15 from nmigen
.cli
import rtlil
16 from openpower
.decoder
.isa
.caller
import special_sprs
, SVP64State
17 from openpower
.decoder
.isa
.all
import ISA
18 from openpower
.endian
import bigendian
20 from openpower
.decoder
.power_decoder
import create_pdecode
21 from openpower
.decoder
.power_decoder2
import PowerDecode2
22 from soc
.regfile
.regfiles
import StateRegs
24 from soc
.simple
.issuer
import TestIssuerInternal
26 from soc
.config
.test
.test_loadstore
import TestMemPspec
27 from soc
.simple
.test
.test_core
import (setup_regs
, check_regs
,
30 from soc
.fu
.compunits
.test
.test_compunit
import (setup_test_memory
,
32 from soc
.debug
.dmi
import DBGCore
, DBGCtrl
, DBGStat
33 from nmutil
.util
import wrap
34 from soc
.experiment
.test
.test_mmu_dcache
import wb_get
37 def setup_i_memory(imem
, startaddr
, instructions
):
39 print("insn before, init mem", mem
.depth
, mem
.width
, mem
,
41 for i
in range(mem
.depth
):
42 yield mem
._array
[i
].eq(0)
44 startaddr
//= 4 # instructions are 32-bit
47 for ins
in instructions
:
48 if isinstance(ins
, tuple):
52 insn
= insn
& 0xffffffff
53 yield mem
._array
[startaddr
].eq(insn
)
56 print("instr: %06x 0x%x %s" % (4*startaddr
, insn
, code
))
58 startaddr
= startaddr
& mask
63 for ins
in instructions
:
64 if isinstance(ins
, tuple):
68 insn
= insn
& 0xffffffff
69 msbs
= (startaddr
>> 1) & mask
70 val
= yield mem
._array
[msbs
]
72 print("before set", hex(4*startaddr
),
73 hex(msbs
), hex(val
), hex(insn
))
74 lsb
= 1 if (startaddr
& 1) else 0
75 val
= (val |
(insn
<< (lsb
*32)))
77 yield mem
._array
[msbs
].eq(val
)
80 print("after set", hex(4*startaddr
), hex(msbs
), hex(val
))
81 print("instr: %06x 0x%x %s %08x" % (4*startaddr
, insn
, code
, val
))
83 startaddr
= startaddr
& mask
86 def set_dmi(dmi
, addr
, data
):
88 yield dmi
.addr_i
.eq(addr
)
89 yield dmi
.din
.eq(data
)
98 yield dmi
.addr_i
.eq(0)
104 def get_dmi(dmi
, addr
):
105 yield dmi
.req_i
.eq(1)
106 yield dmi
.addr_i
.eq(addr
)
110 ack
= yield dmi
.ack_o
115 data
= yield dmi
.dout
# get data after ack valid for 1 cycle
116 yield dmi
.req_i
.eq(0)
117 yield dmi
.addr_i
.eq(0)
123 class TestRunner(FHDLTestCase
):
124 def __init__(self
, tst_data
, microwatt_mmu
=False, rom
=None,
126 super().__init
__("run_all")
127 self
.test_data
= tst_data
128 self
.microwatt_mmu
= microwatt_mmu
136 svstate_i
= Signal(32)
138 if self
.microwatt_mmu
:
139 ldst_ifacetype
= 'test_mmu_cache_wb'
141 ldst_ifacetype
= 'test_bare_wb'
142 imem_ifacetype
= 'test_bare_wb'
144 pspec
= TestMemPspec(ldst_ifacetype
=ldst_ifacetype
,
145 imem_ifacetype
=imem_ifacetype
,
156 mmu
=self
.microwatt_mmu
,
158 m
.submodules
.issuer
= issuer
= TestIssuerInternal(pspec
)
159 imem
= issuer
.imem
._get
_memory
()
162 pdecode2
= issuer
.pdecode2
164 regreduce_en
= pspec
.regreduce_en
== True
166 # copy of the decoder for simulator
167 simdec
= create_pdecode()
168 simdec2
= PowerDecode2(simdec
, regreduce_en
=regreduce_en
)
169 m
.submodules
.simdec2
= simdec2
# pain in the neck
171 # run core clock at same rate as test clock
172 intclk
= ClockSignal("coresync")
173 comb
+= intclk
.eq(ClockSignal())
175 comb
+= issuer
.pc_i
.data
.eq(pc_i
)
176 comb
+= issuer
.svstate_i
.data
.eq(svstate_i
)
185 yield from set_dmi(dmi
, DBGCore
.CTRL
, 1<<DBGCtrl
.STOP
)
189 # get each test, completely reset the core, and run it
191 for test
in self
.test_data
:
194 # yield from set_dmi(dmi, DBGCore.CTRL, 1<<DBGCtrl.RESET)
196 # set up bigendian (TODO: don't do this, use MSR)
197 yield issuer
.core_bigendian_i
.eq(bigendian
)
206 program
= test
.program
207 self
.subTest(test
.name
)
208 print("regs", test
.regs
)
209 print("sprs", test
.sprs
)
211 print("mem", test
.mem
)
212 print("msr", test
.msr
)
213 print("assem", program
.assembly
)
214 gen
= list(program
.generate_instructions())
215 insncode
= program
.assembly
.splitlines()
216 instructions
= list(zip(gen
, insncode
))
218 # set up the Simulator (which must track TestIssuer exactly)
219 sim
= ISA(simdec2
, test
.regs
, test
.sprs
, test
.cr
, test
.mem
,
221 initial_insns
=gen
, respect_pc
=True,
222 disassembly
=insncode
,
224 initial_svstate
=test
.svstate
)
226 # establish the TestIssuer context (mem, regs etc)
228 pc
= 0 # start address
229 counter
= 0 # test to pause/start
231 yield from setup_i_memory(imem
, pc
, instructions
)
232 yield from setup_test_memory(l0
, sim
)
233 yield from setup_regs(pdecode2
, core
, test
)
237 yield issuer
.pc_i
.ok
.eq(1)
239 initial_svstate
= test
.svstate
240 if isinstance(initial_svstate
, int):
241 initial_svstate
= SVP64State(initial_svstate
)
242 yield svstate_i
.eq(initial_svstate
.spr
.value
)
243 yield issuer
.svstate_i
.ok
.eq(1)
246 print("instructions", instructions
)
248 # run the loop of the instructions on the current test
249 index
= sim
.pc
.CIA
.value
//4
250 while index
< len(instructions
):
251 ins
, code
= instructions
[index
]
253 print("instruction: 0x{:X}".format(ins
& 0xffffffff))
259 yield from set_dmi(dmi
, DBGCore
.CTRL
, 1<<DBGCtrl
.START
)
260 yield issuer
.pc_i
.ok
.eq(0) # no change PC after this
261 yield issuer
.svstate_i
.ok
.eq(0) # ditto
265 counter
= counter
+ 1
267 # wait until executed
268 while not (yield issuer
.insn_done
):
271 # set up simulated instruction (in simdec2)
273 yield from sim
.setup_one()
274 except KeyError: # indicates instruction not in imem: stop
278 # call simulated operation
280 yield from sim
.execute_one()
282 index
= sim
.pc
.CIA
.value
//4
284 terminated
= yield issuer
.dbg
.terminated_o
285 print("terminated", terminated
)
287 if index
>= len(instructions
):
288 print ("index over, send dmi stop")
290 yield from set_dmi(dmi
, DBGCore
.CTRL
, 1<<DBGCtrl
.STOP
)
295 yield from check_regs(self
, sim
, core
, test
, code
)
298 yield from check_sim_memory(self
, l0
, sim
, code
)
300 terminated
= yield issuer
.dbg
.terminated_o
301 print("terminated(2)", terminated
)
306 yield from set_dmi(dmi
, DBGCore
.CTRL
, 1<<DBGCtrl
.STOP
)
311 cr
= yield from get_dmi(dmi
, DBGCore
.CR
)
312 print("after test %s cr value %x" % (test
.name
, cr
))
315 xer
= yield from get_dmi(dmi
, DBGCore
.XER
)
316 print("after test %s XER value %x" % (test
.name
, xer
))
318 # test of dmi reg get
319 for int_reg
in range(32):
320 yield from set_dmi(dmi
, DBGCore
.GSPR_IDX
, int_reg
)
321 value
= yield from get_dmi(dmi
, DBGCore
.GSPR_DATA
)
323 print("after test %s reg %2d value %x" %
324 (test
.name
, int_reg
, value
))
327 'dec': {'base': 'dec'},
328 'bin': {'base': 'bin'},
329 'closed': {'closed': True}
334 ('state machines', 'closed', [
335 'fetch_pc_valid_i', 'fetch_pc_ready_o',
337 'fetch_insn_valid_o', 'fetch_insn_ready_i',
338 'pred_insn_valid_i', 'pred_insn_ready_o',
339 'fetch_predicate_state',
340 'pred_mask_valid_o', 'pred_mask_ready_i',
342 'exec_insn_valid_i', 'exec_insn_ready_o',
344 'exec_pc_valid_o', 'exec_pc_ready_i',
345 'insn_done', 'core_stop_o', 'pc_i_ok', 'pc_changed',
346 'is_last', 'dec2.no_out_vec']),
347 {'comment': 'fetch and decode'},
349 'cia[63:0]', 'nia[63:0]', 'pc[63:0]',
350 'cur_pc[63:0]', 'core_core_cia[63:0]']),
352 'raw_opcode_in[31:0]', 'insn_type',
353 ('svp64 decoding', 'closed', [
354 'svp64_rm[23:0]', ('dec2.extra[8:0]', 'bin'),
355 'dec2.sv_rm_dec.mode', 'dec2.sv_rm_dec.predmode',
356 'dec2.sv_rm_dec.ptype_in',
357 'dec2.sv_rm_dec.dstpred[2:0]', 'dec2.sv_rm_dec.srcpred[2:0]',
358 'dstmask[63:0]', 'srcmask[63:0]',
359 'dregread[4:0]', 'dinvert',
360 'sregread[4:0]', 'sinvert',
361 'core.int.pred__addr[4:0]', 'core.int.pred__data_o[63:0]',
362 'core.int.pred__ren']),
363 ('register augmentation', 'dec', 'closed', [
364 {'comment': 'v3.0b registers'},
365 'dec2.dec_o.RT[4:0]',
366 'dec2.dec_a.RA[4:0]',
367 'dec2.dec_b.RB[4:0]',
369 'dec2.o_svdec.reg_in[4:0]',
370 ('dec2.o_svdec.spec[2:0]', 'bin'),
371 'dec2.o_svdec.reg_out[6:0]']),
373 'dec2.in1_svdec.reg_in[4:0]',
374 ('dec2.in1_svdec.spec[2:0]', 'bin'),
375 'dec2.in1_svdec.reg_out[6:0]']),
377 'dec2.in2_svdec.reg_in[4:0]',
378 ('dec2.in2_svdec.spec[2:0]', 'bin'),
379 'dec2.in2_svdec.reg_out[6:0]']),
380 {'comment': 'SVP64 registers'},
381 'dec2.rego[6:0]', 'dec2.reg1[6:0]', 'dec2.reg2[6:0]'
383 {'comment': 'svp64 context'},
384 'core_core_vl[6:0]', 'core_core_maxvl[6:0]',
385 'core_core_srcstep[6:0]', 'next_srcstep[6:0]',
386 'core_core_dststep[6:0]',
387 {'comment': 'issue and execute'},
388 'core.core_core_insn_type',
390 'core_rego[6:0]', 'core_reg1[6:0]', 'core_reg2[6:0]']),
393 'dbg.dmi_req_i', 'dbg.dmi_ack_o',
394 {'comment': 'instruction memory'},
395 'imem.sram.rdport.memory(0)[63:0]',
396 {'comment': 'registers'},
397 # match with soc.regfile.regfiles.IntRegs port names
398 'core.int.rp_src1.memory(0)[63:0]',
399 'core.int.rp_src1.memory(1)[63:0]',
400 'core.int.rp_src1.memory(2)[63:0]',
401 'core.int.rp_src1.memory(3)[63:0]',
402 'core.int.rp_src1.memory(4)[63:0]',
403 'core.int.rp_src1.memory(5)[63:0]',
404 'core.int.rp_src1.memory(6)[63:0]',
405 'core.int.rp_src1.memory(7)[63:0]',
406 'core.int.rp_src1.memory(9)[63:0]',
407 'core.int.rp_src1.memory(10)[63:0]',
408 'core.int.rp_src1.memory(13)[63:0]',
411 if self
.microwatt_mmu
:
413 {'comment': 'microwatt_mmu'},
414 'core.fus.mmu0.alu_mmu0.illegal',
415 'core.fus.mmu0.alu_mmu0.debug0[3:0]',
416 'core.fus.mmu0.alu_mmu0.mmu.state',
417 'core.fus.mmu0.alu_mmu0.mmu.pid[31:0]',
418 'core.fus.mmu0.alu_mmu0.mmu.prtbl[63:0]',
419 {'comment': 'wishbone_memory'},
420 'core.fus.mmu0.alu_mmu0.dcache.stb',
421 'core.fus.mmu0.alu_mmu0.dcache.cyc',
422 'core.fus.mmu0.alu_mmu0.dcache.we',
423 'core.fus.mmu0.alu_mmu0.dcache.ack',
424 'core.fus.mmu0.alu_mmu0.dcache.stall,'
427 write_gtkw("issuer_simulator.gtkw",
428 "issuer_simulator.vcd",
429 traces
, styles
, module
='top.issuer')
431 # add run of instructions
432 sim
.add_sync_process(process
)
434 # optionally, if a wishbone-based ROM is passed in, run that as an
435 # extra emulated process
436 if self
.rom
is not None:
437 dcache
= core
.fus
.fus
["mmu0"].alu
.dcache
438 default_mem
= self
.rom
439 sim
.add_sync_process(wrap(wb_get(dcache
, default_mem
, "DCACHE")))
441 with sim
.write_vcd("issuer_simulator.vcd"):