1 from openpower
.decoder
.power_enums
import XER_bits
6 yield from self
.get_intregs()
7 yield from self
.get_crregs()
8 yield from self
.get_xregs()
9 yield from self
.get_pc()
11 def compare(self
, s2
):
12 # Compare int registers
13 for i
, (self
.intregs
, s2
.intregs
) in enumerate(
14 zip(self
.intregs
, s2
.intregs
)):
15 print("asserting...reg", i
, self
.intregs
, s2
.intregs
)
16 print("code, frepr(code)", self
.code
, repr(self
.code
))
17 self
.dut
.assertEqual(self
.intregs
, s2
.intregs
,
18 "int reg %d (%s) not equal (%s) %s. got %x expected %x" %
19 (i
, self
.state_type
, s2
.state_type
, repr(self
.code
),
20 self
.intregs
, s2
.intregs
))
23 for i
, (self
.crregs
, s2
.crregs
) in enumerate(
24 zip(self
.crregs
, s2
.crregs
)):
25 print("asserting...cr", i
, self
.crregs
, s2
.crregs
)
26 self
.dut
.assertEqual(self
.crregs
, s2
.crregs
,
27 "cr reg %d (%s) not equal (%s) %s. got %x expected %x" %
28 (i
, self
.state_type
, s2
.state_type
, repr(self
.code
),
29 self
.crregs
, s2
.crregs
))
32 self
.dut
.assertEqual(self
.so
, s2
.so
, "so mismatch (%s != %s) %s" %
33 (self
.state_type
, s2
.state_type
, repr(self
.code
)))
34 self
.dut
.assertEqual(self
.ov
, s2
.ov
, "ov mismatch (%s != %s) %s" %
35 (self
.state_type
, s2
.state_type
, repr(self
.code
)))
36 self
.dut
.assertEqual(self
.ca
, s2
.ca
, "ca mismatch (%s != %s) %s" %
37 (self
.state_type
, s2
.state_type
, repr(self
.code
)))
40 self
.dut
.assertEqual(self
.pc
, s2
.pc
, "pc mismatch (%s != %s) %s" %
41 (self
.state_type
, s2
.state_type
, repr(self
.code
)))
44 class SimState(State
):
45 def __init__(self
, sim
):
48 def get_intregs(self
):
53 simregval
= self
.sim
.gpr
[i
].asint()
54 self
.intregs
.append(simregval
)
55 print("class sim int regs", list(map(hex, self
.intregs
)))
62 cri
= self
.sim
.crl
[7 - i
].get_range().value
63 self
.crregs
.append(cri
)
64 print("class sim cr regs", list(map(hex, self
.crregs
)))
70 self
.so
= self
.sim
.spr
['XER'][XER_bits
['SO']].value
71 self
.ov
= self
.sim
.spr
['XER'][XER_bits
['OV']].value
72 self
.ov32
= self
.sim
.spr
['XER'][XER_bits
['OV32']].value
73 self
.ca
= self
.sim
.spr
['XER'][XER_bits
['CA']].value
74 self
.ca32
= self
.sim
.spr
['XER'][XER_bits
['CA32']].value
75 self
.ov
= self
.ov |
(self
.ov32
<< 1)
76 self
.ca
= self
.ca |
(self
.ca32
<< 1)
77 self
.xregs
.extend((self
.so
, self
.ov
, self
.ca
))
78 print("class sim xregs", list(map(hex, self
.xregs
)))
84 self
.pc
= self
.sim
.pc
.CIA
.value
85 self
.pcl
.append(self
.pc
)
86 print("class sim pc", hex(self
.pc
))
89 class HDLState(State
):
90 def __init__(self
, core
):
93 def get_intregs(self
):
96 if self
.core
.regs
.int.unary
:
97 rval
= yield self
.core
.regs
.int.regs
[i
].reg
99 rval
= yield self
.core
.regs
.int.memory
._array
[i
]
100 self
.intregs
.append(rval
)
101 print("class hdl int regs", list(map(hex, self
.intregs
)))
103 def get_crregs(self
):
106 rval
= yield self
.core
.regs
.cr
.regs
[i
].reg
107 self
.crregs
.append(rval
)
108 print("class hdl cr regs", list(map(hex, self
.crregs
)))
112 self
.xr
= self
.core
.regs
.xer
113 self
.so
= yield self
.xr
.regs
[self
.xr
.SO
].reg
114 self
.ov
= yield self
.xr
.regs
[self
.xr
.OV
].reg
115 self
.ca
= yield self
.xr
.regs
[self
.xr
.CA
].reg
116 self
.xregs
.extend((self
.so
, self
.ov
, self
.ca
))
117 print("class hdl xregs", list(map(hex, self
.xregs
)))
121 self
.state
= self
.core
.regs
.state
122 self
.pc
= yield self
.state
.r_ports
['cia'].o_data
123 self
.pcl
.append(self
.pc
)
124 print("class hdl pc", hex(self
.pc
))
127 def TestState(state_type
, state_dic
, dut
, code
):
128 state_factory
= {'sim': SimState
, 'hdl': HDLState
}
129 state_class
= state_factory
[state_type
]
130 state
= state_class(state_dic
[state_type
])
132 state
.state_type
= state_type
134 yield from state
.get_state()