1 from nmigen
import Module
, Signal
2 from nmigen
.back
.pysim
import Simulator
, Delay
, Settle
3 from nmutil
.formaltest
import FHDLTestCase
5 from soc
.decoder
.power_decoder
import (create_pdecode
)
6 from soc
.decoder
.power_enums
import (Function
, MicrOp
,
7 In1Sel
, In2Sel
, In3Sel
,
8 OutSel
, RC
, LdstLen
, CryIn
,
9 single_bit_flags
, Form
, SPR
,
10 get_signal_name
, get_csv
)
11 from soc
.decoder
.power_decoder2
import (PowerDecode2
)
12 from soc
.simulator
.program
import Program
13 from soc
.simulator
.qemu
import run_program
14 from soc
.decoder
.isa
.all
import ISA
15 from soc
.fu
.test
.common
import TestCase
16 from soc
.simulator
.test_sim
import DecoderBase
17 from soc
.config
.endian
import bigendian
20 class HelloTestCases(FHDLTestCase
):
23 def __init__(self
, name
="div"):
24 super().__init
__(name
)
27 def test_microwatt_helloworld(self
):
38 "mtspr 9, 12", # mtctr r12
39 "bcctrl 20,0,0", # bctrl
41 self
.run_tst_program(Program(lst
, bigendian
),
42 [1,12], extra_break_addr
=0x1014)
44 def run_tst_program(self
, prog
, initial_regs
=None, initial_sprs
=None,
45 initial_mem
=None, extra_break_addr
=None):
46 initial_regs
= [0] * 32
47 tc
= TestCase(prog
, self
.test_name
, initial_regs
, initial_sprs
, 0,
49 extra_break_addr
=extra_break_addr
)
50 self
.test_data
.append(tc
)
53 class HelloDecoderTestCase(DecoderBase
, HelloTestCases
):
57 if __name__
== "__main__":