add code-fragment from microwatt helloworld
[soc.git] / src / soc / simulator / test_helloworld_sim.py
1 from nmigen import Module, Signal
2 from nmigen.back.pysim import Simulator, Delay, Settle
3 from nmigen.test.utils import FHDLTestCase
4 import unittest
5 from soc.decoder.power_decoder import (create_pdecode)
6 from soc.decoder.power_enums import (Function, InternalOp,
7 In1Sel, In2Sel, In3Sel,
8 OutSel, RC, LdstLen, CryIn,
9 single_bit_flags, Form, SPR,
10 get_signal_name, get_csv)
11 from soc.decoder.power_decoder2 import (PowerDecode2)
12 from soc.simulator.program import Program
13 from soc.simulator.qemu import run_program
14 from soc.decoder.isa.all import ISA
15 from soc.fu.test.common import TestCase
16 from soc.simulator.test_sim import DecoderBase
17
18
19
20 class HelloTestCases(FHDLTestCase):
21 test_data = []
22
23 def __init__(self, name="div"):
24 super().__init__(name)
25 self.test_name = name
26
27 def test_microwatt_helloworld(self):
28 lst = ["addis 1,0,0",
29 "ori 1,1,0",
30 "rldicr 1,1,32,31",
31 "oris 1,1,0",
32 "ori 1,1,7936",
33 "addis 12,0,0",
34 "ori 12,12,0",
35 "rldicr 12,12,32,31",
36 "oris 12,12,0",
37 "ori 12,12,4116",
38 ]
39 self.run_tst_program(Program(lst), [1,12])
40
41 def run_tst_program(self, prog, initial_regs=None, initial_sprs=None,
42 initial_mem=None):
43 initial_regs = [0] * 32
44 tc = TestCase(prog, self.test_name, initial_regs, initial_sprs, 0,
45 initial_mem, 0)
46 self.test_data.append(tc)
47
48
49 class HelloDecoderTestCase(DecoderBase, HelloTestCases):
50 pass
51
52
53 if __name__ == "__main__":
54 unittest.main()