1 from nmigen
import Module
, Signal
2 from nmigen
.back
.pysim
import Simulator
, Delay
, Settle
3 from nmigen
.test
.utils
import FHDLTestCase
5 from soc
.decoder
.power_decoder
import (create_pdecode
)
6 from soc
.decoder
.power_enums
import (Function
, MicrOp
,
7 In1Sel
, In2Sel
, In3Sel
,
8 OutSel
, RC
, LdstLen
, CryIn
,
9 single_bit_flags
, Form
, SPR
,
10 get_signal_name
, get_csv
)
11 from soc
.decoder
.power_decoder2
import (PowerDecode2
)
12 from soc
.simulator
.program
import Program
13 from soc
.simulator
.qemu
import run_program
14 from soc
.decoder
.isa
.all
import ISA
15 from soc
.fu
.test
.common
import TestCase
16 from soc
.config
.endian
import bigendian
19 class AttnTestCase(FHDLTestCase
):
22 def __init__(self
, name
="general"):
23 super().__init
__(name
)
26 def test_0_attn(self
):
27 """simple test of attn. program is 4 long: should halt at 2nd op
29 lst
= ["addi 6, 0, 0x10",
34 with
Program(lst
, bigendian
) as program
:
35 self
.run_tst_program(program
, [1])
37 def run_tst_program(self
, prog
, initial_regs
=None, initial_sprs
=None,
39 initial_regs
= [0] * 32
40 tc
= TestCase(prog
, self
.test_name
, initial_regs
, initial_sprs
, 0,
42 self
.test_data
.append(tc
)
45 class GeneralTestCases(FHDLTestCase
):
48 def __init__(self
, name
="general"):
49 super().__init
__(name
)
52 @unittest.skip("disable")
54 lst
= ["addi 6, 0, 0x10",
59 with
Program(lst
, bigendian
) as program
:
60 self
.run_tst_program(program
, [1])
62 @unittest.skip("disable")
63 def test_example(self
):
64 lst
= ["addi 1, 0, 0x5678",
68 with
Program(lst
, bigendian
) as program
:
69 self
.run_tst_program(program
, [1, 2, 3, 4])
71 @unittest.skip("disable")
73 lst
= ["addi 1, 0, 0x5678",
78 initial_mem
= {0x1230: (0x5432123412345678, 8),
79 0x1238: (0xabcdef0187654321, 8),
81 with
Program(lst
, bigendian
) as program
:
82 self
.run_tst_program(program
,
86 @unittest.skip("disable")
87 def test_ld_rev_ext(self
):
88 lst
= ["addi 1, 0, 0x5678",
93 with
Program(lst
, bigendian
) as program
:
94 self
.run_tst_program(program
, [1, 2, 3])
96 @unittest.skip("disable")
97 def test_st_rev_ext(self
):
98 lst
= ["addi 1, 0, 0x5678",
103 with
Program(lst
, bigendian
) as program
:
104 self
.run_tst_program(program
, [1, 2, 3])
106 @unittest.skip("disable")
107 def test_ldst_extended(self
):
108 lst
= ["addi 1, 0, 0x5678",
113 with
Program(lst
, bigendian
) as program
:
114 self
.run_tst_program(program
, [1, 2, 3])
116 @unittest.skip("disable")
117 def test_0_ldst_widths(self
):
118 lst
= ["addis 1, 0, 0xdead",
128 with
Program(lst
, bigendian
) as program
:
129 self
.run_tst_program(program
, [1, 2, 3, 4, 5])
131 @unittest.skip("disable")
133 lst
= ["addi 1, 0, 0x1234",
136 "subfic 4, 1, 0x1337",
138 with
Program(lst
, bigendian
) as program
:
139 self
.run_tst_program(program
, [1, 2, 3, 4, 5])
141 @unittest.skip("disable")
142 def test_add_with_carry(self
):
143 lst
= ["addi 1, 0, 5",
150 with
Program(lst
, bigendian
) as program
:
151 self
.run_tst_program(program
, [1, 2, 3])
153 @unittest.skip("disable")
154 def test_addis(self
):
155 lst
= ["addi 1, 0, 0x0FFF",
158 with
Program(lst
, bigendian
) as program
:
159 self
.run_tst_program(program
, [1])
161 @unittest.skip("broken")
162 def test_mulli(self
):
163 lst
= ["addi 1, 0, 3",
166 with
Program(lst
, bigendian
) as program
:
167 self
.run_tst_program(program
, [1])
169 @unittest.skip("disable")
170 def test_2_load_store(self
):
171 lst
= ["addi 1, 0, 0x1004",
177 initial_regs
= [0] * 32
178 initial_regs
[1] = 0x1004
179 initial_regs
[2] = 0x1008
180 initial_regs
[3] = 0x00ee
181 initial_mem
= {0x1000: (0x5432123412345678, 8),
182 0x1008: (0xabcdef0187654321, 8),
183 0x1020: (0x1828384822324252, 8),
185 with
Program(lst
, bigendian
) as program
:
186 self
.run_tst_program(program
, [3,4], initial_mem
)
188 @unittest.skip("disable")
189 def test_3_load_store(self
):
190 lst
= ["addi 1, 0, 0x1004",
195 initial_regs
= [0] * 32
196 initial_regs
[1] = 0x1004
197 initial_regs
[2] = 0x1002
198 initial_regs
[3] = 0x15eb
199 initial_mem
= {0x1000: (0x5432123412345678, 8),
200 0x1008: (0xabcdef0187654321, 8),
201 0x1020: (0x1828384822324252, 8),
203 with
Program(lst
, bigendian
) as program
:
204 self
.run_tst_program(program
, [1,2,3,4], initial_mem
)
208 register unsigned long i asm ("r12");
216 lst
= ["addi 9, 0, 0x10", # i = 16
217 "addi 9,9,-1", # i = i - 1
218 "cmpi 0,1,9,12", # compare 9 to value 0, store in CR2
219 "bc 4,0,-8" # branch if CR2 "test was != 0"
221 with
Program(lst
, bigendian
) as program
:
222 self
.run_tst_program(program
, [9], initial_mem
={})
224 def test_30_addis(self
):
225 lst
= [#"addi 0, 0, 5",
228 with
Program(lst
, bigendian
) as program
:
229 self
.run_tst_program(program
, [12])
231 def run_tst_program(self
, prog
, initial_regs
=None, initial_sprs
=None,
233 initial_regs
= [0] * 32
234 tc
= TestCase(prog
, self
.test_name
, initial_regs
, initial_sprs
, 0,
236 self
.test_data
.append(tc
)
241 def run_tst(self
, generator
, initial_mem
=None, initial_pc
=0):
245 gen
= list(generator
.generate_instructions())
246 insn_code
= generator
.assembly
.splitlines()
247 instructions
= list(zip(gen
, insn_code
))
249 pdecode
= create_pdecode()
250 m
.submodules
.pdecode2
= pdecode2
= PowerDecode2(pdecode
)
252 # place program at requested address
253 gen
= (initial_pc
, gen
)
255 simulator
= ISA(pdecode2
, [0] * 32, {}, 0, initial_mem
, 0,
256 initial_insns
=gen
, respect_pc
=True,
257 disassembly
=insn_code
,
258 initial_pc
=initial_pc
,
264 #yield pdecode2.dec.bigendian.eq(bigendian)
269 yield from simulator
.setup_one()
270 except KeyError: # indicates instruction not in imem: stop
273 yield from simulator
.execute_one()
277 sim
.add_process(process
)
278 with sim
.write_vcd("simulator.vcd", "simulator.gtkw",
284 def run_tst_program(self
, prog
, reglist
, initial_mem
=None,
285 extra_break_addr
=None):
287 simulator
= self
.run_tst(prog
, initial_mem
=initial_mem
,
288 initial_pc
=0x20000000)
290 with
run_program(prog
, initial_mem
, extra_break_addr
,
291 bigendian
=bigendian
) as q
:
292 self
.qemu_register_compare(simulator
, q
, reglist
)
293 self
.qemu_mem_compare(simulator
, q
, True)
294 print(simulator
.gpr
.dump())
296 def qemu_mem_compare(self
, sim
, qemu
, check
=True):
297 if False: # disable convenient large interesting debugging memory dump
299 qmemdump
= qemu
.get_mem(addr
, 2048)
300 for i
in range(len(qmemdump
)):
301 s
= hex(int(qmemdump
[i
]))
302 print ("qemu mem %06x %s" % (addr
+i
*8, s
))
303 for k
, v
in sim
.mem
.mem
.items():
304 qmemdump
= qemu
.get_mem(k
*8, 8)
305 s
= hex(int(qmemdump
[0]))[2:]
306 print ("qemu mem %06x %16s" % (k
*8, s
))
307 for k
, v
in sim
.mem
.mem
.items():
308 print ("sim mem %06x %016x" % (k
*8, v
))
311 for k
, v
in sim
.mem
.mem
.items():
312 qmemdump
= qemu
.get_mem(k
*8, 1)
313 self
.assertEqual(int(qmemdump
[0]), v
)
315 def qemu_register_compare(self
, sim
, qemu
, regs
):
316 qpc
, qxer
, qcr
= qemu
.get_pc(), qemu
.get_xer(), qemu
.get_cr()
317 sim_cr
= sim
.cr
.get_range().value
318 sim_pc
= sim
.pc
.CIA
.value
319 sim_xer
= sim
.spr
['XER'].value
320 print("qemu pc", hex(qpc
))
321 print("qemu cr", hex(qcr
))
322 print("qemu xer", bin(qxer
))
323 print("sim nia", hex(sim
.pc
.NIA
.value
))
324 print("sim pc", hex(sim
.pc
.CIA
.value
))
325 print("sim cr", hex(sim_cr
))
326 print("sim xer", hex(sim_xer
))
327 self
.assertEqual(qpc
, sim_pc
)
329 qemu_val
= qemu
.get_register(reg
)
330 sim_val
= sim
.gpr(reg
).value
331 self
.assertEqual(qemu_val
, sim_val
,
332 "expect %x got %x" % (qemu_val
, sim_val
))
333 self
.assertEqual(qcr
, sim_cr
)
336 class DecoderTestCase(DecoderBase
, GeneralTestCases
):
340 if __name__
== "__main__":