1 from nmigen
import Module
, Signal
2 from nmigen
.back
.pysim
import Simulator
, Delay
, Settle
3 from nmigen
.test
.utils
import FHDLTestCase
5 from soc
.decoder
.power_decoder
import (create_pdecode
)
6 from soc
.decoder
.power_enums
import (Function
, InternalOp
,
7 In1Sel
, In2Sel
, In3Sel
,
8 OutSel
, RC
, LdstLen
, CryIn
,
9 single_bit_flags
, Form
, SPR
,
10 get_signal_name
, get_csv
)
11 from soc
.decoder
.power_decoder2
import (PowerDecode2
)
12 from soc
.simulator
.program
import Program
13 from soc
.simulator
.qemu
import run_program
14 from soc
.decoder
.isa
.all
import ISA
18 def __init__(self
, num
):
22 class DecoderTestCase(FHDLTestCase
):
24 def run_tst(self
, generator
, initial_mem
=None):
28 gen
= list(generator
.generate_instructions())
29 insn_code
= generator
.assembly
.splitlines()
30 instructions
= list(zip(gen
, insn_code
))
32 pdecode
= create_pdecode()
33 m
.submodules
.pdecode2
= pdecode2
= PowerDecode2(pdecode
)
35 simulator
= ISA(pdecode2
, [0] * 32, {}, 0, initial_mem
, 0,
36 initial_insns
=gen
, respect_pc
=True,
37 disassembly
=insn_code
)
44 yield from simulator
.setup_one()
45 except KeyError: # indicates instruction not in imem: stop
48 yield from simulator
.execute_one()
52 sim
.add_process(process
)
53 with sim
.write_vcd("simulator.vcd", "simulator.gtkw",
59 @unittest.skip("disable")
61 lst
= ["addi 6, 0, 0x10",
66 with
Program(lst
) as program
:
67 self
.run_tst_program(program
, [1])
69 @unittest.skip("disable")
70 def test_example(self
):
71 lst
= ["addi 1, 0, 0x5678",
75 with
Program(lst
) as program
:
76 self
.run_tst_program(program
, [1, 2, 3, 4])
78 @unittest.skip("disable")
80 lst
= ["addi 1, 0, 0x5678",
85 initial_mem
= {0x1230: (0x5432123412345678, 8),
86 0x1238: (0xabcdef0187654321, 8),
88 with
Program(lst
) as program
:
89 self
.run_tst_program(program
,
93 @unittest.skip("disable")
94 def test_ld_rev_ext(self
):
95 lst
= ["addi 1, 0, 0x5678",
100 with
Program(lst
) as program
:
101 self
.run_tst_program(program
, [1, 2, 3])
103 @unittest.skip("disable")
104 def test_st_rev_ext(self
):
105 lst
= ["addi 1, 0, 0x5678",
110 with
Program(lst
) as program
:
111 self
.run_tst_program(program
, [1, 2, 3])
113 @unittest.skip("disable")
114 def test_ldst_extended(self
):
115 lst
= ["addi 1, 0, 0x5678",
120 with
Program(lst
) as program
:
121 self
.run_tst_program(program
, [1, 2, 3])
123 @unittest.skip("disable")
124 def test_0_ldst_widths(self
):
125 lst
= ["addis 1, 0, 0xdead",
135 with
Program(lst
) as program
:
136 self
.run_tst_program(program
, [1, 2, 3, 4, 5])
138 @unittest.skip("disable")
140 lst
= ["addi 1, 0, 0x1234",
143 "subfic 4, 1, 0x1337",
145 with
Program(lst
) as program
:
146 self
.run_tst_program(program
, [1, 2, 3, 4, 5])
148 @unittest.skip("disable")
149 def test_add_with_carry(self
):
150 lst
= ["addi 1, 0, 5",
157 with
Program(lst
) as program
:
158 self
.run_tst_program(program
, [1, 2, 3])
160 @unittest.skip("disable")
161 def test_addis(self
):
162 lst
= ["addi 1, 0, 0x0FFF",
165 with
Program(lst
) as program
:
166 self
.run_tst_program(program
, [1])
168 @unittest.skip("broken")
169 def test_mulli(self
):
170 lst
= ["addi 1, 0, 3",
173 with
Program(lst
) as program
:
174 self
.run_tst_program(program
, [1])
176 def tst_2_load_store(self
):
177 lst
= ["addi 1, 0, 0x1004",
183 initial_regs
= [0] * 32
184 initial_regs
[1] = 0x1004
185 initial_regs
[2] = 0x1008
186 initial_regs
[3] = 0x00ee
187 initial_mem
= {0x1000: (0x5432123412345678, 8),
188 0x1008: (0xabcdef0187654321, 8),
189 0x1020: (0x1828384822324252, 8),
191 with
Program(lst
) as program
:
192 self
.run_tst_program(program
, [3,4], initial_mem
)
194 @unittest.skip("disable")
195 def test_3_load_store(self
):
196 lst
= ["addi 1, 0, 0x1004",
201 initial_regs
= [0] * 32
202 initial_regs
[1] = 0x1004
203 initial_regs
[2] = 0x1002
204 initial_regs
[3] = 0x15eb
205 initial_mem
= {0x1000: (0x5432123412345678, 8),
206 0x1008: (0xabcdef0187654321, 8),
207 0x1020: (0x1828384822324252, 8),
209 with
Program(lst
) as program
:
210 self
.run_tst_program(program
, [1,2,3,4], initial_mem
)
214 register unsigned long i asm ("r12");
222 lst
= ["addi 9, 0, 0x10", # i = 16
223 "addi 9,9,-1", # i = i - 1
224 "cmpi 0,1,9,12", # compare 9 to value 0, store in CR2
225 "bc 4,0,-8" # branch if CR2 "test was != 0"
227 with
Program(lst
) as program
:
228 self
.run_tst_program(program
, [9], initial_mem
={})
230 def run_tst_program(self
, prog
, reglist
, initial_mem
=None):
232 simulator
= self
.run_tst(prog
, initial_mem
=initial_mem
)
234 with
run_program(prog
, initial_mem
) as q
:
235 self
.qemu_register_compare(simulator
, q
, reglist
)
236 self
.qemu_mem_compare(simulator
, q
, reglist
)
237 print(simulator
.gpr
.dump())
239 def qemu_mem_compare(self
, sim
, qemu
, check
=True):
240 if False: # disable convenient large interesting debugging memory dump
242 qmemdump
= qemu
.get_mem(addr
, 2048)
243 for i
in range(len(qmemdump
)):
244 s
= hex(int(qmemdump
[i
]))
245 print ("qemu mem %06x %s" % (addr
+i
*8, s
))
246 for k
, v
in sim
.mem
.mem
.items():
247 qmemdump
= qemu
.get_mem(k
*8, 8)
248 s
= hex(int(qmemdump
[0]))[2:]
249 print ("qemu mem %06x %16s" % (k
*8, s
))
250 for k
, v
in sim
.mem
.mem
.items():
251 print ("sim mem %06x %016x" % (k
*8, v
))
254 for k
, v
in sim
.mem
.mem
.items():
255 qmemdump
= qemu
.get_mem(k
*8, 1)
256 self
.assertEqual(int(qmemdump
[0]), v
)
258 def qemu_register_compare(self
, sim
, qemu
, regs
):
259 qpc
, qxer
, qcr
= qemu
.get_pc(), qemu
.get_xer(), qemu
.get_cr()
260 sim_cr
= sim
.cr
.get_range().value
261 sim_pc
= sim
.pc
.CIA
.value
262 sim_xer
= sim
.spr
['XER'].value
263 print("qemu pc", hex(qpc
))
264 print("qemu cr", hex(qcr
))
265 print("qemu xer", bin(qxer
))
266 print("sim pc", hex(sim
.pc
.CIA
.value
))
267 print("sim cr", hex(sim_cr
))
268 print("sim xer", hex(sim_xer
))
269 self
.assertEqual(qcr
, sim_cr
)
271 qemu_val
= qemu
.get_register(reg
)
272 sim_val
= sim
.gpr(reg
).value
273 self
.assertEqual(qemu_val
, sim_val
)
276 if __name__
== "__main__":