src/soc/sv/svp64.py

   1 # SPDX-License-Identifier: LGPLv3+
   2 # Copyright (C) 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
   3 # Funded by NLnet http://nlnet.nl
   4 """SVP64 RM (Remap) Record.
   5
   6 https://libre-soc.org/openpower/sv/svp64/
   7
   8 | Field Name  | Field bits | Description                            |
   9 |-------------|------------|----------------------------------------|
  10 | MASKMODE    | `0`        | Execution (predication) Mask Kind      |
  11 | MASK        | `1:3`      | Execution Mask                         |
  12 | ELWIDTH     | `4:5`      | Element Width                          |
  13 | ELWIDTH_SRC | `6:7`      | Element Width for Source               |
  14 | SUBVL       | `8:9`      | Sub-vector length                      |
  15 | EXTRA       | `10:18`    | context-dependent extra                |
  16 | MODE        | `19:23`    | changes Vector behaviour               |
  17 """
  18
  19 from nmigen import Record
  20
  21
  22 # in nMigen, Record begins at the LSB and fills upwards
  23 class SVP64Rec(Record):
  24     def __init__(self, name=None):
  25         Record.__init__(self, layout=[("mode"    , 5),
  26                                       ("extra"   , 9),
  27                                       ("subvl"   , 2),
  28                                       ("ewsrc"   , 2),
  29                                       ("elwidth" , 2),
  30                                       ("mask"    , 3),
  31                                       ("mmode"   , 1)], name=name)
  32
  33     def ports(self):
  34         return [self.mmode, self.mask, self.elwidth, self.ewsrc,
  35                 self.extra, self.mode]
  36
  37 """RM Mode
  38
  39 LD/ST:
  40 00      str     sz dz   normal mode
  41 01      inv     CR-bit  Rc=1: ffirst CR sel
  42 01      inv     els RC1 Rc=0: ffirst z/nonz
  43 10      N       sz els  sat mode: N=0/1 u/s
  44 11      inv     CR-bit  Rc=1: pred-result CR sel
  45 11      inv     els RC1 Rc=0: pred-result z/nonz
  46
  47 Arithmetic:
  48 00      0       sz dz   normal mode
  49 00      1       sz CRM  reduce mode (mapreduce), SUBVL=1
  50 00      1       SVM CRM subvector reduce mode, SUBVL>1
  51 01      inv     CR-bit  Rc=1: ffirst CR sel
  52 01      inv     sz RC1  Rc=0: ffirst z/nonz
  53 10      N       sz dz   sat mode: N=0/1 u/s
  54 11      inv     CR-bit  Rc=1: pred-result CR sel
  55 11      inv     sz RC1  Rc=0: pred-result z/nonz
  56 """